Merge branch 'RT-Thread:master' into hal

.github/workflows/action.yml

@@ -35,7 +35,6 @@ jobs:
          - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}

bsp/acm32f4xx-nucleo/.ignore_format.yml

+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- libraries

bsp/essemi/es32f0271/Kconfig → bsp/acm32f4xx-nucleo/Kconfig

-mainmenu "RT-Thread Configuration"
+mainmenu "RT-Thread Project Configuration"
 
 config BSP_DIR
     string
@@ -8,7 +8,7 @@ config BSP_DIR
 config RTT_DIR
     string
     option env="RTT_ROOT"
-    default "../../.."
+    default "../.."
 
 config PKGS_DIR
     string
@@ -18,10 +18,5 @@ config PKGS_DIR
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
 
-config SOC_ES32F0271LT
-    bool
-    select RT_USING_COMPONENTS_INIT
-    select RT_USING_USER_MAIN
-    default y
+source "$BSP_DIR/drivers/Kconfig"
 
-source "drivers/Kconfig"

bsp/acm32f4xx-nucleo/README.md

+# acm32f0x0板级支持包
+
+## 1. 简介
+
+ACM32F4xx芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性：
+
+|--------------------------|--------------------|
+|         硬件             |         描述       |
+| -------------------------|--------------------|
+|芯片型号                  | ACM32F4XX系列      |
+|CPU                       | ARM Cortex-M33     |
+|主频                      | 180MHz             |
+|片内SRAM                  | 192K               |
+|片内Flash                 | 512K               |
+|--------------------------|--------------------|
+
+具体型号及资源请参考上海航芯官方网站[ACM32F4](www.aisinochip.com/index.php/product/child1/id/219.html)。
+
+## 2. 编译说明
+
+推荐使用[env工具][1]，可以在console下进入到`bsp/acm32f4xx-nucleo`目录中，运行以下命令：
+
+`scons`
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
+
+也可以通过`scons --target=mdk5`生成keil工程，再使用keil进行编译。
+
+## 3. 烧写及执行
+
+开发板的使用请参考上海航芯官方网站相应型号的[开发工具](www.aisinochip.com/index.php/product/detail/id/25.html)。
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+## 4. 驱动支持情况及计划
+
+| **片上外设**  | **支持情况** |               **备注**                |
+| ------------- | ------------ | ------------------------------------- |
+| GPIO          |     支持     | PA0, PA1... PF4 ---> PIN: 0, 1...83  |
+| UART          |     支持     |              UART1/UART2              |
+| LED           |     支持     |              LED1                     |
+
+## 5. 联系人信息
+
+维护人：AisinoChip < xiangfeng.liu@aisinochip.com >
+
+## 6. 参考
+
+* 板子[数据手册][2]
+* 芯片[数据手册][3]
+
+  [1]: https://www.rt-thread.org/page/download.html
+  [2]: www.aisinochip.com/index.php/product/detail/id/50.html
+  [3]: www.aisinochip.com/index.php/product/detail/id/50.html

bsp/essemi/es32f0334/SConscript → bsp/acm32f4xx-nucleo/SConscript

 # for module compiling
 import os
-Import('RTT_ROOT')
+from building import *
 
+cwd  = GetCurrentDir()
 objs = []
-cwd = str(Dir('#'))
 list = os.listdir(cwd)
 
 for d in list:

bsp/essemi/es32f0271/SConstruct → bsp/acm32f4xx-nucleo/SConstruct

@@ -5,29 +5,24 @@ import rtconfig
 if os.getenv('RTT_ROOT'):
     RTT_ROOT = os.getenv('RTT_ROOT')
 else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
 
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-try:
-    from building import *
-except:
-    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
-    print(RTT_ROOT)
-    exit(-1)
+from building import *
 
-TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+TARGET = 'rtthread_acm32f4xx.' + rtconfig.TARGET_EXT
 
 env = Environment(tools = ['mingw'],
-    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-    AR = rtconfig.AR, ARFLAGS = '-rc',
-    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 
 if rtconfig.PLATFORM == 'iar':
-    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
-    env.Replace(ARFLAGS = [''])
-    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
 
 Export('RTT_ROOT')
 Export('rtconfig')

bsp/essemi/es32f0271/applications/SConscript → bsp/acm32f4xx-nucleo/applications/SConscript

@@ -2,10 +2,10 @@ Import('RTT_ROOT')
 Import('rtconfig')
 from building import *
 
-cwd     = os.path.join(str(Dir('#')), 'applications')
-src	= Glob('*.c')
-
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
 CPPPATH = [cwd, str(Dir('#'))]
+
 group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')

bsp/acm32f4xx-nucleo/applications/main.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-17     AisinoChip   the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include <drivers/pin.h>
+
+#define LED_PIN_NUM    83     /* PF3 */
+
+int main(void)
+{
+    rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN_NUM, PIN_LOW);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
+        rt_pin_write(LED_PIN_NUM, PIN_HIGH);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
+    }
+}

bsp/acm32f4xx-nucleo/drivers/Kconfig

+menu "Hardware Drivers Config"
+
+choice
+    prompt "select chip type"
+    default SOC_ACM32F403RET7
+
+    config SOC_ACM32F403KCU7
+    bool "SOC_ACM32F403KCU7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403KEU7
+    bool "SOC_ACM32F403KEU7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403CCT7
+    bool "SOC_ACM32F403CCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403CET7
+    bool "SOC_ACM32F403CET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403RCT7
+    bool "SOC_ACM32F403RCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403RET7
+    bool "SOC_ACM32F403RET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403VCT7
+    bool "SOC_ACM32F403VCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403VET7
+    bool "SOC_ACM32F403VET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+endchoice
+
+menu "ACM32F403RET7"
+    depends on SOC_ACM32F403RET7
+
+    config SOC_SRAM_START_ADDR
+        hex "sram start address"
+        default 0x20000000
+
+    config SOC_SRAM_SIZE
+        hex "sram size(KBytes)"
+        default 0xC0
+
+    config SOC_FLASH_START_ADDR
+        hex "EFlash Start Address"
+        default 0x00000000
+
+    config SOC_FLASH_SIZE
+        hex "EFlash Size(KBytes)"
+        default 0x8000
+endmenu
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    menu "Hardware GPIO"
+        config BSP_USING_GPIO1
+            bool "Enable GPIOAB"
+            default y
+            select RT_USING_PIN
+        config BSP_USING_GPIO2
+            bool "Enable GPIOCD"
+            default y
+            select RT_USING_PIN
+        config BSP_USING_GPIO3
+            bool "Enable GPIOEF"
+            default y
+            select RT_USING_PIN
+    endmenu
+
+    config BSP_USING_ADC
+        bool "Enable ADC"
+        select RT_USING_ADC
+        default n
+
+    config BSP_USING_DAC
+        bool "Enable DAC"
+        select RT_USING_DAC
+        default n
+
+    menu "Hardware UART"
+        config BSP_USING_UART1
+            bool "Enable UART1 (PA9/PA10)"
+            default y
+            select RT_USING_SERIAL
+
+        config BSP_USING_UART2
+            bool "Enable UART2 (PA2/PA3)"
+            default y
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART2
+            config BSP_UART2_RX_USING_DMA
+                bool "Enable UART2 RX DMA"
+                depends on BSP_USING_UART2
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART2_TX_USING_DMA
+                bool "Enable UART2 TX DMA"
+                depends on BSP_USING_UART2
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+
+        config BSP_USING_UART3
+            bool "Enable UART3 (PC4/PC5)"
+            default n
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART3
+            config BSP_UART3_RX_USING_DMA
+                bool "Enable UART3 RX DMA"
+                depends on BSP_USING_UART3
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART3_TX_USING_DMA
+                bool "Enable UART3 TX DMA"
+                depends on BSP_USING_UART3
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+
+        config BSP_USING_UART4
+            bool "Enable UART4 (PC11/PC10)"
+            default n
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART4
+            config BSP_UART4_RX_USING_DMA
+                bool "Enable UART4 RX DMA"
+                depends on BSP_USING_UART4
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART4_TX_USING_DMA
+                bool "Enable UART4 TX DMA"
+                depends on BSP_USING_UART4
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+    endmenu
+
+    config BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+
+    config BSP_USING_LPUART
+        bool "Enable LPUART"
+        select RT_USING_UART
+        default n
+
+    menu "Hardware I2C"
+        config BSP_USING_I2C1
+            bool "Enable I2C1"
+            default n
+            select RT_USING_I2C
+        config BSP_USING_I2C2
+            bool "Enable I2C2"
+            default n
+            select RT_USING_I2C
+    endmenu
+
+    menu "Hardware I2S"
+        config BSP_USING_I2S1
+            bool "Enable I2S1"
+            default n
+            select RT_USING_I2S
+    endmenu
+
+    menu "Hardware CAN"
+        config BSP_USING_CAN1
+            bool "Enable CAN1"
+            default n
+            select RT_USING_CAN
+        config BSP_USING_CAN2
+            bool "Enable CAN2"
+            default n
+            select RT_USING_CAN
+    endmenu
+
+    menu "Hardware TIMER"
+        config BSP_USING_TIM1
+            bool "Enable Timer1"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM2
+            bool "Enable Timer2"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM3
+            bool "Enable Timer3"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM4
+            bool "Enable Timer4"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM6
+            bool "Enable Timer6"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM7
+            bool "Enable Timer7"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM14
+            bool "Enable Timer14"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM15
+            bool "Enable Timer15"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM16
+            bool "Enable Timer16"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM17
+            bool "Enable Timer17"
+            default n
+            select RT_USING_HWTIMER
+    endmenu
+
+    menu "Hardware WDT"
+        config BSP_USING_WDT
+            bool "Enable Watch Dog Timer"
+            default n
+            select RT_USING_WDT
+        config BSP_USING_IWDT
+            bool "Enable Independent Watch Dog Timer"
+            default n
+            select RT_USING_WDT
+    endmenu
+
+    config BSP_USING_LCD
+        bool "Enable LCD"
+        default n
+
+    menu "Hardware SPI"
+        config BSP_USING_SPI1
+            bool "Enable SPI1"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI1
+            config BSP_SPI1_RX_USING_DMA
+                bool "Enable SPI1 RX DMA"
+                default n
+
+            config BSP_SPI1_TX_USING_DMA
+                bool "Enable SPI1 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI2
+            bool "Enable SPI2"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI2
+            config BSP_SPI2_RX_USING_DMA
+                bool "Enable SPI2 RX DMA"
+                default n
+
+            config BSP_SPI2_TX_USING_DMA
+                bool "Enable SPI2 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI3
+            bool "Enable SPI3"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI3
+            config BSP_SPI3_RX_USING_DMA
+                bool "Enable SPI3 RX DMA"
+                default n
+
+            config BSP_SPI3_TX_USING_DMA
+                bool "Enable SPI3 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI4
+            bool "Enable SPI4"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI4
+            config BSP_SPI4_RX_USING_DMA
+                bool "Enable SPI4 RX DMA"
+                default n
+
+            config BSP_SPI4_TX_USING_DMA
+                bool "Enable SPI4 TX DMA"
+                default n
+        endif
+    endmenu
+
+    menu "Hardware CRYPTO"
+        config BSP_USING_CRC
+            select RT_HWCRYPTO_USING_CRC
+            bool "Enable CRC"
+            default n
+            select RT_USING_HWCRYPTO
+        config BSP_USING_AES
+            select RT_HWCRYPTO_USING_AES
+            bool "Enable AES"
+            default n
+            select RT_USING_HWCRYPTO
+
+        config BSP_USING_HRNG
+            select RT_HWCRYPTO_USING_RNG
+            bool "Enable HRNG"
+            default n
+            select RT_USING_HWCRYPTO
+    endmenu
+
+    config BSP_USING_CMP
+        bool "Enable Analog Voltage Comparer"
+        default n
+
+    config BSP_USING_OPA
+        bool "Enable Operational Amplifier"
+        default n
+
+    config BSP_USING_TKEY
+        bool "Enable Touch Key"
+        select RT_USING_TOUCH
+        default n
+
+    config BSP_USING_RPMU
+        bool "Enable RTC PMU"
+        select RT_USING_PM
+        default n
+
+    config BSP_USING_USBD
+        bool "Enable USB Device"
+        select RT_USING_USB
+        default n
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
+

bsp/essemi/es8p508x/applications/SConscript → bsp/acm32f4xx-nucleo/drivers/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
 from building import *
 
 cwd = GetCurrentDir()
 src = Glob('*.c')
-
 CPPPATH = [cwd]
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
+

bsp/acm32f4xx-nucleo/drivers/board.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-25     AisinoChip   first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include <rtdevice.h>
+
+#define SOC_SRAM_END_ADDR   (SOC_SRAM_START_ADDR+SOC_SRAM_SIZE*1024)
+
+extern int  rt_application_init(void);
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+    #pragma section="HEAP"
+#else
+    extern int __bss_end;
+#endif
+
+extern void rt_hw_uart_init(void);
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial EVB board.
+ */
+void rt_hw_board_init(void)
+{
+    /* system init, clock, NVIC */
+    System_Init();
+
+    /* Configure the SysTick */
+    SysTick_Config(System_Get_SystemClock() / RT_TICK_PER_SECOND);
+
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#ifdef RT_USING_HEAP
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SOC_SRAM_END_ADDR);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void *)SOC_SRAM_END_ADDR);
+#else
+    /* init memory system */
+    rt_system_heap_init((void *)&__bss_end, (void *)SOC_SRAM_END_ADDR);
+#endif
+#endif /* RT_USING_HEAP */
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+

bsp/acm32f4xx-nucleo/drivers/board.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-22     AisinoCip    add board.h to this bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtconfig.h>
+#include "ACM32Fxx_HAL.h"
+
+/*-------------------------- UART CONFIG BEGIN --------------------------*/
+
+/** After configuring corresponding UART or UART DMA, you can use it.
+  *
+  * STEP 1, define macro define related to the serial port opening based on the serial port number
+  *                 such as     #define BSP_USING_UATR1
+  *
+  * STEP 2, according to the corresponding pin of serial port, modify the related serial port information
+  *                 such as     #define UART1_TX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_RX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_TX_PIN        GPIO_PIN_X   ->   GPIO_PIN_9
+  *                             #define UART1_RX_PIN        GPIO_PIN_X   ->   GPIO_PIN_10
+  *
+  * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
+  *                 RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
+  *
+  * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
+  *                 such as     #define BSP_UART1_RX_USING_DMA
+  *
+  */
+
+#if defined(BSP_USING_UART1)
+    #define UART1_TX_PORT           GPIOA
+    #define UART1_RX_PORT           GPIOA
+    #define UART1_TX_PIN            GPIO_PIN_9
+    #define UART1_RX_PIN            GPIO_PIN_10
+
+    #if defined(BSP_UART1_RX_USING_DMA)
+        #define UART1_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART1_RX_DMA_RCC        BIT12
+        #define UART1_RX_DMA_IRQ        DMA_IRQn
+        #define UART1_RX_DMA_CHANNEL    0
+        #define UART1_RX_DMA_REQUEST    REQ6_UART1_RECV
+    #endif /* BSP_UART1_RX_USING_DMA */
+
+    #if defined(BSP_UART1_TX_USING_DMA)
+        #define UART1_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART1_TX_DMA_RCC        BIT12
+        #define UART1_TX_DMA_IRQ        DMA_IRQn
+        #define UART1_TX_DMA_CHANNEL    1
+        #define UART1_TX_DMA_REQUEST    REQ5_UART1_SEND
+    #endif /* BSP_UART1_TX_USING_DMA */
+
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+    #define UART2_TX_PORT           GPIOA
+    #define UART2_RX_PORT           GPIOA
+    #define UART2_TX_PIN            GPIO_PIN_2
+    #define UART2_RX_PIN            GPIO_PIN_3
+
+    #if defined(BSP_UART2_RX_USING_DMA)
+        #define UART2_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART2_RX_DMA_RCC        BIT12
+        #define UART2_RX_DMA_IRQ        DMA_IRQn
+        #define UART2_RX_DMA_CHANNEL    0
+        #define UART2_RX_DMA_REQUEST    REQ8_UART2_RECV
+    #endif /* BSP_UART2_RX_USING_DMA */
+
+    #if defined(BSP_UART2_TX_USING_DMA)
+        #define UART2_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART2_TX_DMA_RCC        BIT12
+        #define UART2_TX_DMA_IRQ        DMA_IRQn
+        #define UART2_TX_DMA_CHANNEL    1
+        #define UART2_TX_DMA_REQUEST    REQ7_UART2_SEND
+    #endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+    #define UART3_TX_PORT           GPIOB
+    #define UART3_RX_PORT           GPIOB
+    #define UART3_TX_PIN            GPIO_PIN_10
+    #define UART3_RX_PIN            GPIO_PIN_11
+
+    #if defined(BSP_UART3_RX_USING_DMA)
+        #define UART3_RX_DMA_INSTANCE   DMA_Channel2
+        #define UART3_RX_DMA_RCC        BIT12
+        #define UART3_RX_DMA_IRQ        DMA_IRQn
+        #define UART3_RX_DMA_CHANNEL    2
+        #define UART3_RX_DMA_REQUEST    REQ29_UART3_RECV
+    #endif /* BSP_UART3_RX_USING_DMA */
+
+    #if defined(BSP_UART3_TX_USING_DMA)
+        #define UART3_TX_DMA_INSTANCE   DMA_Channel3
+        #define UART3_TX_DMA_RCC        BIT12
+        #define UART3_TX_DMA_IRQ        DMA_IRQn
+        #define UART3_TX_DMA_CHANNEL    3
+        #define UART3_TX_DMA_REQUEST    REQ27_UART3_SEND
+    #endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+    #define UART4_TX_PORT           GPIOC
+    #define UART4_RX_PORT           GPIOC
+    #define UART4_TX_PIN            GPIO_PIN_10
+    #define UART4_RX_PIN            GPIO_PIN_11
+
+    #if defined(BSP_UART4_RX_USING_DMA)
+        #define UART4_RX_DMA_INSTANCE   DMA_Channel4
+        #define UART4_RX_DMA_RCC        BIT12
+        #define UART4_RX_DMA_IRQ        DMA_IRQn
+        #define UART4_RX_DMA_CHANNEL    4
+        #define UART4_RX_DMA_REQUEST    REQ46_UART4_RECV
+    #endif /* BSP_UART4_RX_USING_DMA */
+
+    #if defined(BSP_UART4_TX_USING_DMA)
+        #define UART4_TX_DMA_INSTANCE   DMA_Channel5
+        #define UART4_TX_DMA_RCC        BIT12
+        #define UART4_TX_DMA_IRQ        DMA_IRQn
+        #define UART4_TX_DMA_CHANNEL    5
+        #define UART4_TX_DMA_REQUEST    REQ45_UART4_SEND
+    #endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+/*-------------------------- UART CONFIG END --------------------------*/
+
+/* board configuration */
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
+

bsp/essemi/es8p508x/drivers/drv_gpio.c → bsp/acm32f4xx-nucleo/drivers/drv_gpio.c

 /*
- * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author        Notes
- * 2019-07-11     wangyq        the first version
+ * Date           Author            Notes
+ * 2021-09-18     AisinoChip        first version
  */
 
 #include <rthw.h>
 #include <rtdevice.h>
 #include "board.h"
-#include "drv_gpio.h"
-#include <lib_scu.h>
-#include <lib_gpio.h>
 
 #ifdef RT_USING_PIN
 
-#define __ES8P_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_Pin_##gpio_index}
-#define __ES8P_PIN_DEFAULT {-1, GPIOA, GPIO_Pin_0}
+#define __ACM32_PIN(index, gpio, gpio_index)                                \
+    {                                                                       \
+        index, GPIO##gpio, GPIO_PIN_##gpio_index                            \
+    }
+
+#define __ACM32_PIN_RESERVE                                                 \
+    {                                                                       \
+        -1, 0, 0                                                            \
+    }
 
-/* es8p GPIO driver */
+/* ACM32 GPIO driver */
 struct pin_index
 {
-    int index;
-    GPIO_TYPE gpio;
-    GPIO_TYPE_PIN pin;
+    int             index;
+    enum_GPIOx_t    gpio;
+    uint32_t        pin;
 };
 
-static const struct pin_index pins[] =
+struct pin_irq_map
 {
-    __ES8P_PIN_DEFAULT,
-    __ES8P_PIN(1, B, 0),
-    __ES8P_PIN(2, B, 1),
-    __ES8P_PIN(3, B, 2),
-    __ES8P_PIN(4, B, 3),
-    __ES8P_PIN(5, B, 4),
-    __ES8P_PIN(6, B, 5),
-    __ES8P_PIN(7, B, 6),
-    __ES8P_PIN(8, B, 7),
-    __ES8P_PIN(9, B, 8),
-    __ES8P_PIN(10, B, 9),
-    __ES8P_PIN(11, B, 10),
-    __ES8P_PIN(12, B, 11),
-    __ES8P_PIN(13, B, 12),
-    __ES8P_PIN(14, B, 13),
-    __ES8P_PIN(15, A, 0),
-    __ES8P_PIN(16, A, 1),
-    __ES8P_PIN(17, A, 2),
-    __ES8P_PIN(18, A, 3),
-    __ES8P_PIN(19, A, 4),
-    __ES8P_PIN(20, A, 5),
-    __ES8P_PIN(21, A, 6),
-    __ES8P_PIN(22, A, 7),
-    __ES8P_PIN(23, A, 8),
-    __ES8P_PIN(24, A, 9),
-    __ES8P_PIN(25, A, 10),
-    __ES8P_PIN(26, A, 11),
-    __ES8P_PIN(27, A, 12),
-    __ES8P_PIN(28, A, 13),
-    __ES8P_PIN(29, A, 14),
-    __ES8P_PIN(30, A, 15),
-    __ES8P_PIN(31, A, 16),
-    __ES8P_PIN_DEFAULT,
-    __ES8P_PIN_DEFAULT,
-    __ES8P_PIN(34, A, 17),
-    __ES8P_PIN(35, A, 18),
-    __ES8P_PIN_DEFAULT,
-    __ES8P_PIN(37, A, 20),
-    __ES8P_PIN(38, A, 21),
-    __ES8P_PIN(39, A, 22),
-    __ES8P_PIN(40, A, 23),
-    __ES8P_PIN(41, A, 24),
-    __ES8P_PIN(42, A, 25),
-    __ES8P_PIN(43, A, 26),
-    __ES8P_PIN(44, A, 27),
-    __ES8P_PIN(45, A, 28),
-    __ES8P_PIN(46, A, 29),
-    __ES8P_PIN(47, A, 30),
-    __ES8P_PIN(48, A, 31),
+    rt_uint16_t         line;
+    EXTI_HandleTypeDef  handle;
 };
 
-struct irq_map
+static const struct pin_index pins[] =
 {
-    PINT_TYPE pinno;
-    IRQn_Type irqno;
+#if defined(BSP_USING_GPIO1)
+    __ACM32_PIN(0,   A, 0),
+    __ACM32_PIN(1,   A, 1),
+    __ACM32_PIN(2,   A, 2),
+    __ACM32_PIN(3,   A, 3),
+    __ACM32_PIN(4,   A, 4),
+    __ACM32_PIN(5,   A, 5),
+    __ACM32_PIN(6,   A, 6),
+    __ACM32_PIN(7,   A, 7),
+    __ACM32_PIN(8,   A, 8),
+    __ACM32_PIN(9,   A, 9),
+    __ACM32_PIN(10,  A, 10),
+    __ACM32_PIN(11,  A, 11),
+    __ACM32_PIN(12,  A, 12),
+    __ACM32_PIN(13,  A, 13),
+    __ACM32_PIN(14,  A, 14),
+    __ACM32_PIN(15,  A, 15),
+    __ACM32_PIN(16,  B, 0),
+    __ACM32_PIN(17,  B, 1),
+    __ACM32_PIN(18,  B, 2),
+    __ACM32_PIN(19,  B, 3),
+    __ACM32_PIN(20,  B, 4),
+    __ACM32_PIN(21,  B, 5),
+    __ACM32_PIN(22,  B, 6),
+    __ACM32_PIN(23,  B, 7),
+    __ACM32_PIN(24,  B, 8),
+    __ACM32_PIN(25,  B, 9),
+    __ACM32_PIN(26,  B, 10),
+    __ACM32_PIN(27,  B, 11),
+    __ACM32_PIN(28,  B, 12),
+    __ACM32_PIN(29,  B, 13),
+    __ACM32_PIN(30,  B, 14),
+    __ACM32_PIN(31,  B, 15),
+#if defined(BSP_USING_GPIO2)
+    __ACM32_PIN(32,  C, 0),
+    __ACM32_PIN(33,  C, 1),
+    __ACM32_PIN(34,  C, 2),
+    __ACM32_PIN(35,  C, 3),
+    __ACM32_PIN(36,  C, 4),
+    __ACM32_PIN(37,  C, 5),
+    __ACM32_PIN(38,  C, 6),
+    __ACM32_PIN(39,  C, 7),
+    __ACM32_PIN(40,  C, 8),
+    __ACM32_PIN(41,  C, 9),
+    __ACM32_PIN(42,  C, 10),
+    __ACM32_PIN(43,  C, 11),
+    __ACM32_PIN(44,  C, 12),
+    __ACM32_PIN(45,  C, 13),
+    __ACM32_PIN(46,  C, 14),
+    __ACM32_PIN(47,  C, 15),
+    __ACM32_PIN(48,  D, 0),
+    __ACM32_PIN(49,  D, 1),
+    __ACM32_PIN(50,  D, 2),
+    __ACM32_PIN(51,  D, 3),
+    __ACM32_PIN(52,  D, 4),
+    __ACM32_PIN(53,  D, 5),
+    __ACM32_PIN(54,  D, 6),
+    __ACM32_PIN(55,  D, 7),
+    __ACM32_PIN(56,  D, 8),
+    __ACM32_PIN(57,  D, 9),
+    __ACM32_PIN(58,  D, 10),
+    __ACM32_PIN(59,  D, 11),
+    __ACM32_PIN(60,  D, 12),
+    __ACM32_PIN(61,  D, 13),
+    __ACM32_PIN(62,  D, 14),
+    __ACM32_PIN(63,  D, 15),
+#if defined(BSP_USING_GPIO3)
+    __ACM32_PIN(64,  E, 0),
+    __ACM32_PIN(65,  E, 1),
+    __ACM32_PIN(66,  E, 2),
+    __ACM32_PIN(67,  E, 3),
+    __ACM32_PIN(68,  E, 4),
+    __ACM32_PIN(69,  E, 5),
+    __ACM32_PIN(70,  E, 6),
+    __ACM32_PIN(71,  E, 7),
+    __ACM32_PIN(72,  E, 8),
+    __ACM32_PIN(73,  E, 9),
+    __ACM32_PIN(74,  E, 10),
+    __ACM32_PIN(75,  E, 11),
+    __ACM32_PIN(76,  E, 12),
+    __ACM32_PIN(77,  E, 13),
+    __ACM32_PIN(78,  E, 14),
+    __ACM32_PIN(79,  E, 15),
+    __ACM32_PIN(80,  F, 0),
+    __ACM32_PIN(81,  F, 1),
+    __ACM32_PIN(82,  F, 2),
+    __ACM32_PIN(83,  F, 3),
+    __ACM32_PIN(84,  F, 4),
+#endif /* defined(BSP_USING_GPIO3) */
+#endif /* defined(BSP_USING_GPIO2) */
+#endif /* defined(BSP_USING_GPIO1) */
 };
-static const struct irq_map irq_map[] =
+
+static struct pin_irq_map pin_irq_map[] =
 {
-    {PINT0, PINT0_IRQn},
-    {PINT1, PINT1_IRQn},
-    {PINT2, PINT2_IRQn},
-    {PINT3, PINT3_IRQn},
-    {PINT4, PINT4_IRQn},
-    {PINT5, PINT5_IRQn},
-    {PINT6, PINT6_IRQn},
-    {PINT7, PINT7_IRQn},
+    {EXTI_LINE_0,  {0}},
+    {EXTI_LINE_1,  {0}},
+    {EXTI_LINE_2,  {0}},
+    {EXTI_LINE_3,  {0}},
+    {EXTI_LINE_4,  {0}},
+    {EXTI_LINE_5,  {0}},
+    {EXTI_LINE_6,  {0}},
+    {EXTI_LINE_7,  {0}},
+    {EXTI_LINE_8,  {0}},
+    {EXTI_LINE_9,  {0}},
+    {EXTI_LINE_10, {0}},
+    {EXTI_LINE_11, {0}},
+    {EXTI_LINE_12, {0}},
+    {EXTI_LINE_13, {0}},
+    {EXTI_LINE_14, {0}},
+    {EXTI_LINE_15, {0}},
 };
 
-struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
 {
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
@@ -108,12 +163,22 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
 };
+static uint32_t pin_irq_enable_mask = 0;
 
 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
-const struct pin_index *get_pin(uint8_t pin)
+static const struct pin_index *get_pin(uint8_t pin)
 {
     const struct pin_index *index;
+
     if (pin < ITEM_NUM(pins))
     {
         index = &pins[pin];
@@ -124,52 +189,46 @@ const struct pin_index *get_pin(uint8_t pin)
     {
         index = RT_NULL;
     }
+
     return index;
 };
 
-void es8p_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
 {
     const struct pin_index *index;
+
     index = get_pin(pin);
     if (index == RT_NULL)
     {
         return;
     }
 
-    if (value == 0)
-    {
-        if (index->gpio == GPIOA)
-            GPIOA_ResetBit(index->pin);
-        else if (index->gpio == GPIOB)
-            GPIOB_ResetBit(index->pin);
-    }
-    else
-    {
-        if (index->gpio == GPIOA)
-            GPIOA_SetBit(index->pin);
-        else if (index->gpio == GPIOB)
-            GPIOB_SetBit(index->pin);
-    }
+    HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value);
 }
 
-int es8p_pin_read(rt_device_t dev, rt_base_t pin)
+static int _pin_read(rt_device_t dev, rt_base_t pin)
 {
     int value;
     const struct pin_index *index;
+
     value = PIN_LOW;
+
     index = get_pin(pin);
     if (index == RT_NULL)
     {
         return value;
     }
-    value = GPIO_ReadBit(index->gpio, index->pin);
+
+    value = HAL_GPIO_ReadPin(index->gpio, index->pin);
+
     return value;
 }
 
-void es8p_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
     const struct pin_index *index;
-    GPIO_InitStruType gpio_initstruct;
+    GPIO_InitTypeDef GPIO_InitStruct;
+
     index = get_pin(pin);
     if (index == RT_NULL)
     {
@@ -177,69 +236,66 @@ void es8p_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     }
 
     /* Configure GPIO_InitStructure */
-    gpio_initstruct.GPIO_Signal = GPIO_Pin_Signal_Digital;
-    gpio_initstruct.GPIO_Func = GPIO_Func_0;
-    gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Disable;
-    gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Disable;
-    gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable;
-    gpio_initstruct.GPIO_DS = GPIO_DS_Output_Normal;
+    GPIO_InitStruct.Pin = index->pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
 
     if (mode == PIN_MODE_OUTPUT)
     {
         /* output setting */
-        gpio_initstruct.GPIO_Direction = GPIO_Dir_Out;
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
     }
     else if (mode == PIN_MODE_INPUT)
     {
         /* input setting: not pull. */
-        gpio_initstruct.GPIO_Direction = GPIO_Dir_In;
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
     }
     else if (mode == PIN_MODE_INPUT_PULLUP)
     {
         /* input setting: pull up. */
-        gpio_initstruct.GPIO_Direction = GPIO_Dir_In;
-        gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Enable;
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_PULLUP;
     }
     else if (mode == PIN_MODE_INPUT_PULLDOWN)
     {
         /* input setting: pull down. */
-        gpio_initstruct.GPIO_Direction = GPIO_Dir_In;
-        gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Enable;
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_PULLDOWN;
     }
     else if (mode == PIN_MODE_OUTPUT_OD)
     {
         /* output setting: od. */
-        gpio_initstruct.GPIO_Direction = GPIO_Dir_Out;
-        gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Enable;
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
     }
-    GPIO_Init(index->gpio, index->pin, &gpio_initstruct);
+
+    /* special PIN process */
+    __HAL_RTC_PC13_DIGIT();
+
+    HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
 }
 
-rt_inline const struct irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
-{
-    rt_int32_t mapindex = gpio_pin & 0x00FF;
-    if (mapindex < 0 || mapindex >= 32)
-    {
-        return RT_NULL;
-    }
-    return &irq_map[mapindex % 8];
-};
+#define     PIN2INDEX(pin)      ((pin) % 16)
 
-rt_err_t es8p_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                             rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
-    rt_int32_t irqindex;
+    rt_int32_t irqindex = -1;
+
     index = get_pin(pin);
     if (index == RT_NULL)
     {
         return RT_ENOSYS;
     }
 
-    irqindex = index->pin % 8;
-    level = rt_hw_interrupt_disable();
+    irqindex = PIN2INDEX(pin);
 
+    level = rt_hw_interrupt_disable();
     if (pin_irq_hdr_tab[irqindex].pin == pin &&
             pin_irq_hdr_tab[irqindex].hdr == hdr &&
             pin_irq_hdr_tab[irqindex].mode == mode &&
@@ -248,6 +304,7 @@ rt_err_t es8p_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
         rt_hw_interrupt_enable(level);
         return RT_EOK;
     }
+
     if (pin_irq_hdr_tab[irqindex].pin != -1)
     {
         rt_hw_interrupt_enable(level);
@@ -263,19 +320,21 @@ rt_err_t es8p_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-rt_err_t es8p_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t _pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
     rt_int32_t irqindex = -1;
+
     index = get_pin(pin);
     if (index == RT_NULL)
     {
         return RT_ENOSYS;
     }
-    irqindex = index->pin % 8;
-    level = rt_hw_interrupt_disable();
 
+    irqindex = PIN2INDEX(pin);
+
+    level = rt_hw_interrupt_disable();
     if (pin_irq_hdr_tab[irqindex].pin == -1)
     {
         rt_hw_interrupt_enable(level);
@@ -286,194 +345,135 @@ rt_err_t es8p_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     pin_irq_hdr_tab[irqindex].mode = 0;
     pin_irq_hdr_tab[irqindex].args = RT_NULL;
     rt_hw_interrupt_enable(level);
+
     return RT_EOK;
 }
 
-rt_err_t es8p_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                             rt_uint32_t enabled)
+static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                     rt_uint32_t enabled)
 {
     const struct pin_index *index;
-    const struct irq_map *irqmap;
+    struct pin_irq_map *irqmap;
     rt_base_t level;
     rt_int32_t irqindex = -1;
-    /* Configure GPIO_InitStructure */
-    GPIO_InitStruType gpio_initstruct;
+    GPIO_InitTypeDef GPIO_InitStruct;
 
     index = get_pin(pin);
     if (index == RT_NULL)
     {
         return RT_ENOSYS;
     }
+
+    irqindex = PIN2INDEX(pin);
+    irqmap = &pin_irq_map[irqindex];
+
     if (enabled == PIN_IRQ_ENABLE)
     {
-        irqindex = pin % 8;
         level = rt_hw_interrupt_disable();
+
         if (pin_irq_hdr_tab[irqindex].pin == -1)
         {
             rt_hw_interrupt_enable(level);
             return RT_ENOSYS;
         }
-        irqmap = &irq_map[irqindex];
 
         /* Configure GPIO_InitStructure */
-        gpio_initstruct.GPIO_Signal = GPIO_Pin_Signal_Digital;
-        gpio_initstruct.GPIO_Func = GPIO_Func_0;
-        gpio_initstruct.GPIO_Direction = GPIO_Dir_In;
-        gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Disable;
-        gpio_initstruct.GPIO_DS = GPIO_DS_Output_Normal;
+        GPIO_InitStruct.Pin = index->pin;
+        GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+
+        irqmap->handle.u32_Line = irqmap->line;
+        irqmap->handle.u32_Mode = EXTI_MODE_INTERRUPT;
 
         switch (pin_irq_hdr_tab[irqindex].mode)
         {
         case PIN_IRQ_MODE_RISING:
-            gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Disable;
-            gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Enable;
-            if (index->gpio == GPIOA)
-                PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)(pin >> 3), PINT_Trig_Rise);
-            else
-                PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)((pin >> 3) + 4), PINT_Trig_Rise);
+            GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING;
             break;
-
         case PIN_IRQ_MODE_FALLING:
-            gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Enable;
-            gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable;
-            if (index->gpio == GPIOA)
-                PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)(pin >> 3), PINT_Trig_Fall);
-            else
-                PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)((pin >> 3) + 4), PINT_Trig_Fall);
+            GPIO_InitStruct.Pull = GPIO_PULLUP;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_FALLING;
             break;
-
         case PIN_IRQ_MODE_RISING_FALLING:
-            gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Disable;
-            gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable;
-            if (index->gpio == GPIOA)
-                PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)(pin >> 3), PINT_Trig_Change);
-            else
-                PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)((pin >> 3) + 4), PINT_Trig_Change);
-            break;
-
-        default:
+            GPIO_InitStruct.Pull = GPIO_NOPULL;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING_FALLING;
             break;
         }
-        GPIO_Init(index->gpio, index->pin, &gpio_initstruct);
-        NVIC_EnableIRQ(irqmap->irqno);
+        HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
+
+        irqmap->handle.u32_GPIOSel = pin / 16;
+
+        HAL_EXTI_SetConfigLine(&irqmap->handle);
+
+        pin_irq_enable_mask |= 1 << irqindex;
+
         rt_hw_interrupt_enable(level);
     }
     else if (enabled == PIN_IRQ_DISABLE)
     {
-        irqmap = get_pin_irq_map(index->pin);
-        if (irqmap == RT_NULL)
+        if ((pin_irq_enable_mask & (1 << irqindex)) == 0)
         {
             return RT_ENOSYS;
         }
-        NVIC_DisableIRQ(irqmap->irqno);
+
+        level = rt_hw_interrupt_disable();
+
+        EXTI->IENR &= ~irqmap->line;
+        EXTI->EENR &= ~irqmap->line;
+
+        rt_hw_interrupt_enable(level);
     }
     else
     {
-        return RT_ENOSYS;
+        return -RT_ENOSYS;
     }
+
     return RT_EOK;
 }
 
-const static struct rt_pin_ops _es8p_pin_ops =
+const static struct rt_pin_ops _acm32_pin_ops =
 {
-    es8p_pin_mode,
-    es8p_pin_write,
-    es8p_pin_read,
-    es8p_pin_attach_irq,
-    es8p_pin_detach_irq,
-    es8p_pin_irq_enable,
-    RT_NULL,
+    _pin_mode,
+    _pin_write,
+    _pin_read,
+    _pin_attach_irq,
+    _pin_dettach_irq,
+    _pin_irq_enable,
 };
 
-int rt_hw_pin_init(void)
+rt_inline void pin_irq_hdr(int irqno)
 {
-    int result;
-    SCU_GPIOCLK_Enable();
-    result = rt_device_pin_register("pin", &_es8p_pin_ops, RT_NULL);
-    return result;
-}
-INIT_BOARD_EXPORT(rt_hw_pin_init);
-
-rt_inline void pin_irq_hdr(PINT_TYPE_IT GPIO_Pin)
-{
-    uint16_t irqno;
-    /* pin no. convert to dec no. */
-    for (irqno = 0; irqno < 16; irqno++)
-    {
-        if ((0x01 << irqno) == GPIO_Pin)
-        {
-            break;
-        }
-    }
     if (pin_irq_hdr_tab[irqno].hdr)
     {
         pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
     }
 }
 
-rt_inline void GPIO_EXTI_Callback(PINT_TYPE_IT GPIO_Pin)
-{
-    if (PINT_GetIFStatus(GPIO_Pin) != RESET)
-    {
-        PINT_ClearITPendingBit(GPIO_Pin);
-        pin_irq_hdr(GPIO_Pin);
-    }
-}
-
-void PINT0_IRQHandler(void)
-{
-    rt_interrupt_enter();
-    GPIO_EXTI_Callback(PINT_IT_PINT0);
-    rt_interrupt_leave();
-}
-
-void PINT1_IRQHandler(void)
-{
-    rt_interrupt_enter();
-    GPIO_EXTI_Callback(PINT_IT_PINT1);
-    rt_interrupt_leave();
-}
-
-void PINT2_IRQHandler(void)
-{
-    rt_interrupt_enter();
-    GPIO_EXTI_Callback(PINT_IT_PINT2);
-    rt_interrupt_leave();
-}
-
-void PINT3_IRQHandler(void)
+int rt_hw_pin_init(void)
 {
-    rt_interrupt_enter();
-    GPIO_EXTI_Callback(PINT_IT_PINT3);
-    rt_interrupt_leave();
+    return rt_device_pin_register("pin", &_acm32_pin_ops, RT_NULL);
 }
+INIT_BOARD_EXPORT(rt_hw_pin_init);
 
-void PINT4_IRQHandler(void)
+void EXTI_IRQHandler(void)
 {
+    /* enter interrupt */
     rt_interrupt_enter();
-    GPIO_EXTI_Callback(PINT_IT_PINT4);
-    rt_interrupt_leave();
-}
 
-void PINT5_IRQHandler(void)
-{
-    rt_interrupt_enter();
-    GPIO_EXTI_Callback(PINT_IT_PINT5);
-    rt_interrupt_leave();
-}
+    for (int i = 0; i < 16; i++)
+    {
+        if (EXTI->PDR & pin_irq_map[i].line)
+        {
+            EXTI->PDR = pin_irq_map[i].line;
+            pin_irq_hdr(i);
+            break;
+        }
+    }
 
-void PINT6_IRQHandler(void)
-{
-    rt_interrupt_enter();
-    GPIO_EXTI_Callback(PINT_IT_PINT6);
+    /* leave interrupt */
     rt_interrupt_leave();
 }
 
-void PINT7_IRQHandler(void)
-{
-    rt_interrupt_enter();
-    GPIO_EXTI_Callback(PINT_IT_PINT7);
-    rt_interrupt_leave();
-}
+#endif /* RT_USING_PIN */
 
-#endif

bsp/acm32f4xx-nucleo/drivers/drv_uart.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "uart_config.h"
+
+#ifdef RT_USING_SERIAL
+
+#ifdef RT_SERIAL_USING_DMA
+struct dma_config
+{
+    DMA_Channel_TypeDef *Instance;
+    rt_uint32_t         dma_rcc;
+    IRQn_Type           dma_irq;
+
+    rt_uint32_t         channel;
+    rt_uint32_t         request;
+};
+#endif
+
+#ifdef RT_SERIAL_USING_DMA
+    static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag);
+#endif /* RT_SERIAL_USING_DMA */
+
+struct acm32_uart_config
+{
+    const char          *name;
+    UART_TypeDef        *Instance;
+    IRQn_Type           irq_type;
+    enum_Enable_ID_t    enable_id;
+
+#ifdef RT_SERIAL_USING_DMA
+    struct dma_config   *dma_rx;
+    struct dma_config   *dma_tx;
+#endif
+
+    enum_GPIOx_t        tx_port;
+    enum_GPIOx_t        rx_port;
+    rt_uint32_t         tx_pin;
+    rt_uint32_t         rx_pin;
+};
+
+struct acm32_uart
+{
+    UART_HandleTypeDef          handle;
+    struct acm32_uart_config    *config;
+#ifdef RT_SERIAL_USING_DMA
+    struct
+    {
+        DMA_HandleTypeDef       handle;
+        rt_size_t               last_index;
+    } dma_rx;
+
+    struct
+    {
+        DMA_HandleTypeDef       handle;
+    } dma_tx;
+#endif
+
+    rt_uint16_t                 uart_dma_flag;
+    struct rt_serial_device     serial;
+};
+
+static rt_err_t uart_rx_indicate_cb(rt_device_t dev, rt_size_t size)
+{
+    return RT_EOK;
+}
+
+static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    uart->handle.Instance = uart->config->Instance;
+
+    uart->handle.Init.BaudRate = cfg->baud_rate;
+    if (cfg->data_bits == DATA_BITS_8)
+    {
+        uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
+    }
+    else     /* not support */
+    {
+        return -RT_EINVAL;
+    }
+
+    if (cfg->stop_bits == STOP_BITS_1)
+    {
+        uart->handle.Init.StopBits = UART_STOPBITS_1;
+    }
+    else if (cfg->stop_bits == STOP_BITS_2)
+    {
+        uart->handle.Init.StopBits = UART_STOPBITS_2;
+    }
+    else     /* not support */
+    {
+        return -RT_EINVAL;
+    }
+
+    if (cfg->parity == PARITY_NONE)
+    {
+        uart->handle.Init.Parity = UART_PARITY_NONE;
+    }
+    else if (cfg->parity == PARITY_ODD)
+    {
+        uart->handle.Init.Parity = UART_PARITY_ODD;
+    }
+    else if (cfg->parity == PARITY_EVEN)
+    {
+        uart->handle.Init.Parity = UART_PARITY_EVEN;
+    }
+    else     /* not support */
+    {
+        return -RT_EINVAL;
+    }
+
+    uart->handle.Init.Mode       = UART_MODE_TX_RX;
+    uart->handle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
+
+    HAL_UART_Init(&uart->handle);
+
+    uart->handle.Instance->LCRH &= ~UART_LCRH_FEN;
+    return RT_EOK;
+}
+
+static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct acm32_uart *uart;
+#ifdef RT_SERIAL_USING_DMA
+    rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+#endif
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    switch (cmd)
+    {
+    /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        NVIC_DisableIRQ(uart->config->irq_type);
+        /* Disable RX interrupt */
+        uart->handle.Instance->IE &= ~UART_IE_RXI;
+        break;
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        NVIC_EnableIRQ(uart->config->irq_type);
+        /* Enable RX interrupt */
+        uart->handle.Instance->IE |= UART_IE_RXI;
+        break;
+#ifdef RT_SERIAL_USING_DMA
+    /* UART config */
+    case RT_DEVICE_CTRL_CONFIG :
+        DMA_Configuration(serial, (rt_uint32_t)ctrl_arg);
+        rt_device_set_rx_indicate((rt_device_t)serial, uart_rx_indicate_cb);
+        break;
+#endif /* RT_SERIAL_USING_DMA */
+    }
+    return RT_EOK;
+}
+
+static int _uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    while (uart->handle.Instance->FR & UART_FR_TXFF);    /* wait Tx FIFO not full */
+    uart->handle.Instance->DR = c;
+    while ((uart->handle.Instance->FR & UART_FR_BUSY)); /* wait TX Complete */
+
+    return 1;
+}
+
+static int _uart_getc(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart;
+
+    int ch;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    ch = -1;
+    if (!(uart->handle.Instance->FR & UART_FR_RXFE))   /* Rx FIFO not empty */
+    {
+        ch = uart->handle.Instance->DR & 0xff;
+    }
+
+    return ch;
+}
+
+#ifdef RT_SERIAL_USING_DMA
+/**
+ * Serial port receive idle process. This need add to uart idle ISR.
+ *
+ * @param serial serial device
+ */
+static void dma_uart_rx_idle_isr(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    rt_size_t recv_total_index, recv_len;
+    rt_base_t level;
+
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
+
+    recv_total_index = uart->handle.lu32_RxSize - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
+    recv_len = recv_total_index - uart->handle.lu32_RxCount;
+    uart->handle.lu32_RxCount = recv_total_index;
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
+
+    if (recv_len)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+    }
+}
+
+/*
+ DMA receive done process. This need add to DMA receive done ISR.
+
+ @param serial serial device
+*/
+static void dma_rx_done_isr(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart;
+    struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    rt_size_t recv_len;
+    rt_base_t level;
+
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
+
+    recv_len = serial->config.bufsz - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
+    uart->dma_rx.last_index = 0;
+
+    DMA->INT_TC_CLR |= 1 << (uart->config->dma_rx->channel);      /* clear channel0 TC flag */
+
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
+
+    if (recv_len)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+    }
+
+    HAL_UART_Receive_DMA(&(uart->handle), &rx_fifo->buffer[rx_fifo->put_index], serial->config.bufsz);
+}
+
+static rt_size_t _uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+{
+    struct acm32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    if (size == 0)
+    {
+        return 0;
+    }
+
+    if (RT_SERIAL_DMA_TX == direction)
+    {
+        if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
+            return size;
+        }
+        else
+        {
+            return 0;
+        }
+    }
+    return 0;
+}
+
+#endif /* RT_SERIAL_USING_DMA */
+
+static const struct rt_uart_ops acm32_uart_ops =
+{
+    _uart_configure,
+    _uart_control,
+    _uart_putc,
+    _uart_getc,
+#ifdef RT_SERIAL_USING_DMA
+    _uart_dma_transmit,
+#endif
+};
+
+#ifdef RT_SERIAL_USING_DMA
+static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag)
+{
+    struct rt_serial_rx_fifo *rx_fifo;
+    DMA_HandleTypeDef *DMA_Handle;
+    struct dma_config *dma_config;
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        DMA_Handle = &uart->dma_rx.handle;
+        dma_config = uart->config->dma_rx;
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+        DMA_Handle = &uart->dma_tx.handle;
+        dma_config = uart->config->dma_tx;
+    }
+    else
+    {
+        return;
+    }
+
+    DMA_Handle->Instance                 = dma_config->Instance;
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        DMA_Handle->Init.Data_Flow          = DMA_DATA_FLOW_P2M;
+        DMA_Handle->Init.Mode               = DMA_NORMAL;
+        DMA_Handle->Init.Source_Inc         = DMA_SOURCE_ADDR_INCREASE_DISABLE;
+        DMA_Handle->Init.Desination_Inc     = DMA_DST_ADDR_INCREASE_ENABLE;
+
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+        DMA_Handle->Init.Data_Flow          = DMA_DATA_FLOW_M2P;
+        DMA_Handle->Init.Mode               = DMA_NORMAL;
+        DMA_Handle->Init.Source_Inc         = DMA_SOURCE_ADDR_INCREASE_ENABLE;
+        DMA_Handle->Init.Desination_Inc     = DMA_DST_ADDR_INCREASE_DISABLE;
+    }
+
+    DMA_Handle->Init.Request_ID             = dma_config->request;
+    DMA_Handle->Init.Source_Width           = DMA_SRC_WIDTH_BYTE;
+    DMA_Handle->Init.Desination_Width       = DMA_DST_WIDTH_BYTE;
+
+    if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
+    {
+        RT_ASSERT(0);
+    }
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        __HAL_LINK_DMA(uart->handle, HDMA_Rx, uart->dma_rx.handle);
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+        __HAL_LINK_DMA(uart->handle, HDMA_Tx, uart->dma_tx.handle);
+    }
+    /* enable interrupt */
+    if (flag == RT_DEVICE_FLAG_DMA_RX)
+    {
+        rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+        /* Start DMA transfer */
+        if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
+        {
+            /* Transfer error in reception process */
+            RT_ASSERT(0);
+        }
+
+    }
+}
+#endif /* RT_SERIAL_USING_DMA */
+
+enum
+{
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_INDEX,
+#endif
+#ifdef BSP_USING_UART4
+    UART4_INDEX,
+#endif
+    UART_MAX_INDEX,
+};
+
+static struct acm32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART1
+    UART1_CONFIG,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_CONFIG,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_CONFIG,
+#endif
+#ifdef BSP_USING_UART4
+    UART4_CONFIG,
+#endif
+};
+
+static struct acm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+#ifdef RT_SERIAL_USING_DMA
+static void uart_get_dma_config(void)
+{
+#if defined(BSP_USING_UART1)
+#if defined(BSP_UART1_RX_USING_DMA)
+    static struct dma_config uart1_rx_dma_conf = UART1_DMA_RX_CONFIG;
+    uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART1_INDEX].dma_rx = &uart1_rx_dma_conf;
+#endif /* BSP_UART1_RX_USING_DMA */
+#if defined(BSP_UART1_TX_USING_DMA)
+    static struct dma_config uart1_tx_dma_conf = UART1_DMA_TX_CONFIG;
+    uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART1_INDEX].dma_tx = &uart1_tx_dma_conf;
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#if defined(BSP_UART2_RX_USING_DMA)
+    static struct dma_config uart2_rx_dma_conf = UART2_DMA_RX_CONFIG;
+    uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART2_INDEX].dma_rx = &uart2_rx_dma_conf;
+#endif /* BSP_UART2_RX_USING_DMA */
+#if defined(BSP_UART2_TX_USING_DMA)
+    static struct dma_config uart2_tx_dma_conf = UART2_DMA_TX_CONFIG;
+    uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART2_INDEX].dma_tx = &uart2_tx_dma_conf;
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#if defined(BSP_UART3_RX_USING_DMA)
+    static struct dma_config uart3_rx_dma_conf = UART3_DMA_RX_CONFIG;
+    uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART3_INDEX].dma_rx = &uart3_rx_dma_conf;
+#endif /* BSP_UART3_RX_USING_DMA */
+#if defined(BSP_UART3_TX_USING_DMA)
+    static struct dma_config uart3_tx_dma_conf = UART3_DMA_TX_CONFIG;
+    uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART3_INDEX].dma_tx = &uart3_tx_dma_conf;
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#if defined(BSP_UART4_RX_USING_DMA)
+    static struct dma_config uart4_rx_dma_conf = UART4_DMA_RX_CONFIG;
+    uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART4_INDEX].dma_rx = &uart4_rx_dma_conf;
+#endif /* BSP_UART4_RX_USING_DMA */
+#if defined(BSP_UART3_TX_USING_DMA)
+    static struct dma_config uart4_tx_dma_conf = UART4_DMA_TX_CONFIG;
+    uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART4_INDEX].dma_tx = &uart4_tx_dma_conf;
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+}
+#endif
+
+rt_err_t rt_hw_uart_init(void)
+{
+    rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct acm32_uart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t rc = RT_EOK;
+
+#ifdef RT_SERIAL_USING_DMA
+    uart_get_dma_config();
+#endif
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        uart_obj[i].config          = &uart_config[i];
+
+        uart_obj[i].serial.ops      = &acm32_uart_ops;
+        uart_obj[i].serial.config   = config;
+
+        /* register UART device */
+        rc = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
+                                   RT_DEVICE_FLAG_RDWR
+                                   | RT_DEVICE_FLAG_INT_RX
+                                   | RT_DEVICE_FLAG_INT_TX
+                                   | uart_obj[i].uart_dma_flag
+                                   , NULL);
+        RT_ASSERT(rc == RT_EOK);
+    }
+
+    return rc;
+}
+
+static void uart_isr(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    RT_ASSERT(serial != RT_NULL);
+
+    /* receive interrupt enabled */
+    if (uart->handle.Instance->IE & UART_IE_RXI)
+    {
+        if (uart->handle.Instance->RIS & UART_RIS_RXI)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        }
+    }
+
+#ifdef RT_SERIAL_USING_DMA
+    if (uart->handle.Instance->IE & UART_IE_RTI)   /* Receive TimeOut Interrupt */
+    {
+        dma_uart_rx_idle_isr(serial);
+        /* Clear RTI Status */
+        uart->handle.Instance->ICR = UART_ICR_RTI;
+    }
+#endif /* RT_SERIAL_USING_DMA */
+
+    if (uart->handle.Instance->IE & UART_IE_TXI && \
+            uart->handle.Instance->RIS & UART_RIS_TXI)
+    {
+        /* Clear TXI Status */
+        uart->handle.Instance->ICR = UART_ICR_TXI;
+        if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
+        }
+        /* Disable TX interrupt */
+        uart->handle.Instance->IE &= ~UART_IE_TXI;
+    }
+}
+
+#if defined(BSP_USING_UART1)
+void UART1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART1_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+void UART2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART2_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+void UART3_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART3_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+void UART4_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART4_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART4 */
+
+#ifdef RT_SERIAL_USING_DMA
+void DMA_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    for (int i = 0; i < UART_MAX_INDEX; i++)
+    {
+        if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_rx->channel))
+        {
+            dma_rx_done_isr(&uart_obj[i].serial);
+            break;
+        }
+
+        if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_tx->channel))
+        {
+            DMA->INT_TC_CLR |= 1 << (uart_obj[i].config->dma_tx->channel);      /* clear channel0 TC flag */
+            break;
+        }
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_SERIAL_USING_DMA */
+
+void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+    struct acm32_uart *uart;
+    GPIO_InitTypeDef  GPIO_Uart;
+
+    RT_ASSERT(huart != RT_NULL);
+
+    /* get uart object */
+    uart = rt_container_of(huart, struct acm32_uart, handle);
+
+    /* Enable Clock */
+    System_Module_Enable(uart->config->enable_id);
+
+    /* Initialization GPIO */
+    GPIO_Uart.Pin       = uart->config->tx_pin;
+    GPIO_Uart.Mode      = GPIO_MODE_AF_PP;
+    GPIO_Uart.Pull      = GPIO_PULLUP;
+    GPIO_Uart.Alternate = GPIO_FUNCTION_2;
+    HAL_GPIO_Init(uart->config->tx_port, &GPIO_Uart);
+
+    GPIO_Uart.Pin       = uart->config->rx_pin;
+    GPIO_Uart.Mode      = GPIO_MODE_AF_PP;
+    GPIO_Uart.Pull      = GPIO_PULLUP;
+    GPIO_Uart.Alternate = GPIO_FUNCTION_2;
+    HAL_GPIO_Init(uart->config->rx_port, &GPIO_Uart);
+
+    /* NVIC Config */
+    NVIC_ClearPendingIRQ(uart->config->irq_type);
+    NVIC_SetPriority(uart->config->irq_type, 5);
+    NVIC_EnableIRQ(uart->config->irq_type);
+}
+
+#endif /* RT_USING_SEARIAL */
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0007FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0800;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.lds

+/*
+ * linker script for ACM32F4xx with GNU ld
+ */
+
+/* describes the location and size of blocks of memory in the target. */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 512KB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */
+}
+/* Program Entry, set to mark it as "used" and avoid gc */
+ENTRY(Reset_Handler)
+_system_stack_size = 0x800;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(8);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+

bsp/essemi/es8p508x/drivers/linker_scripts/link.sct → bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.sct

@@ -2,13 +2,14 @@
 ; *** Scatter-Loading Description File generated by uVision ***
 ; *************************************************************
 
-LR_IROM1 0x00000000 0x00020000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x00020000  {  ; load address = execution address
+LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
+   .ANY (+XO)
   }
-  RW_IRAM1 0x20000000 0x00006000  {  ; RW data
+  RW_IRAM1 0x20000000 0x00030000  {  ; RW data
    .ANY (+RW +ZI)
   }
 }

bsp/acm32f4xx-nucleo/drivers/uart_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "board.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(RT_USING_SERIAL)
+
+#if defined(BSP_USING_UART1)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = UART1,                                          \
+        .irq_type = UART1_IRQn,                                     \
+        .enable_id = EN_UART1,                                      \
+        .tx_port  = UART1_TX_PORT,                                  \
+        .rx_port  = UART1_RX_PORT,                                  \
+        .tx_pin   = UART1_TX_PIN,                                   \
+        .rx_pin   = UART1_RX_PIN,                                   \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+        .channel  = UART2_RX_DMA_CHANNEL,                           \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+        .channel  = UART2_TX_DMA_CHANNEL,                           \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = UART2,                                          \
+        .irq_type = UART2_IRQn,                                     \
+        .enable_id = EN_UART2,                                      \
+        .tx_port  = UART2_TX_PORT,                                  \
+        .rx_port  = UART2_RX_PORT,                                  \
+        .tx_pin   = UART2_TX_PIN,                                   \
+        .rx_pin   = UART2_RX_PIN,                                   \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+        .channel  = UART3_RX_DMA_CHANNEL,                           \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+        .channel  = UART3_TX_DMA_CHANNEL,                           \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = UART3,                                          \
+        .irq_type = UART3_IRQn,                                     \
+        .enable_id = EN_UART3,                                      \
+        .tx_port  = UART3_TX_PORT,                                  \
+        .rx_port  = UART3_RX_PORT,                                  \
+        .tx_pin   = UART3_TX_PIN,                                   \
+        .rx_pin   = UART3_RX_PIN,                                   \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+        .channel  = UART4_RX_DMA_CHANNEL,                           \
+        .request  = UART4_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_TX_DMA_RCC,                               \
+        .dma_irq  = UART4_TX_DMA_IRQ,                               \
+        .channel  = UART4_TX_DMA_CHANNEL,                           \
+        .request  = UART4_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+        .enable_id = EN_UART4,                                      \
+        .tx_port  = UART4_TX_PORT,                                  \
+        .rx_port  = UART4_RX_PORT,                                  \
+        .tx_pin   = UART4_TX_PIN,                                   \
+        .rx_pin   = UART4_RX_PIN,                                   \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RT_USING_SERIAL */
+
+#endif /* __UART_CONFIG_H__ */
+

bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h → bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_compiler.h

 /**************************************************************************//**
  * @file     cmsis_compiler.h
  * @brief    CMSIS compiler generic header file
- * @version  V5.0.4
- * @date     10. January 2018
+ * @version  V5.1.0
+ * @date     09. October 2018
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,9 +35,15 @@
 
 
 /*
- * Arm Compiler 6 (armclang)
+ * Arm Compiler 6.6 LTM (armclang)
  */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
   #include "cmsis_armclang.h"
 
 
@@ -115,8 +121,11 @@
     #define __ALIGNED(x)                           __attribute__((aligned(x)))
   #endif
   #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
   #endif
 
 
@@ -187,6 +196,10 @@
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
   #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 /*
@@ -255,6 +268,10 @@
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
   #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 #else

bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h → bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_iccarm.h

 /**************************************************************************//**
  * @file     cmsis_iccarm.h
  * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version  V5.0.5
- * @date     10. January 2018
+ * @version  V5.2.0
+ * @date     28. January 2020
  ******************************************************************************/
 
 //------------------------------------------------------------------------------
 //
-// Copyright (c) 2017-2018 IAR Systems
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved. 
+//
+// SPDX-License-Identifier: Apache-2.0
 //
 // Licensed under the Apache License, Version 2.0 (the "License")
 // you may not use this file except in compliance with the License.
@@ -110,6 +113,10 @@
   #define __ASM __asm
 #endif
 
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
 #ifndef __INLINE
   #define __INLINE inline
 #endif
@@ -150,7 +157,12 @@
 #endif
 
 #ifndef   __RESTRICT
-  #define __RESTRICT            restrict
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
 #endif
 
 #ifndef   __STATIC_INLINE
@@ -234,6 +246,25 @@ __packed struct  __iar_u32 { uint32_t v; };
   #endif
 #endif
 
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
 
 #ifndef __ICCARM_INTRINSICS_VERSION__
   #define __ICCARM_INTRINSICS_VERSION__  0
@@ -340,8 +371,17 @@ __packed struct  __iar_u32 { uint32_t v; };
   #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
   #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
   #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
-  #define __TZ_get_PSPLIM_NS()        (__arm_rsr("PSPLIM_NS"))
-  #define __TZ_set_PSPLIM_NS(VALUE)   (__arm_wsr("PSPLIM_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
   #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
   #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
 
@@ -558,7 +598,7 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT uint32_t __RRX(uint32_t value)
     {
       uint32_t result;
-      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
       return(result);
     }
 
@@ -716,12 +756,25 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
     {
       uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
       __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
       return res;
     }
+
     __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
     {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
       __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
     }
 
     __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
@@ -784,37 +837,37 @@ __packed struct  __iar_u32 { uint32_t v; };
   __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
   {
     uint32_t res;
-    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
   {
     uint32_t res;
-    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
   {
     uint32_t res;
-    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return res;
   }
 
   __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
   {
-    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+    __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
   }
 
   __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
   {
-    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+    __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
   }
 
   __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
   {
-    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+    __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
   }
 
 #endif /* (__CORTEX_M >= 0x03) */
@@ -826,78 +879,78 @@ __packed struct  __iar_u32 { uint32_t v; };
   __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return res;
   }
 
   __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
   {
-    __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
   {
-    __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
   {
-    __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
@@ -910,4 +963,6 @@ __packed struct  __iar_u32 { uint32_t v; };
 #pragma diag_default=Pe940
 #pragma diag_default=Pe177
 
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
 #endif /* __CMSIS_ICCARM_H__ */

bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h → bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_version.h

 /**************************************************************************//**
  * @file     cmsis_version.h
  * @brief    CMSIS Core(M) Version definitions
- * @version  V5.0.2
- * @date     19. April 2017
+ * @version  V5.0.3
+ * @date     24. June 2019
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,7 +33,7 @@
 
 /*  CMSIS Version definitions */
 #define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
 #define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
 #endif

bsp/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h

+/*
+  ******************************************************************************
+  * @file    System_Accelerate.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   MCU Accelerate Peripheral Access Layer System header File.
+  ******************************************************************************
+*/
+#ifndef __SYSTEM_ACCELERATE_H__
+#define __SYSTEM_ACCELERATE_H__
+
+
+
+/* System_EnableIAccelerate */ 
+void System_EnableIAccelerate(void);
+
+/* System_DisableIAccelerate */
+void System_DisableIAccelerate(void);
+
+/* System_EnableDAccelerate */
+void System_EnableDAccelerate(void);
+
+/* System_DisableDAccelerate */
+void System_DisableDAccelerate(void);
+
+
+#endif
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash.h

+/*
+  ******************************************************************************
+  * @file    HAL_EFlash.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of EFlash HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_H__
+#define __HAL_EFlash_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define EFLASH_PAGE_SIZE    (512UL)
+
+#define HAL_EFLASH_READ_WORD(Addr)        (*(volatile uint32_t *)(Addr))    // Read By Word
+#define HAL_EFLASH_READ_HALFWORD(Addr)    (*(volatile uint16_t *)(Addr))    // Read By Half Word
+#define HAL_EFLASH_READ_BYTE(Addr)        (*(volatile uint8_t *)(Addr))     // Read By Byte
+
+/********************  Bit definition for EFC_CTRL register  ******************/
+#define EFC_CTRL_CHIP_ERASE_MODE        (1 << 2)
+#define EFC_CTRL_PAGE_ERASE_MODE        (1 << 1)
+#define EFC_CTRL_PROGRAM_MODE           (1 << 0)
+
+/********************  Bit definition for EFC_STATUS register  ***************/
+#define EFC_STATUS_NVR4_LOCK            (1 << 4)
+#define EFC_STATUS_NVR3_LOCK            (1 << 3)
+#define EFC_STATUS_NVR2_LOCK            (1 << 2)
+#define EFC_STATUS_NVR1_LOCK            (1 << 1)
+#define EFC_STATUS_EFLASH_RDY           (1 << 0)
+
+#define RD_WAIT_ENSURE_OK   8 
+#define SET_EFC_RD_WAIT(wait)     {EFC->CTRL   = (EFC->CTRL & ~(0x1F << 7)) | (wait << 7);}     
+
+/* Exported functions --------------------------------------------------------*/  
+
+/* HAL_EFlash_Init */  
+void HAL_EFlash_Init(uint32_t fu32_freq);  
+/* HAL_EFlash_ErasePage */
+bool HAL_EFlash_ErasePage(uint32_t fu32_Addr);
+
+/* HAL_EFlash_Program_Word */
+bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h

+/*
+  ******************************************************************************
+  * @file    HAL_EFlash_EX.h
+  * @version V1.0.0
+  * @date    2021
+  * @brief   Header file of EFlash extention module   
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_EX_H__
+#define __HAL_EFlash_EX_H__
+
+#include "stdint.h"
+
+/* HAL_EFlash_Return_To_Boot */
+void HAL_EFlash_Return_to_Boot(void);
+
+/* HAL_EFlash_Init_Para */ 
+void HAL_EFlash_Init_Para(uint32_t fu32_freq);   
+
+/* HAL_EFlash_ErasePage_EX */   
+void HAL_EFlash_ErasePage_EX(uint32_t fu32_Addr);  
+
+/* HAL_EFlash_Program_Word_EX */     
+void HAL_EFlash_Program_Word_EX(uint32_t fu32_Addr, uint32_t fu32_Data);  
+
+#endif