[add] stm32mp1 library

bsp/stm32/libraries/Kconfig

@@ -55,3 +55,8 @@ config SOC_SERIES_STM32H7
     bool
     select ARCH_ARM_CORTEX_M7
     select SOC_FAMILY_STM32
+
+config SOC_SERIES_STM32MP1
+    bool
+    select ARCH_ARM_CORTEX_M4
+    select SOC_FAMILY_STM32

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h

+/**
+  ******************************************************************************
+  * @file    stm32mp1xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32MP1xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32MP1xx device used in the target application
+  *              - To use or not the peripherals drivers in application code(i.e.
+  *                code will be based on direct access to peripherals registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32mp1xx
+  * @{
+  */
+
+#ifndef __STM32MP1xx_H
+#define __STM32MP1xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target STM32MP1 device used in your
+   application
+  */
+
+#if !defined (STM32MP1)
+#define STM32MP1
+#endif /* STM32MP1 */
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number
+  */
+#define __STM32MP1xx_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32MP1xx_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32MP1xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32MP1xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32MP1xx_CMSIS_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(CORE_CM4)
+#if defined(STM32MP15xx)  /* keep for backward compatibility STM32MP15xx = STM32MP157Cxx */
+  #include "stm32mp157cxx_cm4.h"
+#elif defined(STM32MP157Axx)
+  #include "stm32mp157axx_cm4.h"
+#elif defined(STM32MP157Cxx)
+  #include "stm32mp157cxx_cm4.h"
+#elif defined(STM32MP157Dxx)
+  #include "stm32mp157dxx_cm4.h"
+#elif defined(STM32MP157Fxx)
+  #include "stm32mp157fxx_cm4.h"
+#elif defined(STM32MP153Axx)
+  #include "stm32mp153axx_cm4.h"
+#elif defined(STM32MP153Cxx)
+  #include "stm32mp153cxx_cm4.h"
+#elif defined(STM32MP153Dxx)
+  #include "stm32mp153dxx_cm4.h"
+#elif defined(STM32MP153Fxx)
+  #include "stm32mp153fxx_cm4.h"
+#elif defined(STM32MP151Axx)
+  #include "stm32mp151axx_cm4.h"
+#elif defined(STM32MP151Cxx)
+  #include "stm32mp151cxx_cm4.h"
+#elif defined(STM32MP151Dxx)
+  #include "stm32mp151dxx_cm4.h"
+#elif defined(STM32MP151Fxx)
+  #include "stm32mp151fxx_cm4.h"
+#else
+ #error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)"
+#endif
+#endif
+
+#if defined(CORE_CA7)
+#if defined(STM32MP15xx)  /* keep for backward compatibility STM32MP15xx = STM32MP157Cxx */
+  #include "stm32mp157cxx_ca7.h"
+#elif defined(STM32MP157Axx)
+  #include "stm32mp157axx_ca7.h"
+#elif defined(STM32MP157Cxx)
+  #include "stm32mp157cxx_ca7.h"
+#elif defined(STM32MP157Dxx)
+  #include "stm32mp157dxx_ca7.h"
+#elif defined(STM32MP157Fxx)
+  #include "stm32mp157fxx_ca7.h"
+#elif defined(STM32MP153Axx)
+  #include "stm32mp153axx_ca7.h"
+#elif defined(STM32MP153Cxx)
+  #include "stm32mp153cxx_ca7.h"
+#elif defined(STM32MP153Dxx)
+  #include "stm32mp153dxx_ca7.h"
+#elif defined(STM32MP153Fxx)
+  #include "stm32mp153fxx_ca7.h"
+#elif defined(STM32MP151Axx)
+  #include "stm32mp151axx_ca7.h"
+#elif defined(STM32MP151Cxx)
+  #include "stm32mp151cxx_ca7.h"
+#elif defined(STM32MP151Dxx)
+  #include "stm32mp151dxx_ca7.h"
+#elif defined(STM32MP151Fxx)
+  #include "stm32mp151fxx_ca7.h"
+#else
+ #error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)"
+#endif
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32mp1xx_hal_conf.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32MP1xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h

+/**
+  ******************************************************************************
+  * @file    system_stm32mp1xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device System Source File for STM32MP1xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32mp1xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32MP1XX_H
+#define __SYSTEM_STM32MP1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup STM32MP1xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32MP1xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Core1 Clock Frequency  */
+extern uint32_t SystemCore1Clock;         /*!< System Core1 Clock Frequency  */
+extern uint32_t SystemCore2Clock;         /*!< System Core2 Clock Frequency  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32MP1XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html

+<!DOCTYPE html>
+<html><head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><title>Release Notes for STM32MP1xx CMSIS</title>
+
+<style>
+div.Section1 {
+page: Section1;
+font-family: Arial,Helvetica,sans-serif;
+}
+h1 {
+font-size: 24pt;
+font-weight: bold;
+font-family: Arial,Helvetica,sans-serif;
+text-align: center;
+color: #3366ff;
+}
+h2 {
+margin: 12pt 0in 3pt;
+page-break-after: avoid;
+font-weight: bold;
+font-family: Arial,Helvetica,sans-serif;
+background-color: #3366ff;
+color: white;
+padding-left: 5px;
+font-size: 16pt;
+}
+h3 {
+margin-left: 0in;
+font-weight: bold;
+font-family: Arial,Helvetica,sans-serif;
+background-color: #3366ff;
+width: 200px;
+margin-right: 500pt;
+color: white;
+padding-left: 5px;
+padding-top: 2px;
+padding-bottom: 2px;
+font-size: 12pt;
+}
+h4 {
+font-family: Arial,Helvetica,sans-serif;
+font-weight: bold;
+text-decoration: underline;
+font-size: 12pt;
+}
+p {
+margin: 0px 0px 0px 0in;
+font-family: Arial,Helvetica,sans-serif;
+padding-top: 3px;
+padding-bottom: 3px;
+font-size: 12pt;
+}
+ul {
+font-family: Arial,Helvetica,sans-serif;
+margin-top: 3px;
+margin-bottom: 3px;
+font-size: 10pt;
+}
+caption {
+margin-top: 10px;
+font-family: Arial,Helvetica,sans-serif;
+font-size: 11pt;
+}
+hr {
+width: 100%;
+}
+.guidance {
+background-color: #e5b8b7;
+font-style: italic;
+font-family: Arial,Helvetica,sans-serif;
+padding-top: 3px;
+padding-bottom: 3px;
+margin-top: 3px;
+margin-bottom: 3px;
+font-size: 10pt;
+}
+.guidance_title {
+font-style: normal;
+font-weight: bold;
+text-decoration: underline;
+font-family: Arial,Helvetica,sans-serif;
+font-size: 10pt;
+}
+.tickets {
+border: 1pt solid #9cc2e5;
+font-family: Arial,Helvetica,sans-serif;
+margin-bottom: 3px;
+margin-top: 3px;
+font-size: 10pt;
+}
+.tickets th {
+border: 1pt solid #9cc2e5;
+font-size: 12pt;
+background-color: #39a9dc;
+color: white;
+text-align: center;
+}
+.tickets td {
+border: 1pt solid #9cc2e5;
+min-height: 32px;
+}
+tr:nth-child(even) {background-color: #cee2f2;}
+tr:nth-child(even) {background-color: #e8f1f9;}
+.topic1 {
+margin-top: 3px;
+margin-bottom: 3px;
+margin-left: 40px;
+}
+.topic2 {
+margin-top: 3px;
+margin-bottom: 3px;
+}
+.topic3 {
+margin-top: 3px;
+margin-bottom: 3px;
+margin-left: 20px;
+}
+#purpose {
+margin-top: 3px;
+margin-bottom: 3px;
+}
+#identification {
+margin-top: 3px;
+margin-bottom: 3px;
+}
+</style></head>
+<body link="blue" vlink="blue">
+<script type="text/javascript">
+var toggle_hist_disp = true;
+function toggle_history()
+{
+if (toggle_hist_disp)
+{
+toggle_hist_disp = false;
+var filter_off_text = document.createTextNode("Hide History");
+document.getElementById('filter_hist').innerHTML = "";
+document.getElementById('filter_hist').appendChild(filter_off_text);
+document.getElementById("history").hidden = false;
+}
+else
+{
+toggle_hist_disp = true;
+var filter_on_text = document.createTextNode("Show History");
+document.getElementById('filter_hist').innerHTML = "";
+document.getElementById('filter_hist').appendChild(filter_on_text);
+document.getElementById("history").hidden = true;
+}
+}</script><a href="../../../../../Release_Notes.html">Back to Release page</a>
+<div style="width: 1034px;" class="Section1">
+<div id="header">
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for<o:p></o:p> STM32MP1xx CMSIS Device</span></h1>
+<p style="text-align: center;">Copyright 2019
+STMicroelectronics</p>
+<p style="text-align: center;"><img style="width: 104px; height: 77px;" id="st_logo" alt="&lt;ST logo&gt; image" src="../../../../../_htmresc/st_logo.png"></p>
+</div>
+<div id="license" class="topic1">
+<h2>License</h2>
+<p>This software component is licensed by ST under BSD 3-Clause
+license, the "License"; You may not use this component except in
+compliance with the License. You may obtain a copy of the License at:</p>
+<p style="text-align: center; color: white;"><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank"><span style="background-color: yellow;"></span></a><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank">https://opensource.org/licenses/BSD-3-Clause</a><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank"><span style="background-color: yellow;"></span></a></p>
+</div>
+<div id="release_container" class="topic1">
+<div class="topic2" id="identification">
+<h3 style="width: 230px;">V1.2.0 / 03-Feb-2020</h3>
+</div>
+<div style="margin-left: 20px; width: 974px;" class="topic3" id="changes">
+<h4>Main changes</h4>
+<ul><li>Header files:&nbsp;</li><ul><li>Add new Part Number for 800MHz</li><li>Update license with BSD 3-Clause template</li><li>Rework CMSIS for RTC/TAMP, GPIO and TIM</li><li>Rename TIM Break source bit definition</li></ul></ul><ul><li>Update Linker Template&nbsp;file for KEIL and IAR:</li><ul><li>Add OpenAMP region ( region present by default, to comment if needed )</li></ul></ul><br>
+</div>
+<div class="topic3" id="contents">
+<h4>Contents</h4>
+<ul>
+<li>CMSIS devices files for:</li><ul><li>STM32MP<span style="font-weight: bold;">151C</span>xx ,STM32MP<span style="font-weight: bold;">151A</span>xx, STM32MP<span style="font-weight: bold;">151D</span>xx ,STM32MP<span style="font-weight: bold;">151F</span>xx</li><li>STM32MP<span style="font-weight: bold;">153C</span>xx ,STM32MP<span style="font-weight: bold;">153A</span>xx, STM32MP<span style="font-weight: bold;">153D</span>xx ,STM32MP<span style="font-weight: bold;">153F</span>xx</li><li>STM32MP<span style="font-weight: bold;">157C</span>xx ,STM32MP<span style="font-weight: bold;">157A</span>xx, STM32MP<span style="font-weight: bold;">157D</span>xx ,STM32MP<span style="font-weight: bold;">157F</span>xx</li></ul></ul><ul>
+</ul>
+</div>
+</div>
+<div style="margin-left: 40px;"><button id="filter_hist" onclick="toggle_history()">Show
+History</button><br>
+</div>
+<div id="history" class="topic1" hidden="">
+<h2>Update History</h2>
+<br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 26px; width: 174px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 10-Sept-2019</span><br></h3><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<h4>Main changes</h4>
+<ul><li>Header files:&nbsp;</li><ul><li>Update FMC bit definition</li><li>Update ETH&nbsp;bit definition</li><li>update EXTI_EXTICR&nbsp;bit definition</li><li>Update I2C&nbsp;bit definition</li><li>Update SPI&nbsp;bit definition (SPI_CR1_CRC33_17, SPI_RXCRC, SPI_IER, SPI_I2SCFGR)&nbsp;</li><li>TMPSENS IP renamed DTS</li><li>Update FDCAN TXBC&nbsp;bit definition</li><li>Update DAC_DHR8RD&nbsp;bit definition</li><li>Add CRYP in STM32MP151Cx and STM32MP153Cx</li><li>Update TIM / LPTIM&nbsp;bit definition + add missing macros</li></ul><li>Update system_stm32mp1xx.c</li><ul><li>Update SystemCoreClock</li></ul><li>Update startup file for KEIL and IAR</li></ul></div><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<h4>Contents</h4>
+<ul><li>CMSIS devices files for STM32MP<span style="font-weight: bold;">151C</span>xx ,STM32MP<span style="font-weight: bold;">151A</span>xx, STM32MP<span style="font-weight: bold;">153C</span>xx, STM32MP<span style="font-weight: bold;">153A</span>xx, STM32MP<span style="font-weight: bold;">157C</span>xx ,STM32MP<span style="font-weight: bold;">157A</span>xx</li></ul>
+<br>
+</div><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 26px; width: 174px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 22-January-2019</span><br></h3><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<h4>Main changes</h4>
+<ul><li>First official release for <span style="font-weight: bold;">STM32MP15xx</span> devices<br>
+</li></ul></div><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<h4>Contents</h4>
+<ul><li>CMSIS devices files for STM32MP<span style="font-weight: bold;">151C</span>xx ,STM32MP<span style="font-weight: bold;">151A</span>xx, STM32MP<span style="font-weight: bold;">153C</span>xx, STM32MP<span style="font-weight: bold;">153A</span>xx, STM32MP<span style="font-weight: bold;">157C</span>xx ,STM32MP<span style="font-weight: bold;">157A</span>xx</li></ul>
+<br>
+</div><br><br>
+</div>
+<div id="product_doc" class="topic1">
+<hr>
+<p style="text-align: center;">For complete
+documentation on&nbsp;<span style="background-color: white;">STM32
+Microcontrollers</span>, visit: <span style="background-color: white;"><a href="http://www.st.com/STM32" target="_blank">www.st.com/STM32</a></span></p>
+</div>
+</div>
+</body></html>
\ No newline at end of file

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/linker/stm32mp15xx_m4.sct

+; *************************************************************
+; *** Scatter-Loading Description                           ***
+; *************************************************************
+
+LR_VECTORS 0x00000000 0x00000400  {    ; load region size_region
+  .isr_vector +0 {
+    startup*.o (RESET, +First)
+  }
+}
+
+LR_IROM1 0x10000000 0x00020000  {      ; load region size_region
+  ER_IROM1 0x10000000 0x00020000  {    ; load address = execution address
+    *(InRoot$$Sections)
+    .ANY (+RO)
+    .ANY (+XO)
+  }
+  RW_IRAM1 0x10020000 0x00020000  {    ; RW data
+    .ANY (+RW +ZI)
+  }
+
+; *****   Create region for OPENAMP                               *****
+; ***     These 4 lines can be commented if OPENAMP is not used     ***
+  .resource_table +0 ALIGN 4 {         ; resource table
+    *(.resource_table)
+  }
+  __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP
+}

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld

+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Abstract    : Linker script for STM32MP1 series
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the License; You may not use this file except in compliance with the 
+** License. You may obtain a copy of the License at:
+**                       opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x10040000;    /* end of RAM */
+
+_Min_Heap_Size  = 0x200;  /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  m_interrupts (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000298
+  m_text       (RX)  : ORIGIN = 0x10000000, LENGTH = 0x00020000
+  m_data       (RW)  : ORIGIN = 0x10020000, LENGTH = 0x00020000
+  m_ipc_shm    (RW)  : ORIGIN = 0x10040000, LENGTH = 0x00008000
+}
+
+ /* Symbols needed for OpenAMP to enable rpmsg */
+__OPENAMP_region_start__  = ORIGIN(m_ipc_shm);
+__OPENAMP_region_end__ = ORIGIN(m_ipc_shm)+LENGTH(m_ipc_shm);
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into ROM memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+ 
+
+  /* The program code and other data into ROM memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } > m_text
+
+  /* Constant data into ROM memory*/
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab   : { 
+  	. = ALIGN(4);
+  	*(.ARM.extab* .gnu.linkonce.armextab.*)
+  	. = ALIGN(4);
+  } > m_text
+  
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } > m_text
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } > m_text
+  
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } > m_text
+  
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } > m_text
+
+  /* Used by the startup to initialize data */
+  __DATA_ROM = .;
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections */
+  .data :  AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (_edata - _sdata);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  .resource_table :
+  {
+    . = ALIGN(4);
+    KEEP (*(.resource_table*))
+    . = ALIGN(4);
+  } > m_data
+  
+
+  /* Uninitialized data section into RAM memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } > m_data
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } > m_data
+
+  
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+}

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_text_start__ = 0x00000000;
+define symbol __ICFEDIT_region_text_end__   = 0x00008000;
+define symbol __ICFEDIT_region_data_start__ = 0x00008000;
+define symbol __ICFEDIT_region_data_end__   = 0x00010000;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region text_region   = mem:[from __ICFEDIT_region_text_start__   to __ICFEDIT_region_text_end__];
+define region data_region   = mem:[from __ICFEDIT_region_data_start__   to __ICFEDIT_region_data_end__];
+
+keep { section .resource_table };
+".resource_table" :  place in data_region {section .resource_table};
+
+/* Create region for OPENAMP */
+/* !!! These 4 lines can be commented if OPENAMP is not used !!!*/
+define symbol __OPENAMP_region_start__ = 0x10040000;
+define symbol __OPENAMP_region_size__   = 0x8000;
+export symbol __OPENAMP_region_start__;
+export symbol __OPENAMP_region_size__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit};
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in text_region   { readonly };
+place in data_region   { readwrite,
+                         block CSTACK, block HEAP};
\ No newline at end of file

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_text_start__ = 0x10000000;
+define symbol __ICFEDIT_region_text_end__   = 0x1001FFFF;
+define symbol __ICFEDIT_region_data_start__ = 0x10020000;
+define symbol __ICFEDIT_region_data_end__   = 0x1003FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region text_region   = mem:[from __ICFEDIT_region_text_start__   to __ICFEDIT_region_text_end__];
+define region data_region   = mem:[from __ICFEDIT_region_data_start__   to __ICFEDIT_region_data_end__];
+
+keep { section .resource_table };
+".resource_table" :  place in data_region {section .resource_table};
+
+/* Create region for OPENAMP */
+/* !!! These 4 lines can be commented if OPENAMP is not used !!!*/
+define symbol __OPENAMP_region_start__ = 0x10040000;
+define symbol __OPENAMP_region_size__   = 0x8000;
+export symbol __OPENAMP_region_start__;
+export symbol __OPENAMP_region_size__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit};
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in text_region   { readonly };
+place in data_region   { readwrite,
+                         block CSTACK, block HEAP};
\ No newline at end of file

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c

+/**
+  ******************************************************************************
+  * @file    system_stm32mp1xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32mp1xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock frequency, it can
+  *                                  be used by the user application to setup
+  *                                  the SysTick timer or configure other
+  *                                  parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  *
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32mp1xx_system
+  * @{
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32mp1xx_hal.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_Defines
+  * @{
+  */
+
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x400. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) each time HAL_RCC_ClockConfig() is called to configure the system clock
+         frequency
+         Note: If you use this function to configure the system clock;
+               then there is no need to call the first functions listed above,
+               since SystemCoreClock variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = HSI_VALUE;
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (DATA_IN_ExtSRAM) 
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_Functions
+  * @{
+  */
+
+  /**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory 
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+#if defined (CORE_CM4)
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+   SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined (VECT_TAB_SRAM)
+  SCB->VTOR = MCU_AHB_SRAM | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif
+  /* Disable all interrupts and events */
+  CLEAR_REG(EXTI_C2->IMR1);
+  CLEAR_REG(EXTI_C2->IMR2);
+  CLEAR_REG(EXTI_C2->IMR3);
+  CLEAR_REG(EXTI_C2->EMR1);
+  CLEAR_REG(EXTI_C2->EMR2);
+  CLEAR_REG(EXTI_C2->EMR3);
+#else
+#error Please #define CORE_CM4
+#endif	                         
+}
+
+/**
+   * @brief Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock frequency (Hz),
+  *         it can be used by the user application to setup the SysTick timer or
+  *         configure other parameters.
+  *
+  * @note   Each time the core clock changes, this function must be called to
+  *         update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the
+  *             HSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the
+  *             HSE_VALUE(**)
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the
+  *             CSI_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL3_P, SystemCoreClock will contain the
+  *             HSI_VALUE(*) or the HSE_VALUE(*) or the CSI_VALUE(***)
+  *             multiplied/divided by the PLL3 factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
+  *             (default value 64 MHz) but the real value may vary depending
+  *             on the variations in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
+  *              (default value 24 MHz), user has to ensure that HSE_VALUE is
+  *              same as the real frequency of the crystal used. Otherwise, this
+  *              function may have wrong result.
+  *
+  *         (***) CSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
+  *              (default value 4 MHz)but the real value may vary depending
+  *              on the variations in voltage and temperature.
+  *
+  *         - The result of this function could be not correct when using
+  *           fractional value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t   pllsource, pll3m, pll3fracen;
+  float fracn1, pll3vco;
+
+  switch (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC)
+  {
+  case 0x00:  /* HSI used as system clock source */
+    SystemCoreClock = (HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV));
+    break;
+
+  case 0x01:  /* HSE used as system clock source */
+    SystemCoreClock = HSE_VALUE;
+    break;
+
+  case 0x02:  /* CSI used as system clock source */
+    SystemCoreClock = CSI_VALUE;
+    break;
+
+  case 0x03:  /* PLL3_P used as system clock source */
+    pllsource = (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC);
+    pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U;
+    pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> 16U;
+    fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> 3U));
+    pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x1FFF));
+
+    if (pll3m != 0U)
+    {
+      switch (pllsource)
+      {
+        case 0x00:  /* HSI used as PLL clock source */
+          pll3vco *= (float)((HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV)) / pll3m);
+          break;
+
+        case 0x01:  /* HSE used as PLL clock source */
+          pll3vco *= (float)(HSE_VALUE / pll3m);
+          break;
+
+        case 0x02:  /* CSI used as PLL clock source */
+          pll3vco *= (float)(CSI_VALUE / pll3m);
+          break;
+
+        case 0x03:  /* No clock source for PLL */
+          pll3vco = 0;
+          break;
+       }
+      SystemCoreClock = (uint32_t)(pll3vco/ ((float)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) + 1U)));
+    }
+    else
+    {
+      SystemCoreClock = 0U;
+    }
+    break;
+  }
+
+  /* Compute mcu_ck */
+  SystemCoreClock = SystemCoreClock >> (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV);
+}
+
+
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32mp15xx.s before jump to main.
+  *         This function configures the external SRAM mounted on Eval boards
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Include/cmsis_compiler.h

+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Include/cmsis_version.h

+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Include/mpu_armv7.h

+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Include/tz_context.h

+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/docs/index.html

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<title>Redirect to the CMSIS main page after 0 seconds</title>
+<meta http-equiv="refresh" content="0; URL=General/html/index.html">
+<meta name="keywords" content="automatic redirection">
+</head>
+
+<body>
+
+If the automatic redirection is failing, click <a href="General/html/index.html">open CMSIS Documentation</a>.
+
+</body>
+</html>

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32_assert_template.h

+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @author  MCD Application Team
+  * @brief   STM32 assert template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32_assert.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_ASSERT_H
+#define STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_ASSERT_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/