import CM3-M7 project.

bsp/CME_M7/CME_M7.ld

+/******************************************************************************
+ *
+ * nuc472_flash.ld - Linker configuration file for project.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2014-08-24     aozima       first implementation
+ *
+ *****************************************************************************/
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+SECTIONS
+{
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)
+        *(.rodata*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for components init. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+    } > FLASH
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > FLASH
+    __exidx_end = .;
+
+	/* end of all text. */
+    _etext = .;
+	
+    .data : AT(_etext)
+    {
+        _data = .;
+        *(vtable)
+        *(.data*)
+        _edata = .;
+    } > SRAM
+
+    .bss :
+    {
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        _ebss = .;
+    } > SRAM
+    __bss_end = .;
+
+}

bsp/CME_M7/CME_M7.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+; load 		region 			size_region
+LR_IROM1 	(0)				(1024 * 128)
+{
+	; load address = execution address
+	ER_IROM1 (0) 			(1024 * 128)
+	{
+		*.o (RESET, +First)
+		*(InRoot$$Sections)
+		.ANY (+RO)
+	}
+
+	; RW data
+	RW_IRAM1 0x20000000 (1024 * 64)
+	{
+		.ANY (+RW +ZI)
+	}
+}
+

bsp/CME_M7/CMSIS/CME_M7/cmem7_it.c

+/**
+	*****************************************************************************
+	* @file     cmem7_it.c
+	*
+	* @brief    CMEM7 system exception file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note      
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#include "cmem7_it.h"
+
+void NMI_Handler(void)
+{
+	while (1);
+}
+
+void HardFault_Handler(void)
+{
+  if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
+    __breakpoint (0); // halt program execution here
+  }
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+void MemManage_Handler(void)
+{
+  if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
+    __breakpoint (0); // halt program execution here
+  }
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+void BusFault_Handler(void)
+{
+  if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
+    __breakpoint (0); // halt program execution here
+  }
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+void UsageFault_Handler(void)
+{
+  if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
+    __breakpoint (0); // halt program execution here
+  }
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+void SVC_Handler(void)
+{
+}
+
+void DebugMon_Handler(void)
+{
+}
+
+void PendSV_Handler(void)
+{
+}
+
+void SysTick_Handler(void)
+{
+}
+

bsp/CME_M7/CMSIS/CME_M7/cmem7_it.h

+/**
+	*****************************************************************************
+	* @file     cmem7_it.h
+	*
+	* @brief    CMEM7 system exception interrupt header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note     Actually, you don't have to implement below involved function 
+	*           whick were defined as weak dummy functions in startup file.
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+
+#ifndef __CMEM7_IT_H
+#define __CMEM7_IT_H
+
+#include "cmem7.h"
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void);
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void);
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void);
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void);
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void);
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void);
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void);
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void);
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void);
+
+/**
+  * @brief  This function handles ethernet interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void ETH_IRQHandler(void);
+
+/**
+  * @brief  This function handles USB interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void USB_IRQHandler(void);
+
+/**
+  * @brief  This function handles DMA interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void DMAC_IRQHandler(void);
+
+/**
+  * @brief  This function handles CAN0 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void CAN0_IRQHandler(void); 
+
+/**
+  * @brief  This function handles CAN1 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void CAN1_IRQHandler(void); 
+
+/**
+  * @brief  This function handles FP0 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP0_IRQHandler(void);  
+
+/**
+  * @brief  This function handles FP1 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP1_IRQHandler(void);          
+
+/**
+  * @brief  This function handles FP2 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP2_IRQHandler(void);          		
+
+/**
+  * @brief  This function handles FP3 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP3_IRQHandler(void); 
+
+/**
+  * @brief  This function handles FP4 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP4_IRQHandler(void); 
+
+/**
+  * @brief  This function handles FP5 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP5_IRQHandler(void); 
+
+/**
+  * @brief  This function handles FP6 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP6_IRQHandler(void);
+
+/**
+  * @brief  This function handles FP7 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP7_IRQHandler(void);
+
+/**
+  * @brief  This function handles FP8 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP8_IRQHandler(void);
+
+/**
+  * @brief  This function handles FP9 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP9_IRQHandler(void);
+
+/**
+  * @brief  This function handles FP10 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP10_IRQHandler(void);
+
+/**
+  * @brief  This function handles FP11 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP11_IRQHandler(void);
+
+/**
+  * @brief  This function handles FP12 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP12_IRQHandler(void);
+
+/**
+  * @brief  This function handles FP13 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP13_IRQHandler(void);
+
+/**
+  * @brief  This function handles FP14 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP14_IRQHandler(void);
+
+/**
+  * @brief  This function handles FP15 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void FP15_IRQHandler(void); 
+
+/**
+  * @brief  This function handles UART0 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void UART0_IRQHandler(void);
+
+/**
+  * @brief  This function handles UART1 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void UART1_IRQHandler(void);
+
+/**
+  * @brief  This function handles ADC interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void ADC_IRQHandler(void); 
+
+/**
+  * @brief  This function handles GPIO interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void GPIO_IRQHandler(void);
+
+/**
+  * @brief  This function handles SPI1 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void SPI1_IRQHandler(void);
+
+/**
+  * @brief  This function handles I2C1 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void I2C1_IRQHandler(void);
+
+/**
+  * @brief  This function handles SPI0 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void SPI0_IRQHandler(void);
+
+/**
+  * @brief  This function handles I2C0 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void I2C0_IRQHandler(void);
+
+/**
+  * @brief  This function handles RTC second interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void RTC_1S_IRQHandler(void); 
+
+/**
+  * @brief  This function handles RTC microsecond interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void RTC_1MS_IRQHandler(void);
+
+/**
+  * @brief  This function handles watchdog interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void WDG_IRQHandler(void); 
+
+/**
+  * @brief  This function handles timer interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void TIMER_IRQHandler(void); 
+
+/**
+  * @brief  This function handles DDR interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void DDRC_SW_PROC_IRQHandler(void); 
+
+/**
+  * @brief  This function handles ethernet pmt interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void ETH_PMT_IRQHandler(void); 
+
+/**
+  * @brief  This function handles pad interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void PAD_IRQHandler(void);
+
+/**
+  * @brief  This function handles DDR interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void DDRC_LANE_SYNC_IRQHandler(void); 
+
+/**
+  * @brief  This function handles UART2 interrupt.
+  * @param  None
+  * @retval None
+	* @note   Implement it in your interrupt handler
+  */
+void UART2_IRQHandler(void);            
+
+#endif /* __CMEM7_IT_H */
+

bsp/CME_M7/CMSIS/CME_M7/startup/arm/startup_cmem7.s

+;*****************************************************************************
+;* @file     start_cmem7.h
+;*
+;* @brief    CMEM7 startup file
+;*
+;*
+;* @version  V1.0
+;* @date     3. September 2013
+;*
+;* @note               
+;*           
+;*****************************************************************************
+;* @attention
+;*
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+;* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+;* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+;* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*
+;* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+;*****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+				DCD     ETH_IRQHandler             ; ETH
+				DCD     USB_IRQHandler             ; USB
+				DCD     DMAC_IRQHandler            ; DMAC
+				DCD     CAN0_IRQHandler            ; CAN0
+				DCD     CAN1_IRQHandler            ; CAN1
+				DCD     FP0_IRQHandler             ; FP[0:15]
+				DCD     FP1_IRQHandler
+				DCD     FP2_IRQHandler
+				DCD     FP3_IRQHandler
+				DCD     FP4_IRQHandler
+				DCD     FP5_IRQHandler
+				DCD     FP6_IRQHandler
+				DCD     FP7_IRQHandler
+				DCD     FP8_IRQHandler
+				DCD     FP9_IRQHandler
+				DCD     FP10_IRQHandler
+				DCD     FP11_IRQHandler
+				DCD     FP12_IRQHandler
+				DCD     FP13_IRQHandler
+				DCD     FP14_IRQHandler
+				DCD     FP15_IRQHandler			   ; 21
+				DCD     UART0_IRQHandler           ; UART0
+                DCD     UART1_IRQHandler           ; UART1
+				DCD     ADC_IRQHandler             ; ADC
+				DCD     GPIO_IRQHandler            ; GPIO
+				DCD     SPI1_IRQHandler            ; SPI1
+				DCD     I2C1_IRQHandler            ; I2C1
+				DCD     SPI0_IRQHandler            ; SPI0
+				DCD     I2C0_IRQHandler            ; I2C0
+				DCD     RTC_1S_IRQHandler          ; RTC 1S
+				DCD     RTC_1MS_IRQHandler         ; RTC 1MS
+				DCD     WDG_IRQHandler             ; Watchdog
+				DCD     TIMER_IRQHandler           ; Timer 0 || 1 || 2 || 3
+                DCD     DDRC_SW_PROC_IRQHandler    ; DDRC sw proc       				
+				DCD     ETH_PMT_IRQHandler         ; ETH pmt
+				DCD     PAD_IRQHandler             ; PAD
+				DCD     DDRC_LANE_SYNC_IRQHandler  ; DDRC lane sync
+				DCD     UART2_IRQHandler           ; UART2
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC               
+				EXPORT  ETH_IRQHandler             [WEAK]
+                EXPORT  USB_IRQHandler             [WEAK]
+				EXPORT  DMAC_IRQHandler            [WEAK]
+				EXPORT  CAN0_IRQHandler            [WEAK]
+				EXPORT  CAN1_IRQHandler            [WEAK]
+				EXPORT  FP0_IRQHandler             [WEAK]
+				EXPORT  FP1_IRQHandler             [WEAK]
+				EXPORT  FP2_IRQHandler             [WEAK]
+				EXPORT  FP3_IRQHandler             [WEAK]
+				EXPORT  FP4_IRQHandler             [WEAK]
+				EXPORT  FP5_IRQHandler             [WEAK]
+				EXPORT  FP6_IRQHandler             [WEAK]
+				EXPORT  FP7_IRQHandler             [WEAK]
+				EXPORT  FP8_IRQHandler             [WEAK]
+				EXPORT  FP9_IRQHandler             [WEAK]
+				EXPORT  FP10_IRQHandler            [WEAK]
+				EXPORT  FP11_IRQHandler            [WEAK]
+				EXPORT  FP12_IRQHandler            [WEAK]
+				EXPORT  FP13_IRQHandler            [WEAK]
+				EXPORT  FP14_IRQHandler            [WEAK]
+				EXPORT  FP15_IRQHandler            [WEAK]
+				EXPORT  UART0_IRQHandler           [WEAK]
+                EXPORT  UART1_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler             [WEAK]
+				EXPORT  GPIO_IRQHandler            [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+				EXPORT  I2C1_IRQHandler            [WEAK]
+                EXPORT  SPI0_IRQHandler            [WEAK]
+                EXPORT  I2C0_IRQHandler            [WEAK]
+				EXPORT  RTC_1S_IRQHandler          [WEAK]
+				EXPORT  RTC_1MS_IRQHandler         [WEAK]
+                EXPORT  WDG_IRQHandler             [WEAK]				
+                EXPORT  TIMER_IRQHandler           [WEAK] 
+                EXPORT  DDRC_SW_PROC_IRQHandler    [WEAK]           				
+				EXPORT  ETH_PMT_IRQHandler         [WEAK]           				
+				EXPORT  PAD_IRQHandler             [WEAK]           				
+				EXPORT  DDRC_LANE_SYNC_IRQHandler  [WEAK]           				
+				EXPORT  UART2_IRQHandler           [WEAK]           				         				
+ETH_IRQHandler
+USB_IRQHandler
+DMAC_IRQHandler
+CAN0_IRQHandler
+CAN1_IRQHandler
+FP0_IRQHandler
+FP1_IRQHandler
+FP2_IRQHandler
+FP3_IRQHandler
+FP4_IRQHandler
+FP5_IRQHandler
+FP6_IRQHandler
+FP7_IRQHandler
+FP8_IRQHandler
+FP9_IRQHandler
+FP10_IRQHandler
+FP11_IRQHandler
+FP12_IRQHandler
+FP13_IRQHandler
+FP14_IRQHandler
+FP15_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler          
+ADC_IRQHandler 
+GPIO_IRQHandler
+SPI1_IRQHandler          
+I2C1_IRQHandler         
+SPI0_IRQHandler          
+I2C0_IRQHandler  
+RTC_1S_IRQHandler
+RTC_1MS_IRQHandler
+WDG_IRQHandler            
+TIMER_IRQHandler 
+DDRC_SW_PROC_IRQHandler    				
+ETH_PMT_IRQHandler               				
+PAD_IRQHandler                  				
+DDRC_LANE_SYNC_IRQHandler     				
+UART2_IRQHandler          
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 Capital Micro *****END OF FILE*****

bsp/CME_M7/CMSIS/CME_M7/system_cmem7.c

+/**
+	*****************************************************************************
+	* @file     system_cmem7.c
+	*
+	* @brief    CMEM7 system initial file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note      
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+
+#include "cmem7.h"
+#include "cmem7_includes.h"
+
+void SystemInit (void) {
+	// Generally, we use DLL clock as system clock, not default oscillator
+	GLB_SelectSysClkSource(SYS_CLK_SEL_DLL);
+
+	// change NMI to PAD IRQ
+	GLB_SetNmiIrqNum(PAD_INT_IRQn);	
+	
+	return ;
+}
+

bsp/CME_M7/CMSIS/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+CME_M7/system_cmem7.c
+""")
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += ['Device/Nuvoton/NUC472_442/Source/GCC/startup_NUC472_442.c']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += ['CME_M7/startup/arm/startup_cmem7.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += ['Device/Nuvoton/NUC472_442/Source/IAR/startup_NUC472_442.S']
+
+path = [cwd + '/CME_M7']
+#ath += [cwd + '/StdDriver/inc']
+
+# if GetDepend(['RT_USING_BSP_CMSIS']):
+    # path += [cwd + '/CMSIS/Include']
+# elif GetDepend(['RT_USING_RTT_CMSIS']):
+    # path += [RTT_ROOT + '/components/CMSIS/Include']
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/CME_M7/SConscript

+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/CME_M7/SConstruct

+import os
+import sys
+import rtconfig
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/CME_M7/StdPeriph_Driver/SConscript

+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src = Glob('src/*.c')
+
+path = [cwd + '/inc']
+
+group = DefineGroup('StdPeriph_Driver', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_adc.h

+/**
+	*****************************************************************************
+	* @file     cmem7_adc.h
+	*
+	* @brief    CMEM7 ADC header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_ADC_H
+#define __CMEM7_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup ADC_PERIPH
+  * @{
+  */
+typedef enum {
+	ADC_PERIPH_1,
+	ADC_PERIPH_2,
+} ADC_PERIPH;
+
+#define IS_ADC_ALL_PERIPH(PERIPH)         (((PERIPH) == ADC_PERIPH_1) || \
+                                           ((PERIPH) == ADC_PERIPH_2))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_VSEN
+  * @{
+  */
+#define ADC_VSEN_VDDCORE                  1
+#define ADC_VSEN_VDDIO                    2
+#define ADC_VSEN_VDDIO2                   4
+
+#define IS_ADC_VSEN(VSEN)                 (((VSEN) == ADC_VSEN_VDDCORE) || \
+                                           ((VSEN) == ADC_VSEN_VDDIO) || \
+                                           ((VSEN) == ADC_VSEN_VDDIO2))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_PHASE_CTRL
+  * @{
+  */
+#define ADC_PHASE_CTRL_0DEG_RISE_EDGE     0         /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(Rising Edge) */                                               
+#define ADC_PHASE_CTRL_90DEG_AHEAD        1         /* ADC-1 90DEG ahead of ADC-2 */
+#define ADC_PHASE_CTRL_90DEG_LAG          2         /* ADC-1 90DEG lag of ADC-2 */
+#define ADC_PHASE_CTRL_0DEG_FALL_EDGE     3         /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(falling Edge) */
+
+#define IS_ADC_PHASE_CTRL(CTRL)           (((CTRL) == ADC_PHASE_CTRL_0DEG_RISE_EDGE) || \
+                                           ((CTRL) == ADC_PHASE_CTRL_90DEG_AHEAD) || \
+                                           ((CTRL) == ADC_PHASE_CTRL_90DEG_LAG) || \
+                                           ((CTRL) == ADC_PHASE_CTRL_0DEG_FALL_EDGE))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_CONVERSION
+  * @{
+  */
+#define ADC_SYSTEM_MODE_SINGLE_CONV       1
+#define ADC_SYSTEM_MODE_CONTINUOUS_CONV   2	
+
+#define IS_ADC_CONVERSION(CONV)           (((CONV) == ADC_SYSTEM_MODE_SINGLE_CONV) || \
+                                           ((CONV) == ADC_SYSTEM_MODE_CONTINUOUS_CONV))
+																					 
+/**
+  * @}
+  */
+
+/** @defgroup ADC_CALIBRATION
+  * @{
+  */
+#define ADC_CALIBRATION_OFFSET            3
+#define ADC_CALIBRATION_NEGTIVE_GAIN      4
+#define ADC_CALIBRATION_POSTIVE_GAIN      5
+
+#define IS_ADC_CALIBRATION(CALIB)         (((CALIB) == ADC_CALIBRATION_OFFSET) || \
+                                           ((CALIB) == ADC_CALIBRATION_NEGTIVE_GAIN) || \
+                                           ((CALIB) == ADC_CALIBRATION_POSTIVE_GAIN))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_CHANNEL
+  * @{
+  */
+#define ADC_CHANNEL_CALIBRATION           0x0
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC1_CHANNEL
+  * @{
+  */
+#define ADC1_CHANNEL_VIP                  0x1		
+#define ADC1_CHANNEL_VSEN                 0x2
+#define ADC1_CHANNEL_VADIO_0              0x4
+#define ADC1_CHANNEL_VADIO_1              0x8
+#define ADC1_CHANNEL_VADIO_2              0x10
+#define ADC1_CHANNEL_VADIO_3              0x20
+#define ADC1_CHANNEL_VADIO_4              0x40
+#define ADC1_CHANNEL_VADIO_5              0x80
+#define ADC1_CHANNEL_ALL                  0xFF
+
+#define IS_ADC1_CHANNEL(CHANNEL)          (((CHANNEL) != 0) && ((CHANNEL) & ~ADC1_CHANNEL_ALL) == 0)
+/**
+  * @}
+  */
+
+/** @defgroup ADC2_CHANNEL
+  * @{
+  */																																										 
+#define ADC2_CHANNEL_VIN                  0x1		
+#define ADC2_CHANNEL_VTMP                 0x2
+#define ADC2_CHANNEL_VADIO_6              0x4
+#define ADC2_CHANNEL_VADIO_7              0x8
+#define ADC2_CHANNEL_VADIO_8              0x10
+#define ADC2_CHANNEL_VADIO_9              0x20
+#define ADC2_CHANNEL_VADIO_10             0x40
+#define ADC2_CHANNEL_VADIO_11             0x80
+#define ADC2_CHANNEL_ALL                  0xFF
+
+#define IS_ADC2_CHANNEL(CHANNEL)          (((CHANNEL) != 0) && ((CHANNEL) & ~ADC2_CHANNEL_ALL) == 0)                                          																 
+/**
+  * @}
+  */
+
+/** @defgroup ADC_INT
+  * @{
+  */																					 
+#define ADC1_INT_ALMOST_FULL              0x1 
+#define ADC2_INT_ALMOST_FULL              0x8
+#define ADC_INT_ALL              					0x9
+
+#define IS_ADC_INT(INT)        						(((INT) != 0) && (((INT) & ~ADC_INT_ALL) == 0))
+/**
+  * @}
+  */
+
+/**
+  * @brief  ADC collection data structure
+	*/ 
+typedef struct {
+	uint8_t channel;												/*!< The channel of collected data, is a value of 
+																							 @ref ADC_CHANNEL, @ref ADC1_CHANNEL or @ref ADC2_CHANNEL */
+	uint16_t data;													/*!< collected data                    												*/
+} ADC_Data;
+
+/**
+  * @brief  ADC initialization structure
+	*/ 
+typedef struct
+{
+	uint8_t ADC_PhaseCtrl;                  /*!< Phase between ADC1 and ADC2, is a value of @ref ADC_PHASE_CTRL */
+	uint8_t ADC_VsenSelection;              /*!< ADC1 VSEN selection, is a value of @ref ADC_VSEN					*/
+} ADC_InitTypeDef;
+
+/**
+  * @brief  ADC initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param[in] init A pointer to structure ADC_InitTypeDef
+  * @retval None
+	*/ 
+void ADC_Init(ADC_InitTypeDef* init);
+
+/**
+  * @brief  Enable or disable ADC. 
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @param[in] Enable The bit indicates if the specific ADC is enable or not
+  * @retval None
+	*/ 
+void ADC_Enable(uint8_t adc, BOOL enable);
+
+/**
+  * @brief  Enable or disable ADC interrupt. 
+	* @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @retval None
+	*/ 
+void ADC_EnableInt(uint32_t Int, BOOL enable);
+
+/**
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT
+	* @retval BOOL The bit indicates if the specific interrupts are set or not
+	*/
+BOOL ADC_GetIntStatus(uint32_t Int);
+
+/**
+  * @brief  Clear specific interrupts
+	* @param[in] Int interrupt mask bits, which can be a value of @ref ADC_INT
+  * @retval None
+	*/
+void ADC_ClearInt(uint32_t Int);
+
+/**
+  * @brief  ADC starts to convert data 
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @param[in] convMode It should be a value of @ref ADC_CONVERSION
+	* @param[in] channel It should be the value of @ref ADC1_CHANNEL 
+	* 					 or @ref ADC2_CHANNEL according to parameter 'adc'
+  * @retval BOOL The bit indicates if the specific ADC starts to convert data
+	*/ 
+BOOL ADC_StartConversion(uint8_t adc, uint8_t convMode, uint32_t channel);
+
+/**
+  * @brief  ADC starts to calibrate and produces one sample
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @param[in] convMode It should be a value of @ref ADC_CALIBRATION
+  * @retval BOOL The bit indicates if the specific ADC starts to convert data
+	*/ 
+BOOL ADC_StartCalibration(uint8_t adc, uint8_t calibration);
+
+/**
+  * @brief  ADC stops conversion or calibration
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @retval NULL
+	*/ 
+void ADC_Stop(uint8_t adc);
+
+/**
+  * @brief  Check if ADC is busy or not
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @retval BOOL The bit indicates if the specific ADC is busy or not
+	*/ 
+BOOL ADC_IsBusy(uint8_t adc);
+
+/**
+  * @brief  Read data from ADC
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @param[in] Size Expected data size to be read
+	* @param[out] data A user-allocated buffer to fetch data to be read
+  * @retval uint8_t Actual read data size
+	*/
+uint8_t ADC_Read(uint8_t adc, uint8_t size, ADC_Data* data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CMEM7_ADC_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_aes.h

+/**
+	*****************************************************************************
+	* @file     cmem7_aes.h
+	*
+	* @brief    CMEM7 AES header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_AES_H
+#define __CMEM7_AES_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/**
+  * @brief  AES decryption
+	* @param[in] src A pointer to data to be decrypted
+	* @param[out] dst A user-allocated buffer to fetch decrypted data
+  * @param[in] len Expected data size to be decrypted, which should
+	*						 be multiply times of 16
+	* @retval BOOL True if succeed, or flase
+	*/
+BOOL AES_Decrypt(const void *src, void *dst, uint32_t len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_AES_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_can.h

+/**
+	*****************************************************************************
+	* @file     cmem7_can.h
+	*
+	* @brief    CMEM7 CAN header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_CAN_H
+#define __CMEM7_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+	 
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN0) || \
+                                   ((PERIPH) == CAN1))
+
+/** @defgroup CAN_FLT
+  * @{
+  */																
+#define CAN_FLT_STANDARD_SINGLE    0x00000000
+#define CAN_FLT_STANDARD_DUAL      0x00000001
+#define CAN_FLT_EXTENDED_SINGLE    0x00000002
+#define CAN_FLT_EXTENDED_DUAL      0x00000003
+
+#define IS_CAN_FLT_TYPE(FILTER)    (((FILTER) == CAN_FLT_STANDARD_SINGLE) || \
+                                    ((FILTER) == CAN_FLT_STANDARD_DUAL) || \
+																		((FILTER) == CAN_FLT_EXTENDED_SINGLE) || \
+                                    ((FILTER) == CAN_FLT_EXTENDED_DUAL))	
+																		
+#define IS_CAN_FLT_SINGLE(FILTER)  (((FILTER) == CAN_FLT_STANDARD_SINGLE) || \
+                                    ((FILTER) == CAN_FLT_EXTENDED_SINGLE))
+
+#define IS_CAN_FLT_DUAL(FILTER)    (IS_CAN_FLT_TYPE(FILTER) && \
+                                    !IS_CAN_FLT_SINGLE(FILTER))
+																		
+/**
+  * @}
+  */
+
+/** @defgroup CAN_CDR_DIV
+  * @{
+  */
+#define CAN_CDR_DIV_1_2            0x0
+#define CAN_CDR_DIV_1_4            0x1
+#define CAN_CDR_DIV_1_6            0x2
+#define CAN_CDR_DIV_1_8            0x3
+#define CAN_CDR_DIV_1_10           0x4
+#define CAN_CDR_DIV_1_12           0x5
+#define CAN_CDR_DIV_1_14           0x6
+#define CAN_CDR_DIV_1_1            0x7
+
+#define IS_CAN_CDR_DIV(DIV)        (((DIV) == CAN_CDR_DIV_1_2) || \
+                                    ((DIV) == CAN_CDR_DIV_1_4) || \
+																		((DIV) == CAN_CDR_DIV_1_6) || \
+																		((DIV) == CAN_CDR_DIV_1_8) || \
+																		((DIV) == CAN_CDR_DIV_1_10) || \
+																		((DIV) == CAN_CDR_DIV_1_12) || \
+																		((DIV) == CAN_CDR_DIV_1_14) || \
+																		((DIV) == CAN_CDR_DIV_1_1))		
+/**
+  * @}
+  */
+
+/** @defgroup CAN_INT
+  * @{
+  */
+#define CAN_INT_RBNF               0x01
+#define CAN_INT_TB_UNLOCK          0x02
+#define CAN_INT_ERR                0x04
+#define CAN_INT_DATA_OVERRUN       0x08
+#define CAN_INT_WAKEUP             0x10
+#define CAN_INT_ERR_PASSIVE        0x20
+#define CAN_INT_ARBITRATION_LOST   0x40
+#define CAN_INT_BUS_ERR            0x80
+#define CAN_INT_All                0xFF
+
+#define IS_CAN_INT(INT)            (((INT) != 0) && (((INT) & ~CAN_INT_All) == 0))                                  
+/**
+  * @}
+  */
+
+/**
+  * @brief  CAN standard filter structure
+	*/ 
+typedef struct {
+	uint16_t  ID28_18;               /*!< 11 bits                                      */
+  BOOL      RTR;                   /*!< if remote frame                              */
+	uint8_t   data1;                 /*!< data byte 1, if not 2nd CAN_FLT_STANDARD_DUAL*/
+	uint8_t   data2;                 /*!< data byte 2, if CAN_FLT_STANDARD_SINGLE      */
+} CAN_STANDARD_FILTER;
+
+/**
+  * @brief  CAN extended filter structure
+	*/
+typedef struct {
+	uint16_t  ID28_13;               /*!< 16 bits                                      */
+	uint16_t  ID12_0;                /*!< 13 bits, if CAN_FLT_EXTENDED_SINGLE          */
+  BOOL      RTR;                   /*!< if remote frame, if CAN_FLT_EXTENDED_SINGLE  */
+} CAN_EXTENDED_FILTER;
+
+/**
+  * @brief  CAN filter structure
+	*/
+typedef struct {
+	uint8_t   type;                  /*!< Filter type, which is a value of @ref CAN_FLT */
+	
+	/**
+  * @brief  accepted filter
+	*/
+	union {
+		CAN_STANDARD_FILTER sf;				 
+		CAN_EXTENDED_FILTER ef;				 
+	} ACCEPT;												 
+	
+	/**
+  * @brief  filter mask 
+	*/
+	union {
+		CAN_STANDARD_FILTER sf;        
+		CAN_EXTENDED_FILTER ef;				 
+	} MASK;													 
+} CAN_FILTER;
+
+/**
+  * @brief  CAN initialization structure
+	*/
+typedef struct {	
+	BOOL CAN_TxEn;            			 /*!< if transmission is enable 										*/
+	BOOL CAN_Loopback;        			 /*!< loop back mode without phy						 				*/
+  uint8_t CAN_ClockDiv;     			 /*!< input clock divider, ref as @ref CAN_CDR_DIV  */                               
+	uint16_t CAN_Prescaler;   			 /*!< Specifies the length of a time quantum. 
+																				Time quantum = (CAN_Prescaler + 1) * 2 * input clock */ 
+  uint8_t CAN_SJW;          			 /*!< Specifies the maximum number of time quanta 
+																				the CAN hardware is allowed to lengthen or 
+																				shorten a bit to perform resynchronization.		*/
+	uint8_t CAN_TSEG1;        			 /*!< the maximum number of time quanta of 
+																				propagation and 1st phase segment 						*/
+  uint8_t CAN_TSEG2;        			 /*!< the maximum number of time quanta of 2nd 
+																				phase segment																	*/	
+  BOOL CAN_HighSpeed;       			 /*!< if CAN is running on high speed bus (class C) */
+} CAN_InitTypeDef;
+
+/**
+  * @brief  CAN frame structure
+	*/
+typedef struct
+{
+  BOOL SFF;        								 /*!< If standard or extended frame format 					*/ 
+	uint32_t Id;     								 /*!< Specifies the identifier.This parameter can 
+																				be a value between 0 to 0x1FFFFFFF. 					*/
+  BOOL RTR;        								 /*!< Specifies if the frame is a remote frame      */
+  uint8_t DLC;     								 /*!< Specifies the length of the frame, which is 
+																				a value between  0 to 8 											*/
+  uint8_t Data[8]; 								 /*!< Frame data																		*/
+} CAN_Frame;
+
+/**
+  * @brief  CAN initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @param[in] Init A pointer to structure CAN_InitTypeDef
+	* @param[in] f1 A pointer to structure CAN_FILTER
+	* @param[in] f2 NULL if single filter, or a pointer to second filter while dual filters
+  * @retval BOOL The bit indicates if specific CAN is initialized or not
+	*/ 
+BOOL CAN_Init(CAN0_Type* CANx, CAN_InitTypeDef* Init, 
+  CAN_FILTER *f1, CAN_FILTER *f2);
+
+/**
+  * @brief  CAN is set to sleep or wake up
+  * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @param[in] Enable The bit indicates if sleep mode is enable or not
+	* @retval None
+	*/
+void CAN_SetSleepMode(CAN0_Type* CANx, BOOL enable);
+
+/**
+  * @brief  Enable or disable UART interrupt. 
+	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref CAN_INT
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @retval None
+	*/ 
+void CAN_EnableInt(CAN0_Type* CANx, uint32_t Int, BOOL enable);
+
+/**
+  * @brief  Check specific interrupts are set or not 
+	* @note   All interrupts except for receive int are cleared after call this func.
+	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @retval uint8_t CAN interrupt bits, which can be the combination of @ref CAN_INT
+	*/
+uint8_t CAN_GetIntStatus(CAN0_Type* CANx);
+
+/**
+  * @brief  CAN perform to transmit data
+	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @param[in] frame A pointer to the CAN_Frame to be transmitted
+	* @retval BOOL The bit indicates if data is transmitted or not
+	*/ 
+BOOL CAN_Transmit(CAN0_Type* CANx, CAN_Frame* frame);
+
+/**
+  * @brief  CAN perform to receive data
+	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @param[out] frame A user-allocated buffer to fetch received frame
+	* @retval BOOL The bit indicates if data is recieved or not
+	*/
+BOOL CAN_Receive(CAN0_Type* CANx, CAN_Frame* frame);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_CAN_H */

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h

+/**
+	*****************************************************************************
+	* @file     cmem7_conf.h
+	*
+	* @brief    CMEM7 config file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+
+#ifndef __CMEM7_CONF_H
+#define __CMEM7_CONF_H
+
+#define _ADC
+#define _AES
+#define _CAN
+#define _DDR
+#define _DMA
+#define _EFUSE
+#define _ETH
+#define _FLASH
+#define _GPIO
+#define _I2C
+#define _MISC
+#define _RTC
+#define _SPI
+#define _TIM
+#define _UART
+#define _USB
+#define _WDG
+
+#define USE_FULL_ASSERT    1 
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports
+  *         the name of the source file and the source line number of the call
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((unsigned char *)__FILE__, __LINE__))
+
+	static void assert_failed(unsigned char* file, unsigned long line) {
+		while (1) {
+			;
+		}
+	}
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+typedef enum _BOOL {FALSE = 0, TRUE = 1} BOOL;
+
+/**
+  * System clock frequency, unit is Hz.
+  */
+#define SYSTEM_CLOCK_FREQ         200000000
+
+/**
+  * @brief  usecond delay 
+	* @note 	It can't delay in an accurate time
+	* @param[in] usec usecond to be delay
+	* @retval None
+	*/
+static void udelay(unsigned long usec) {
+  unsigned long count = 0;
+  unsigned long utime = SYSTEM_CLOCK_FREQ / 1000000 * usec;
+
+  while(++count < utime) ;
+}
+
+/**
+  * UART definition for print
+	*/
+#define PRINT_UART							UART2
+
+/**
+  * DDR type definition
+  */
+#define DDR_TYPE				3	// 2 for DDR2, 3 for DDR3
+
+#if (DDR_TYPE == 3)
+# define DDR_SIZE				(256 << 20)
+#elif (DDR_TYPE == 2)
+# define DDR_SIZE				(128 << 20)
+#else
+# error
+#endif
+
+#endif /* __CMEM7_CONF_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_ddr.h

+/**
+	*****************************************************************************
+	* @file     cmem7_ddr.h
+	*
+	* @brief    CMEM7 AES header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_DDR_H
+#define __CMEM7_DDR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+/** @defgroup _MEM_TYPE
+  * @{
+  */
+enum _MEM_TYPE 
+{
+	MEM_DDR2=1,
+	MEM_DDR3		
+} ;	
+/**
+  * @}
+  */
+
+/** @defgroup _BUS_WIDTH
+  * @{
+  */
+enum _BUS_WIDTH
+{
+	BUS_WIDTH_8,
+	BUS_WIDTH_16,
+	BUS_WIDTH_MAX
+};
+/**
+  * @}
+  */
+/** @defgroup _CHIP_TYPE
+  * @{
+  */  
+enum _CHIP_TYPE
+{
+	_32Mbx8,
+	_64Mbx8,
+	_128Mbx8,
+	_256Mbx8,
+	_512Mbx8,
+	_16Mbx16,
+	_32Mbx16,
+	_64Mbx16,
+	_128Mbx16,
+	_256Mbx16,
+	_512Mbx16,
+	CHIP_TYPE_MAX
+};
+/**
+  * @}
+  */
+
+/** @defgroup _CHIP_NUM
+  * @{
+  */  
+enum _CHIP_NUM
+{
+	CHIP_NUM_x1,
+	CHIP_NUM_x2,
+	CHIP_NUM_MAX
+};
+/**
+  * @}
+  */
+  
+/** @defgroup MEM_CHIP_INFO
+  * @{
+  */
+typedef struct {
+	uint8_t mem_type;     /*!< ddr type @ref _MEM_TYPE*/
+	uint8_t Bus_width;	/*!< ddr qs bus width @ref _BUS_WIDTH*/
+	uint8_t Chip_type;	/*!< chip type @ref _CHIP_TYPE*/
+	uint8_t Chip_num;	/*!< chip number @ref _CHIP_NUM*/
+	uint8_t Chip_bank;      /*!< chip bank number*/		
+} MEM_CHIP_INFO;								
+/**
+  * @}
+  */
+
+
+/** @defgroup DDR2MEM
+  * @{
+  */
+typedef struct {
+	uint32_t tCK;       		/*!< Period of clock(ps), not data period */ 
+	uint32_t tCL;						/*!< tCL */
+	uint32_t tRCD;						/*!< tRCD */
+	uint32_t tRP;						/*!< tRP */
+	uint32_t tRC;						/*!< tRC */
+	uint32_t tRAS;						/*!< tRAS */
+	uint32_t tWR;						/*!< tWR */
+	uint32_t tRRD;						/*!< tRRD */
+	uint32_t tWTR;						/*!< tWTR */
+	uint32_t tRTP;						/*!< tRTP */
+	uint32_t tFAW;						/*!< tFAW */
+} DDR2MEM;								/*!< DDR2ʱ */
+/**
+  * @}
+  */
+
+/** @defgroup DDR3MEM
+  * @{
+  */
+typedef struct {
+	uint32_t tCK;       		/*!< Period of clock(ps), not data period */ 
+	uint32_t tCL;						/*!< tCL */
+	uint32_t tWCL;						/*!< tWCL */
+	uint32_t tRCD;						/*!< tRCD */
+	uint32_t tRAS;						/*!< tRAS */
+	uint32_t tRP;						/*!< tRP */
+	uint32_t tRC;						/*!< tRC */
+	uint32_t tRRD;						/*!< tRRD */
+	uint32_t tFAW;						/*!< tFAW */
+	uint32_t tWR;						/*!< tWR */
+	uint32_t tRTP;						/*!< tRTP */
+	uint32_t tZQoper;					/*!< tZQCL */
+	uint32_t tZQCS;						/*!< tZQCS */
+} DDR3MEM;								/*!< DDR3ʱ */
+/**
+  * @}
+  */
+
+/** @defgroup DDR2PREDEF
+  * @{
+  */
+extern const DDR2MEM DDR2PREDEF[];		/*!< Pre-defined DDR2 Timing in library */
+#define DDR2_400C			0			/*!< sg5E: DDR2-400C CL=4, tCK=5000ps */
+
+/**
+  * @}
+  */
+
+/** @defgroup DDR3PREDEF
+  * @{
+  */
+extern const DDR3MEM DDR3PREDEF[];		/*!< Pre-defined DDR3 Timing in library */
+#define DDR3_400		  	0
+#define DDR3_667        1
+
+/**
+  * @}
+  */
+
+/**
+ * @brief DDR Timing Configuration
+   * @param[in] chip information ,A pointer to struct @ref MEM_CHIP_INFO
+   * @param[in] ddr A pointer to struct @ref DDR2MEM or @ref DDR3MEM that specified DDR Timing. Some typital DDR2/3 Timings are defined in arrays @ref DDR2PREDEF and @ref DDR3PREDEF.
+ * @retval void
+   */
+BOOL  DDR_Init(const MEM_CHIP_INFO *chip_info, const void *ddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_DDR_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_dma.h

+/**
+	*****************************************************************************
+	* @file     cmem7_dma.h
+	*
+	* @brief    CMEM7 DMA header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_DMA_H
+#define __CMEM7_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup DMA_Int
+  * @{
+  */
+#define DMA_Int_TfrComplete                0x00000001    
+#define DMA_Int_Err                        0x00000002
+#define DMA_Int_All                        0x00000003
+
+#define IS_DMA_INT(INT)        (((INT) != 0) && (((INT) & ~DMA_Int_All) == 0))
+/**
+  * @}
+  */ 
+
+/**
+  * @brief  Descriptor structure
+	*	@note		DMA requires users provides a list of descriptors to operation.
+	*					Meanwhile, memory occupied by descriptors should be in physical
+	*					memory and keep valid during DMA transfer.
+	*/ 
+typedef struct {                      
+	uint32_t srcAddr;                  /*!< source address 														*/		
+	uint32_t dstAddr;                  /*!< destination address 											*/	
+	uint32_t number;                   /*!< block byte number, no more than 2K Bytes 	*/
+	uint32_t nextBlock;                /*!< next block descriptor 										*/
+	uint32_t padding;                  /*!< Nonsense, only used to fill 							*/
+} BLOCK_DESC;
+	
+/**
+  * @brief  DMA initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param  None
+	* @retval None
+	*/ 
+void DMA_Init(void);
+
+/**
+  * @brief  Enable or disable DMA interrupt. 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @retval None
+	*/ 
+void DMA_EnableInt(uint32_t Int, BOOL enable);
+
+/**
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
+  * @retval BOOL The bit indicates if specific interrupts are set or not
+	*/
+BOOL DMA_GetIntStatus(uint32_t Int);
+
+/**
+  * @brief  Clear specific interrupts
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
+  * @retval None
+	*/
+void DMA_ClearInt(uint32_t Int);
+
+/**
+  * @brief  DMA transfer
+	* @note		Make sure that memory occupied by descriptors should be in physical
+	*					memory and keep valid before DMA transfer is finished (Return false by
+	*					calling DMA_IsBusy after DMA transfer started).
+	* @param[in] blockList A pointer to header of list of BLOCK_DESC
+  * @retval BOOL The bit indicates if DMA begins to transfer
+	* @see		DMA_IsBusy
+	*/
+BOOL DMA_Transfer(BLOCK_DESC *blockList);
+
+/**
+  * @brief  DMA is busy or not
+  * @param  None
+	* @retval BOOL The bit indicates if DMA is busy or not
+	*/ 
+BOOL DMA_IsBusy(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_DMA_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_efuse.h

+/**
+	*****************************************************************************
+	* @file     cmem7_efuse.h
+	*
+	* @brief    CMEM7 EFUSE header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_EFUSE_H
+#define __CMEM7_EFUSE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup EFUSE_TMRF_R
+  * @{
+  */
+#define EFUSE_TMRF_R_3000                0
+#define EFUSE_TMRF_R_1200                1
+#define EFUSE_TMRF_R_750                 2
+
+#define IS_EFUSE_TMRF(R)                 (((R) == EFUSE_TMRF_R_3000) || \
+                                          ((R) == EFUSE_TMRF_R_1200) || \
+                                          ((R) == EFUSE_TMRF_R_750))
+/**
+  * @}
+  */
+
+/**
+  * @brief  EFUSE timing structure
+	*/
+typedef struct
+{
+	uint32_t EFUSE_Tpwph;                  /*!< Nano second                                    */
+  uint32_t EFUSE_Trac;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Trah;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Trpw;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Trc;                    /*!< Nano second                                    */
+	uint32_t EFUSE_Tesr;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Tprs;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Tpi;                    /*!< Nano second                                    */
+	uint32_t EFUSE_Tpp;                    /*!< Nano second                                    */
+	uint32_t EFUSE_Teps;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Tpwps;                  /*!< Nano second                                    */
+} EFUSE_Timing;
+
+/**
+  * @brief  EFUSE initialization structure
+	*/
+typedef struct
+{
+	uint8_t EFUSE_ClockDividor;       		 /*!< EFUSE clock dividor, 2 in n times */
+	uint8_t EFUSE_TMRF;                    /*!< EFUSE reference resistor select, @ref EFUSE_TMRF_R */
+  EFUSE_Timing* timing;                  /*!< Timing configuration, null if default           */
+} EFUSE_InitTypeDef;
+
+/**
+  * @brief  EFUSE key structure
+	*/
+typedef struct
+{
+	uint32_t key0;                         /*!< EFUSE AES key [31:0]                            */
+  uint32_t key1;                         /*!< EFUSE AES key [63:32]                           */
+	uint32_t key2;                         /*!< EFUSE AES key [95:64]                           */
+	uint32_t key3;                         /*!< EFUSE AES key [127:96]                          */
+	uint32_t key4;                         /*!< EFUSE AES key [159:128]                         */
+  uint32_t key5;                         /*!< EFUSE AES key [191:160]                         */
+	uint32_t key6;                         /*!< EFUSE AES key [223:192]                         */
+	uint32_t key7;                         /*!< EFUSE AES key [255:224]                         */
+} EFUSE_AesKey;
+
+/**
+  * @brief  EFUSE initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param[in] init A pointer to structure EFUSE_InitTypeDef
+  * @retval None
+	*/ 
+void EFUSE_Init(EFUSE_InitTypeDef* init);
+
+/**
+  * @brief  EFUSE initialization
+  * @param[in] key A pointer to EFUSE_AesKey to be compared
+  * @retval BOOL True if equal, or false if different
+	*/ 
+BOOL EFUSE_Compare(EFUSE_AesKey* key);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_EFUSE_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h

+/**
+	*****************************************************************************
+	* @file     cmem7_eth.h
+	*
+	* @brief    CMEM7 ethernet header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_ETH_H
+#define __CMEM7_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup ETH_SPEED
+  * @{
+  */
+#define ETH_SPEED_10M               0x0
+#define ETH_SPEED_100M              0x1
+#define ETH_SPEED_1000M             0x2
+
+#define IS_ETH_SPEED(SPEED)    			(((SPEED) == ETH_SPEED_10M)  || \
+                                     ((SPEED) == ETH_SPEED_100M) || \
+																		 ((SPEED) == ETH_SPEED_1000M))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DUPLEX
+  * @{
+  */
+#define ETH_DUPLEX_HALF             0x0
+#define ETH_DUPLEX_FULL             0x1
+
+#define IS_ETH_DUPLEX(DUPLEX)  			(((DUPLEX) == ETH_DUPLEX_HALF) || \
+																		 ((DUPLEX) == ETH_DUPLEX_FULL))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_INT
+  * @{
+  */																			
+#define ETH_INT_TX_COMPLETE_FRAME		0x0001
+#define ETH_INT_TX_STOP             0x0002
+#define ETH_INT_TX_BUF_UNAVAI       0x0004
+#define ETH_INT_RX_OVERFLOW					0x0010
+#define ETH_INT_TX_UNDERFLOW				0x0020
+#define ETH_INT_RX_COMPLETE_FRAME   0x0040
+#define ETH_INT_RX_BUF_UNAVAI       0x0080
+#define ETH_INT_RX_STOP             0x0100
+#define ETH_INT_BUS_FATAL_ERROR     0x2000
+#define ETH_INT_ALL                 (ETH_INT_TX_COMPLETE_FRAME | \
+                                     ETH_INT_TX_STOP           | \
+																		 ETH_INT_TX_BUF_UNAVAI     | \
+																		 ETH_INT_RX_OVERFLOW       | \
+																		 ETH_INT_TX_UNDERFLOW      | \
+																		 ETH_INT_RX_COMPLETE_FRAME | \
+																		 ETH_INT_RX_BUF_UNAVAI     | \
+																		 ETH_INT_RX_STOP           | \
+																		 ETH_INT_BUS_FATAL_ERROR)
+
+#define IS_ETH_INT(INT)             (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0))
+/**
+  * @}
+  */
+
+/**
+  * @brief  EFUSE receive filter structure
+	*/
+typedef struct
+{
+	BOOL ETH_BroadcastFilterEnable;   /*!< Broadcast is dropped or passed								        */ 
+	BOOL ETH_OwnFilterEnable;	        /*!< source address filter is on or off     							*/
+	BOOL ETH_SelfDrop;				  			/*!< Only own address is dropped or passed								*/
+	BOOL ETH_SourceFilterEnable;	    /*!< source address filter is on or off     							*/
+	BOOL ETH_SourceDrop;				      /*!< Only specific source address is dropped or passed  	*/
+	uint8_t ETH_SourceMacAddr[6];     /*!< Source MAC address                                   */
+} ETH_FrameFilter;
+
+/**
+  * @brief  Ethernet initialization structure
+	*/ 
+typedef struct
+{
+  BOOL ETH_LinkUp;                   /*!< If ETH is linked up and it can be retrieved from PHY */																	  
+	uint8_t ETH_Speed;                 /*!< speed of ETH, refer as @ref ETH_SPEED                */
+  uint8_t ETH_Duplex;                /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX				 */
+	BOOL ETH_RxEn;                     /*!< Rx enable                                            */
+	BOOL ETH_TxEn;                     /*!< Tx enable                                            */
+	BOOL ETH_ChecksumOffload;          /*!< Checksum offload enable                              */
+	BOOL ETH_JumboFrame;               /*!< Jumbo Frame Enable                                   */
+	uint8_t ETH_MacAddr[6];            /*!< MAC address                                          */ 
+  ETH_FrameFilter *ETH_Filter;       /*!< Received frame address filter, receive all if null   */
+} ETH_InitTypeDef;
+
+/**
+  * @brief  Ethernet Tx descriptor structure
+	*/ 
+typedef struct { 
+	union {
+    uint32_t  TX0;
+		
+		struct {
+			uint32_t 								:  1;
+			uint32_t UNDERFLOW_ERR  :  1; 	 /*!< [OUT] Underflow error            											*/
+			uint32_t 								:  1;
+			uint32_t COLLISION_CNT	:  4;		 /*!< [OUT] Collision count				                          */
+			uint32_t 								:  1;
+			uint32_t EX_COLLISION 	:  1;		 /*!< [OUT] Excessive collision error	                      */
+			uint32_t LATE_COLLISION :  1;		 /*!< [OUT] Late collision error	                          */
+			uint32_t NO_CARRIER     :  1;		 /*!< [OUT] No carrier error                          			*/
+			uint32_t LOSS_CARRIER   :  1;		 /*!< [OUT] loss of carrier error                          	*/
+			uint32_t PAYLOAD_ERR 		:  1;		 /*!< [OUT] IP payload error                          			*/
+			uint32_t 								:  2;
+			uint32_t ERR_SUM 				:  1;		 /*!< [OUT] Error summary		                          			*/
+			uint32_t HEADER_ERR 		:  1;		 /*!< [OUT] IP header error                          				*/
+			uint32_t 								:  8;
+			uint32_t TTSE           :  1; 	 /*!< enables IEEE1588 hardware timestamping in first segment */
+			uint32_t 								:  2;
+			uint32_t FS           	:  1; 	 /*!< first segment flag                                    */
+			uint32_t LS           	:  1; 	 /*!< last segment flag                                     */
+			uint32_t 								:  2;
+		} TX0_b;
+	} TX_0;
+	
+	union {
+    uint32_t  TX1;
+		
+		struct {
+			uint32_t SIZE						: 13; 	 	/*!< buffer size                                       */
+			uint32_t                : 19;
+		} TX1_b;
+	} TX_1;
+	
+	uint32_t bufAddr;											/*!< address of buffer						                     */
+	uint32_t nextDescAddr;								/*!< address of next descriptor		                     */
+  uint64_t reserved;
+	uint64_t timeStamp;									 	/*!< time stamp while last segment                     */
+} ETH_TX_DESC;
+
+/**
+  * @brief  Ethernet Rx descriptor structure
+	*/ 
+typedef struct { 
+	union {
+    uint32_t  RX0;
+		
+		struct {
+			uint32_t 								:  1;
+			uint32_t CRC_ERR        :  1; 	 /*!< [OUT] CRC error while last segment                		*/
+			uint32_t 								:  5;
+			uint32_t TTSE           :  1; 	 /*!< timestamp available while last segment                */
+			uint32_t LS           	:  1; 	 /*!< last segment flag                                     */
+			uint32_t FS           	:  1; 	 /*!< first segment flag                                    */
+			uint32_t 								:  1;
+			uint32_t OVERFLOW_ERR   :  1; 	 /*!< [OUT] FIFO overflow while last segment                */
+			uint32_t LENGTH_ERR     :  1; 	 /*!< [OUT] length error while last segment                	*/
+			uint32_t 								:  2;
+			uint32_t ERR_SUM        :  1; 	 /*!< [OUT] Error summary while last segment              	*/
+			uint32_t FL           	: 14; 	 /*!< frame length while last segment                       */
+			uint32_t 		           	:  2;
+		} RX0_b;
+	} RX_0;
+	
+	union {
+    uint32_t  RX1;
+		
+		struct {
+			uint32_t SIZE						: 13; 	 	/*!< buffer size                                       */
+			uint32_t                : 19;
+		} RX1_b;
+	} RX_1;
+	
+	uint32_t bufAddr;											/*!< buffer address                                    */
+	uint32_t nextDescAddr;								/*!< address of next descriptor                        */
+  uint64_t reserved;
+	uint64_t timeStamp;									 	/*!< time stamp while the last segment                 */
+} ETH_RX_DESC;
+
+/**
+  * @brief  Read data from phy chip
+	* @param[in] phyAddr Address of phy chip
+	* @param[in] phyReg Address of phy's register to be read
+  * @retval uint32_t value of phy's register
+	*/
+uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg);
+
+/**
+  * @brief  Write data to phy chip
+	* @param[in] phyAddr Address of phy chip
+	* @param[in] phyReg Address of phy's register to be written
+	* @param[in] data Data to be written
+  * @retval None
+	*/
+void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data);
+
+/**
+  * @brief  Ethernet initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param[in] init A pointer to structure ETH_InitTypeDef
+  * @retval BOOL The bit indicates if ethernet is initialized successfully
+	*/ 
+BOOL ETH_Init(ETH_InitTypeDef *init);
+
+/**
+  * @brief  Enable or disable ethernet interrupt. 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @retval None
+	*/ 
+void ETH_EnableInt(uint32_t Int, BOOL enable);
+
+/**
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
+  * @retval BOOL The bit indicates if specific interrupts are set or not
+	*/
+BOOL ETH_GetIntStatus(uint32_t Int);
+
+/**
+  * @brief  Clear specific interrupts
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
+  * @retval None
+	*/
+void ETH_ClearInt(uint32_t Int);
+
+/**
+  * @brief  Get ethernte MAC address
+	* @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes.
+	* @retval None
+	*/
+void ETH_GetMacAddr(uint8_t *mac);
+
+/**
+  * @brief  Set ethernet transmission descriptor ring 
+	* @note		Make sure that memory occupied by descriptors should be in physical
+	*					memory and keep valid before ethernet transmission is finished.
+	* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node 
+	*					has a 'nextDescAddr' pointed to first node.
+  * @retval BOOL The bit indicates if valid ring is set
+	*/
+BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring);
+
+/**
+  * @brief  Start ethernet transmission
+	* @param	None
+  * @retval None
+	*/
+void ETH_StartTx(void);
+
+/**
+  * @brief  Stop ethernet transmission
+	* @param	None
+  * @retval None
+	*/
+void ETH_StopTx(void);
+
+/**
+  * @brief  Resume ethernet transmission\n
+	* 				While ethernet doesn't have enough buffer to transmit data, it will
+	*					pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users
+	*					must call this function to start ethernet again after new buffer 
+	*					prepared.
+	* @param	None
+  * @retval None
+	*/
+void ETH_ResumeTx(void);
+
+/**
+  * @brief  Get free transmission descriptor\n
+	* @param	None
+  * @retval ETH_TX_DESC* A pointer of free transmission descriptor, 
+	*					NULL if no free descriptor
+	*/
+ETH_TX_DESC *ETH_AcquireFreeTxDesc(void);
+
+/**
+  * @brief  Check if a transmission descriptor is free or not
+	* @param	desc A pointer of a transmission descriptor
+  * @retval BOOL True if the transmission descriptor is free, or flase.
+	*/
+BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
+
+/**
+  * @brief  Release a transmission descriptor to ethernet\n
+	*					After users prepared data in the buffer of a free descriptor,
+	*					They must call this function to change ownership of the 
+	*					descriptor to hardware.
+	* @param	desc A pointer of a transmission descriptor
+  * @retval None
+	*/
+void ETH_ReleaseTxDesc(ETH_TX_DESC *desc);
+
+/**
+  * @brief  Set ethernet receive descriptor ring
+	* @note		Make sure that memory occupied by descriptors should be in physical
+	*					memory and keep valid before ethernet receive is finished.
+	* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node 
+	*					has a 'nextDescAddr' pointed to first node.
+  * @retval BOOL The bit indicates if valid ring is set
+	*/
+BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring);
+
+/**
+  * @brief  Start ethernet receive
+	* @param	None
+  * @retval None
+	*/
+void ETH_StartRx(void);
+
+/**
+  * @brief  Stop ethernet receive
+	* @param	None
+  * @retval None
+	*/
+void ETH_StopRx(void);
+
+/**
+  * @brief  Resume ethernet receive\n
+	* 				While ethernet doesn't have enough buffer to receive data, it will
+	*					pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users
+	*					must call this function to start ethernet again after new buffer 
+	*					prepared.
+	* @param	None
+  * @retval None
+	*/
+void ETH_ResumeRx(void);
+
+/**
+  * @brief  Get the free descriptor which contains received data\n
+	* @param	None
+  * @retval ETH_RX_DESC* A pointer of free receive descriptor, 
+	*					NULL if no free descriptor
+	*/
+ETH_RX_DESC *ETH_AcquireFreeRxDesc(void);
+
+/**
+  * @brief  Check if a receive descriptor is free or not
+	* @param	desc A pointer of a receive descriptor
+  * @retval BOOL True if the receive descriptor is free, or flase.
+	*/
+BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
+
+/**
+  * @brief  Release a receive descriptor to ethernet\n
+	*					After users handled data in the buffer of a free descriptor,
+	*					They must call this function to change ownership of the 
+	*					descriptor to hardware.
+	* @param	desc A pointer of a transmission descriptor
+  * @retval None
+	*/
+void ETH_ReleaseRxDesc(ETH_RX_DESC *desc);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_ETH_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h

+/**
+	*****************************************************************************
+	* @file     cmem7_flash.h
+	*
+	* @brief    CMEM7 flash controller source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_FLASH_H
+#define __CMEM7_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup FLASH_PROTECT_MODE
+  * @{
+  */
+#define FLASH_PROTECT_MODE_SW           0       /*!< The Status Register can be written to after a Write 
+                                                     Enable command.(Default) */
+#define FLASH_PROTECT_MODE_HW           1       /*!< WP pin decides if the Status Register can be written 
+                                                     WP#=0, the Status Register locked
+																									   WP#=1, the Status Register is unlocked and can be written to
+                                                     after a Write Enable command */
+#define FLASH_PROTECT_MODE_POWERDOWN    2				/*!< Status Register is protected and can not be written to again
+                                                     until the next Power-Down, Power-Up cycle */	
+#define FLASH_PROTECT_MODE_OTP          3       /*!< Status Register is permanently protected */	
+
+#define IS_FLASH_PROTECT_MODE(MODE)     (((MODE) == FLASH_PROTECT_MODE_SW) || \
+                                         ((MODE) == FLASH_PROTECT_MODE_HW) || \
+                                         ((MODE) == FLASH_PROTECT_MODE_POWERDOWN) || \
+                                         ((MODE) == FLASH_PROTECT_MODE_OTP))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_PROTECT_REGION
+  * @{
+  */
+#define FLASH_PROTECT_REGION_NONE       0x00    /*!< no region is protected */
+#define FLASH_PROTECT_REGION_UP_64K     0x01    /*!< region(0F0000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_128K    0x02    /*!< region(0E0000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_256K    0x03    /*!< region(0C0000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_512K    0x04    /*!< region(080000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_64K    0x09    /*!< region(000000H-00FFFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_128K   0x0A    /*!< region(000000H-01FFFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_256K   0x0B    /*!< region(000000H-03FFFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_512K   0x0C    /*!< region(000000H-07FFFFH) is protected */
+#define FLASH_PROTECT_REGION_ALL        0x0D    /*!< region(000000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_4K      0x11    /*!< region(0FF000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_8K      0x12    /*!< region(0FE000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_16K     0x13    /*!< region(0FC000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_32K     0x14    /*!< region(0F8000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_4K     0x19    /*!< region(000000H-000FFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_8K     0x1A    /*!< region(000000H-001FFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_16K    0x1B    /*!< region(000000H-003FFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_32K    0x1C    /*!< region(000000H-007FFFH) is protected */
+
+#define IS_FLASH_PROTECT_REGION(REGION) (((REGION) == FLASH_PROTECT_REGION_NONE) || \
+                                         ((REGION) == FLASH_PROTECT_REGION_UP_64K) || \
+                                         ((REGION) == FLASH_PROTECT_REGION_UP_128K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_UP_256K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_UP_512K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_64K) || \
+                                         ((REGION) == FLASH_PROTECT_REGION_LOW_128K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_256K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_512K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_ALL) || \
+                                         ((REGION) == FLASH_PROTECT_REGION_UP_4K) || \
+                                         ((REGION) == FLASH_PROTECT_REGION_UP_8K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_UP_16K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_UP_32K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_4K) || \
+                                         ((REGION) == FLASH_PROTECT_REGION_LOW_8K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_16K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_32K))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_READ_MODE
+  * @{
+  */
+#define FLASH_READ_MODE_NORMAL         0        /*!< normal read, 1 bitwidth, highest freqency is 90MHz */
+#define FLASH_READ_MODE_FAST           1        /*!< fast read, 1 bitwidth, highest freqency is 120MHz */
+#define FLASH_READ_MODE_FAST_DUAL      2        /*!< fast read, 2 bitwidth, highest freqency is 120MHz */
+#define FLASH_READ_MODE_FAST_QUAD      3        /*!< fast read, 4 bitwidth, highest freqency is 90MHz */
+
+#define IS_FLASH_READ_MODE(MODE)       (((MODE) == FLASH_READ_MODE_NORMAL) || \
+                                        ((MODE) == FLASH_READ_MODE_FAST) || \
+                                        ((MODE) == FLASH_READ_MODE_FAST_DUAL) || \
+																				((MODE) == FLASH_READ_MODE_FAST_QUAD))																								
+/**
+  * @}
+  */
+
+/**
+  * @brief  UART initialization structure
+	*/ 
+typedef struct
+{
+  uint8_t FLASH_ClockDividor;       /*!< flash clock dividor, 2 in n times */
+	uint8_t FLASH_ProtectMode;        /*!< Status Register protection mode */
+	uint8_t FLASH_ProtectRegion;      /*!< flash protection region */
+	BOOL FLASH_QuadEnable;            /*!< if allows Quad operation */
+	void (*FLASH_Wait)(void);         /*!< When the former read or write operation is excuting, 
+	                                       Flash has to call a callback to wait it finish. 
+	                                       If null, Flash will wait forever until finish */
+} FLASH_InitTypeDef;
+
+/**
+  * @brief  flash initialization
+  * @note   This function should be called at first before any other interfaces.
+	*					Users should make sure that doesn't erase or write data in a 
+	*					write-protected region.
+	* @param[in] init A pointer to structure FLASH_InitTypeDef
+  * @retval None
+	*/ 
+void FLASH_Init(FLASH_InitTypeDef* init);
+
+/**
+  * @brief  Get flash status 
+  * @param[out] ProtectMode flash protect mode, ref as @ref FLASH_PROTECT_MODE
+  * @param[out] ProtectRegion flash protect region, ref as @ref FLASH_PROTECT_REGION
+	* @param[out] QuadEnable quad speed mode enable bit
+	* @retval None
+	*/ 
+void FLASH_GetStatus(uint8_t* ProtectMode, uint8_t* ProtectRegion, BOOL* QuadEnable);
+
+/**
+  * @brief  Erase a sector, which is 4K bytes large.
+  * @param[in] addr Start address of a sector
+	* @retval None
+	*/
+void FLASH_EraseSector(uint32_t addr);
+
+/**
+  * @brief  Erase a block, which is 32K bytes large.
+  * @param[in] addr Start address of a block
+	* @retval None
+	*/
+void FLASH_Erase32kBlock(uint32_t addr);
+
+/**
+  * @brief  Erase a block, which is 64K bytes large.
+  * @param[in] addr Start address of a block
+	* @retval None
+	*/
+void FLASH_Erase64kBlock(uint32_t addr);
+
+/**
+  * @brief  Erase all chip
+  * @param	None
+	* @retval None
+	*/
+void FLASH_EraseChip(void);
+
+/**
+  * @brief  Enable flash power down mode or not
+  * @param[in] enable The bit indicates if flash power down mode is enable or not
+	* @retval None
+	*/
+void FLASH_EnableDeepPowerDown(BOOL enable);
+
+/**
+  * @brief  Read data from flash
+	* @param[in] ReadMode Normal or fast read, ref as @ref FLASH_READ_MODE
+	* @param[in] addr Start address to be read
+	* @param[in] size Expected data size to be read
+	* @param[out] data A user-allocated buffer to fetch data to be read
+  * @retval None
+	*/
+void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data);
+
+/**
+  * @brief  Write data to flash
+	* @param[in] addr Start address to be read
+	* @param[in] size Expected data size to be read
+	* @param[out] data A pointer to the data to be written
+  * @retval None
+	*/
+void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_FLASH_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h

+/**
+	*****************************************************************************
+	* @file     cmem7_gpio.h
+	*
+	* @brief    CMEM7 GPIO header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_GPIO_H
+#define __CMEM7_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup GPIO_GROUP
+  * @{
+  */
+typedef enum {
+	GPIO_GROUP_GPIO,
+} GPIO_GROUP;
+
+#define IS_GPIO_GROUP(GROUP)  (((GROUP) == GPIO_GROUP_GPIO))
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_PWM_CHANNEL
+  * @{
+  */
+typedef enum {
+	GPIO_PWM_CHANNEL_GPIO_31,
+} GPIO_PWM_CHANNEL;
+        
+#define IS_GPIO_PWM_CHANNEL(CHANNEL)  (((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_31))
+/**
+  * @}
+  */
+	
+/**
+  * @brief  GPIO initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @param[in] PositiveTrigger Positive edge interrupt trigger if true, or negative edge
+  * @retval None
+	*/ 	
+void GPIO_Init(uint8_t Group, uint32_t PositiveTrigger);
+
+/**
+  * @brief  Enable or disable GPIO output in the specific group. 
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @param[in] Enable each bit indicates if the corresponding GPIO pin 
+	*						in the specific GPIO group is enable or not
+  * @retval None
+	*/ 
+void GPIO_EnableOutput(uint8_t Group, uint32_t Enable);
+
+/**
+  * @brief  Enable or disable GPIO interrupt in the specific group. 
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @param[in] Enable each bit indicates if the corresponding GPIO pin interrupt 
+	*						in the specific GPIO group is enable or not
+  * @retval None
+	*/ 
+void GPIO_EnableInt(uint8_t Group, uint32_t Enable);
+
+/**
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @retval uint32_t each bit indicates if the corresponding GPIO pin interrupt 
+	*					in the specific GPIO group is set or not
+	*/
+uint32_t GPIO_GetIntStatus(uint8_t Group);
+
+/**
+  * @brief  Clear GPIO interrupt in the specific group. 
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @param[in] Clear each bit indicates if the corresponding GPIO pin interrupt 
+	*						in the specific GPIO group is clear or not
+  * @retval None
+	*/ 
+void GPIO_ClearInt(uint8_t Group, uint32_t Clear);
+
+/**
+  * @brief  Get value of each GPIO pin in the specific group
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @retval uint32_t each bit indicates value of the corresponding GPIO pin 
+	*					in the specific GPIO group
+	*/
+uint32_t GPIO_Read(uint8_t Group);
+
+/**
+  * @brief  Set value of each GPIO pin in the specific group
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @param[in] Unmask each bit indicates value of the corresponding GPIO pin 
+	*						 in the specific GPIO group is set or not
+	* @param[in] data each bit indicates value of the corresponding GPIO pin
+	*						 in the specific GPIO group to be set
+  * @retval None
+	*/ 
+void GPIO_Write(uint8_t Group, uint32_t Unmask, uint32_t data);
+
+/**
+  * @brief  Initialize PWM for the specific GPIO pin
+	* @note		It can work before call GPIO_EnableOutput for the specific GPIO pin
+	* @param[in] Channel PWM channel, which is a value of @ref GPIO_PWM_CHANNEL
+	* @param[in] HighLevelNanoSecond Nanosecond which high level lasts 
+	* @param[in] LowLevelNanoSecond Nanosecond which low level lasts 
+  * @retval None
+	* @see		GPIO_EnableOutput
+	*/ 
+void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLevelNanoSecond);
+
+/**
+  * @brief  Enable or disable GPIO PWM in the specific channel. 
+	*	@param[in] Channel PWM channel, which is a value of @ref GPIO_PWM_CHANNEL
+	* @param[in] Enable The bit indicates if the specific channel is enable or not
+  * @retval None
+	*/ 
+void GPIO_EnablePwm(uint8_t Channel, BOOL Enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_GPIO_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_i2c.h

+/**
+	*****************************************************************************
+	* @file     cmem7_i2c.h
+	*
+	* @brief    CMEM7 I2C header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_I2C_H
+#define __CMEM7_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C0) || \
+                                   ((PERIPH) == I2C1))
+
+/** @defgroup I2C_Mode
+  * @{
+  */
+#define I2C_Mode_Slave                  0
+#define I2C_Mode_Master                 1
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_Slave) || \
+                           ((MODE) == I2C_Mode_Master))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ADDR_WIDTH
+  * @{
+  */
+#define I2C_ADDR_WIDTH_7BIT                  0
+#define I2C_ADDR_WIDTH_10BIT                 1
+#define IS_I2C_ADDR_WIDTH(WIDTH) (((WIDTH) == I2C_ADDR_WIDTH_7BIT) || \
+                                  ((WIDTH) == I2C_ADDR_WIDTH_10BIT))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_INT
+  * @{
+  */			
+#define I2C_INT_RX_FIFO_NOT_EMPTY      0x00000004 		/*!< Can't be clear but read FIFO */
+#define I2C_INT_RD_REQUEST             0x00000020     /*!< Slave was requested to send data */
+#define I2C_INT_TX_ABORT               0x00000040     /*!< Error while sending data */
+#define I2C_INT_RX_DONE                0x00000080     /*!< Slave sent all requested data */
+#define I2C_INT_TX_DONE                0x00000100     /*!< Master accomplish to send all data */
+
+#define I2C_INT_ALL                    (I2C_INT_RX_FIFO_NOT_EMPTY | \
+																				I2C_INT_RD_REQUEST | \
+																				I2C_INT_TX_ABORT | \
+																				I2C_INT_RX_DONE | \
+																				I2C_INT_TX_DONE)
+
+#define IS_I2C_INT(INT)                (((INT) != 0) && (((INT) & ~I2C_INT_ALL) == 0))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_STATUS
+  * @{
+  */
+#define I2C_STATUS_RX_FIFO_NOT_EMPTY   0x00200000 		/*!< Can't be clear but read FIFO */
+#define I2C_STATUS_RD_REQUEST          0x01000000     /*!< Slave was requested to send data */
+#define I2C_STATUS_TX_ABORT            0x02000000     /*!< Error while sending data */
+#define I2C_STATUS_RX_DONE             0x04000000     /*!< Slave sent all requested data */
+#define I2C_STATUS_TX_DONE             0x08000000     /*!< Master accomplish to send all data */
+
+#define I2C_STATUS_ALL                 (I2C_STATUS_RX_FIFO_NOT_EMPTY | \
+																				I2C_STATUS_RD_REQUEST | \
+																				I2C_STATUS_TX_ABORT | \
+																				I2C_STATUS_RX_DONE | \
+																				I2C_STATUS_TX_DONE)
+
+#define IS_I2C_STATUS(STATUS)          (((STATUS) != 0) && (((STATUS) & ~I2C_STATUS_ALL) == 0))
+/**
+  * @}
+  */
+
+/**
+  * @brief  I2C timing structure
+	*/
+typedef struct
+{
+  uint32_t I2C_Freq;                /*!< I2C frquency */
+
+	uint16_t I2C_TsuDat;              /*!< nano second of TSU:DAT */
+  uint16_t I2C_Tsetup;              /*!< nano second of THD:STA and TSU:STO */ 
+  uint16_t I2C_Tbuf;                /*!< nano second of TBUF */       	
+	uint16_t I2C_TsuSta;              /*!< nano second of TSU:STA */ 
+	
+	BOOL I2C_SdaFilterEn;             /*!< enabled flag of SDA filter */
+	uint8_t I2C_SdaFilterSpike;       /*!< spikes of SDA filter */
+	BOOL I2C_SclFilterEn;             /*!< enabled flag of SCL filter */
+	uint8_t I2C_SclFilterSpike;       /*!< spikes of SCL filter */
+	
+} I2C_InitTimingDef;
+
+/**
+  * @brief  I2C initialization structure
+	*/
+typedef struct
+{
+  uint8_t I2C_Mode;                 /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode */
+	uint8_t I2C_AddressWidth;         /*!< 7- or 10-bits width address, ref as @ref I2C_ADDR_WIDTH */
+	uint8_t I2C_Address;              /*!< 7- or 10-bits address */
+	I2C_InitTimingDef* timing;        /*!< timing structure, null if don't set */		
+} I2C_InitTypeDef;
+
+/**
+  * @brief  I2C initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] init A pointer to structure I2C_InitTypeDef
+  * @retval None
+	*/ 
+void I2C_Init(I2C0_Type* I2Cx, I2C_InitTypeDef* I2C_Init);
+
+/**
+  * @brief  Enable or disable I2C. 
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Enable The bit indicates if the specific I2C is enable or not
+  * @retval None
+	*/ 
+void I2C_Enable(I2C0_Type* I2Cx, BOOL enable);
+
+/**
+  * @brief  Enable or disable I2C interrupt. 
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @retval None
+	*/ 
+void I2C_EnableInt(I2C0_Type* I2Cx, uint32_t Int, BOOL enable);
+
+/**
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
+  * @retval BOOL The bit indicates if specific interrupts are enable or not
+	*/
+BOOL I2C_GetIntStatus(I2C0_Type* I2Cx, uint32_t Int);
+
+/**
+  * @brief  Clear specific interrupts
+	* @note   Specific interrupt clear will clear correspective status as well
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
+  * @retval None
+	*/
+void I2C_ClearInt(I2C0_Type* I2Cx, uint32_t Int);
+
+/**
+  * @brief  Check specific status are set or not 
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
+  * @retval BOOL The bit indicates if specific status are set or not
+	*/
+BOOL I2C_GetStatus(I2C0_Type* I2Cx, uint32_t Status);
+
+/**
+  * @brief  Clear specific status
+	* @note   Specific status clear will clear correspective interrupt as well
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
+  * @retval None
+	*/
+void I2C_ClearStatus(I2C0_Type* I2Cx, uint32_t Status);
+
+/**
+  * @brief  I2C send read request in master mode
+	* @note   Users must call I2C_StopReq between 2 requests
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] size Expected data size to be read
+  * @retval BOOL The bit indicates if read request to be sent is valid
+	* @see		I2C_StopReq
+	*/
+BOOL I2C_MasterReadReq(I2C0_Type* I2Cx, uint8_t size);
+
+/**
+  * @brief  Read data from I2C
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] size Expected data size to be read
+	* @param[out] Data A user-allocated buffer to fetch data to be read
+  * @retval uint8_t Actual read data size
+	*/
+uint8_t I2C_ReadFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data);
+
+/**
+  * @brief  I2C send write request in master or slave mode
+	* @note   Users must call I2C_StopReq between 2 requests
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] size Expected data size to be written, includes the first data
+	* @param[in] firstData The first data to be written
+  * @retval BOOL The bit indicates if write request to be sent is valid
+	* @see		I2C_StopReq
+	*/
+BOOL I2C_WriteReq(I2C0_Type* I2Cx, uint8_t size, uint8_t firstData);
+
+/**
+  * @brief  Write data to I2C
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] size Expected data size to be written
+	* @param[in] Data A pointer to the data to be written
+  * @retval uint8_t Actual written data size
+	*/
+uint8_t I2C_WriteFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data);
+
+/**
+  * @brief  I2C stop request
+	* @note   Users must call I2C_StopReq between 2 requests
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @retval BOOL The bit indicates if request is stopped.
+	* @see		I2C_MasterReadReq I2C_WriteReq 
+	*/
+BOOL I2C_StopReq(I2C0_Type* I2Cx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CMEM7_I2C_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h

+/**
+	*****************************************************************************
+	* @file     cmem7_includes.h
+	*
+	* @brief    CMEM7 includes file, easy to use CMEM7 library
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+
+#ifndef __CMEM7_INCLUDES_H
+#define __CMEM7_INCLUDES_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7_conf.h"
+#include "cmem7_it.h"
+	 
+#ifdef _ADC
+	#include "cmem7_adc.h"
+#endif
+	 
+#ifdef _AES
+	#include "cmem7_aes.h"
+#endif
+	 
+#ifdef _CAN
+	#include "cmem7_can.h"
+#endif
+	 
+#ifdef _DDR
+	#include "cmem7_ddr.h"
+#endif
+	 
+#ifdef _DMA
+	#include "cmem7_dma.h"
+#endif
+	 
+#ifdef _EFUSE
+	#include "cmem7_efuse.h"
+#endif
+	 
+#ifdef _ETH
+	#include "cmem7_eth.h"
+#endif
+	 
+#ifdef _FLASH
+	#include "cmem7_flash.h"
+#endif
+	 
+#ifdef _GPIO
+	#include "cmem7_gpio.h"
+#endif
+	 
+#ifdef _I2C
+	#include "cmem7_i2c.h"
+#endif
+	 
+#ifdef _MISC
+	#include "cmem7_misc.h"
+#endif
+	 
+#ifdef _RTC
+	#include "cmem7_rtc.h"
+#endif
+	 
+#ifdef _SPI
+	#include "cmem7_spi.h"
+#endif
+	 
+#ifdef _TIM
+	#include "cmem7_tim.h"
+#endif
+	 
+#ifdef _UART
+	#include "cmem7_uart.h"
+#endif
+
+#ifdef _USB
+	#include "cmem7_usb.h"
+#endif
+
+#ifdef _WDG
+	#include "cmem7_wdg.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_INCLUDES_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h

+/**
+	*****************************************************************************
+	* @file     cmem7_misc.h
+	*
+	* @brief    CMEM7 miscellaneous header file
+	* 
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_MISC_H
+#define __CMEM7_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/**
+  * @brief  NVIC initialization structure
+	*/
+/**
+@code  
+	The table below gives the allowed values of the pre-emption priority and subpriority according
+	to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+	============================================================================================================================
+		NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+	============================================================================================================================
+	 NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+												 |                                   |                             |   4 bits for subpriority
+	----------------------------------------------------------------------------------------------------------------------------
+	 NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+												 |                                   |                             |   3 bits for subpriority
+	----------------------------------------------------------------------------------------------------------------------------    
+	 NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+												 |                                   |                             |   2 bits for subpriority
+	----------------------------------------------------------------------------------------------------------------------------    
+	 NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+												 |                                   |                             |   1 bits for subpriority
+	----------------------------------------------------------------------------------------------------------------------------    
+	 NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+												 |                                   |                             |   0 bits for subpriority                       
+	============================================================================================================================
+@endcode
+	*/
+	
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be a value of @ref IRQn_Type 
+                                                   (For the complete Capital-micro Devices IRQ Channels list, please
+                                                    refer to cmem7.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  BOOL NVIC_IRQChannelCmd;                    /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+ 
+
+/** @defgroup NVIC_VectTab
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup NVIC_LP
+  * @{
+  */
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup NVIC_PriorityGroup
+  * @{
+  */
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+/**
+  * @}
+  */
+	
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
+  *   This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup:
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+  *                                4 bits for subpriority
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+  *                                3 bits for subpriority
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+  *                                2 bits for subpriority
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+  *                                1 bits for subpriority
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+  *                                0 bits for subpriority
+  * @retval None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+  *   This parameter can be one of the following values, ref as @ref NVIC_VectTab:
+  *     @arg NVIC_VectTab_RAM
+  *     @arg NVIC_VectTab_FLASH
+  * @param  Offset: Vector Table base offset field. This value must be a multiple 
+  *         of 0x200.
+  * @retval None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *   This parameter can be one of the following values, ref as @ref NVIC_LP:
+  *     @arg NVIC_LP_SEVONPEND
+  *     @arg NVIC_LP_SLEEPDEEP
+  *     @arg NVIC_LP_SLEEPONEXIT
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState);
+
+/**
+  * @brief  Memory map from address 'from' to 'address 'to' and open icache or not
+	* @param[in] from address to be mapped from
+	* @param[in] to address to be mapped to
+	* @param[in] isIcacheOn icache is on or off
+  * @retval None
+	*/
+void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn);
+
+/**
+  * @brief  Set NMI irq number, it should be one of @ref IRQn_Type.
+	* @Note		You can assign any valid IRQn_Type to NMI. After that, you will enter NMI 
+	*					interrupt routine if the specific 'irq' occurs. By default, NMI irq number
+	*					is 0, same as ETH_INT_IRQn
+	* @param[in] irq irq number 
+  * @retval None
+	*/
+void GLB_SetNmiIrqNum(uint32_t irq);
+
+/** @defgroup SYS_CLK_SEL
+  * @{
+  */
+#define SYS_CLK_SEL_OSC					0x0
+#define SYS_CLK_SEL_DLL					0x1
+#define SYS_CLK_SEL_CRYSTAL			0x2
+#define SYS_CLK_SEL_EXTERNAL		0x3	
+/**
+  * @}
+  */
+	
+/**
+  * @brief  Select system clock source, it should be one of @ref SYS_CLK_SEL.
+	* @Note		You MUST make sure externel clock has been stabled if clock 
+	*				  source is external before call this function. 
+	* 				Default value is SYS_CLK_SEL_OSC
+	* @param[in] irq irq number 
+  * @retval None
+	*/
+void GLB_SelectSysClkSource(uint8_t source);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_MISC_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_retarget.h

+/**
+	*****************************************************************************
+	* @file     cmem7_retarget.h
+	*
+	* @brief    CMEM7 retarget header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+
+#ifndef __CMEM7_RETARGET_H
+#define __CMEM7_RETARGET_H
+
+#include <stdio.h>
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+#pragma import(__use_no_semihosting_swi)
+
+struct __FILE { int handle; /* Add whatever you need here */ };
+FILE __stdout;
+FILE __stdin;
+FILE __stderr;
+
+
+int fputc(int c, FILE *f) {
+  uint8_t ch = c;
+	if (c == '\n')  {
+		ch = '\r';
+    while (0 == UART_Write(PRINT_UART, 1, &ch));
+		ch = '\n';
+  }
+	
+	while (0 == UART_Write(PRINT_UART, 1, &ch)) ;
+  return ch;
+}
+
+
+int fgetc(FILE *f) {
+	uint8_t ch;
+	
+	while (0 == UART_Read(PRINT_UART, 1, &ch)) ;
+  return ch;
+}
+
+int ferror(FILE *f) {
+  /* Your implementation of ferror */
+  return EOF;
+}
+
+
+void _ttywrch(int c) {
+  while (0 == UART_Write(PRINT_UART, 1, (uint8_t *)&c));
+}
+
+
+void _sys_exit(int return_code) {
+label:  goto label;  /* endless loop */
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_RETARGET_H */

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h

+/**
+	*****************************************************************************
+	* @file     cmem7_rtc.h
+	*
+	* @brief    CMEM7 RTC header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_RTC_H
+#define __CMEM7_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup RTC_Int
+  * @{
+  */
+#define RTC_Int_Second                     ((uint32_t)0x00000001)
+#define RTC_Int_Microsecond                ((uint32_t)0x00000002)
+#define RTC_Int_All                        ((uint32_t)0x00000003)
+#define IS_RTC_INT(INT)                    (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0))
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enable or disable RTC interrupt. 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @retval None
+	*/ 
+void RTC_EnableInt(uint32_t Int, BOOL Enable);
+
+/**
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
+  * @retval BOOL The bit indicates if specific interrupts are set or not
+	*/
+BOOL RTC_GetIntStatus(uint32_t Int);
+
+/**
+  * @brief  Clear specific interrupts
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
+  * @retval None
+	*/
+void RTC_ClearInt(uint32_t Int);
+
+/**
+  * @brief  Get seconds since power up
+	* @param	None
+  * @retval uint32_t Seconds since power up
+	*/
+uint32_t RTC_GetSecond(void);
+
+/**
+  * @brief  Get current micro-seconds
+	* @param	None
+  * @retval uint32_t Current micro-seconds
+	*/
+uint16_t RTC_GetMicroSecond(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_RTC_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_spi.h

+/**
+	*****************************************************************************
+	* @file     cmem7_spi.h
+	*
+	* @brief    CMEM7 SPI header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_SPI_H
+#define __CMEM7_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI0) || \
+                                   ((PERIPH) == SPI1))
+
+
+/** @defgroup SPI_MODE
+  * @{
+  */
+#define SPI_MODE_CPOL_0_CPHA_0         0   	/*!< CPOL : Idle clock level is low level. 
+																								 CPHA : Capture data at the first edge */
+#define SPI_MODE_CPOL_0_CPHA_1         1		/*!< CPOL : Idle clock level is low level. 
+																								 CPHA : Capture data at the second edge */	
+#define SPI_MODE_CPOL_1_CPHA_0         2		/*!< CPOL : Idle clock level is high level. 
+																								 CPHA : Capture data at the first edge */
+#define SPI_MODE_CPOL_1_CPHA_1         3	 	/*!< CPOL : Idle clock level is high level. 
+																								 CPHA : Capture data at the first edge */    
+#define IS_SPI_MODE(MODE)              (((MODE) == SPI_MODE_CPOL_0_CPHA_0) || \
+                                        ((MODE) == SPI_MODE_CPOL_0_CPHA_1) || \
+                                        ((MODE) == SPI_MODE_CPOL_1_CPHA_0) || \
+																				((MODE) == SPI_MODE_CPOL_1_CPHA_1))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_INT
+  * @{
+  */	
+#define SPI_INT_RX_FIFO_UNDERFLOW      0x00000001    
+#define SPI_INT_RX_FIFO_OVERFLOW       0x00000002
+#define SPI_INT_RX_FIFO_ALMOST_FULL    0x00000004
+#define SPI_INT_TX_FIFO_UNDERFLOW      0x00000008    
+#define SPI_INT_TX_FIFO_OVERFLOW       0x00000010
+#define SPI_INT_TX_FIFO_ALMOST_FULL    0x00000020
+#define SPI_INT_DONE                   0x00000040
+#define SPI_INT_ALL                    0x0000007F
+
+#define IS_SPI_INT(INT)                (((INT) != 0) && (((INT) & ~SPI_INT_ALL) == 0))
+/**
+  * @}
+  */
+
+/**
+  * @brief  SPI initialization structure
+	*/ 
+typedef struct
+{
+  uint8_t SPI_Mode;                 /*!< indicates SPI's CPOL and CPHA, ref as @ref SPI_MODE */
+  BOOL SPI_RxEn;                    /*!< indicates if SPI receiver is enabled or not */
+  uint8_t SPI_BitLength;            /*!< bit length while transmitting and receiving */
+  uint8_t SPI_Gap;                  /*!< cycle number between continuous data frame */ 
+	uint8_t SPI_ClockDividor;         /*!< SPI clock dividor, 1 / ((1 + DIV) * 2) */
+} SPI_InitTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @brief  SPI initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] init A pointer to structure SPI_InitTypeDef
+  * @retval None
+	*/ 
+void SPI_Init(SPI0_Type* SPIx, SPI_InitTypeDef *init);
+
+/**
+  * @brief  Enable or disable SPI. 
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] Enable The bit indicates if the specific SPI is enable or not
+  * @retval None
+	*/ 
+void SPI_Enable(SPI0_Type* SPIx, BOOL enable);
+
+/**
+  * @brief  Enable or disable SPI interrupt. 
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @retval None
+	*/ 
+void SPI_EnableInt(SPI0_Type* SPIx, uint32_t Int, BOOL enable);
+
+/**
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
+  * @retval BOOL The bit indicates if specific interrupts are set or not
+	*/
+BOOL SPI_GetIntStatus(SPI0_Type* SPIx, uint32_t Int);
+
+/**
+  * @brief  Clear specific interrupts
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
+  * @retval None
+	*/
+void SPI_ClearInt(SPI0_Type* SPIx, uint32_t Int);
+
+/**
+  * @brief  Read data from SPI FIFO
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] size Expected data size to be read
+	* @param[out] data A user-allocated buffer to fetch data to be read
+  * @retval uint8_t Actual read data size
+	*/
+uint8_t SPI_ReadFifo(SPI0_Type* SPIx, uint8_t size, uint32_t* data);
+
+/**
+  * @brief  Write data to SPI FIFO
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] size Expected data size to be written
+	* @param[in] data A pointer to the data to be written
+  * @retval uint8_t Actual written data size
+	*/
+uint8_t SPI_WriteFifo(SPI0_Type* SPIx, uint8_t Size, uint32_t* data);
+
+/**
+  * @brief  send a SPI transcation request 
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] size Expected data size to be written and read
+	* @retval BOOL The bit indicates if the request is sent
+	*/
+BOOL SPI_Transcation(SPI0_Type* SPIx, uint8_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CMEM7_SPI_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_tim.h

+/**
+	*****************************************************************************
+	* @file     cmem7_tim.h
+	*
+	* @brief    CMEM7 timer header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_TIM_H
+#define __CMEM7_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIMER0) || \
+                                   ((PERIPH) == TIMER1) || \
+                                   ((PERIPH) == TIMER2) || \
+                                   ((PERIPH) == TIMER3))
+																	 
+/**
+  * @brief  Timer initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @param[in] Ms overflow micro-seconds of the specific timer
+  * @retval None
+	*/
+void TIM_Init(TIMER0_Type* Timx, uint16_t Ms);
+
+/**
+  * @brief  Enable or disable timer interrupt. 
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @param[in] Enable The bit indicates if the specific interrupt is enable or not
+  * @retval None
+	*/ 
+void TIM_EnableInt(TIMER0_Type* Timx, BOOL Enable);
+
+/**
+  * @brief  Check the specific interrupt is set or not 
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @retval BOOL The bit indicates if the specific interrupt is set or not
+	*/
+BOOL TIM_GetIntStatus(TIMER0_Type* Timx);
+
+/**
+  * @brief  Clear specific interrupts
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @retval None
+	*/
+void TIM_ClearInt(TIMER0_Type* Timx);
+
+/**
+  * @brief  Enable or disable timer. 
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @param[in] Enable The bit indicates if the specific timer is enable or not
+  * @retval None
+	*/ 
+void TIM_Enable(TIMER0_Type* Timx, BOOL Enable);
+
+/**
+  * @brief  Check the specific timer is overflow or not 
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @retval BOOL The bit indicates if the specific timer is overflow or not
+	*/
+BOOL TIM_IsOverflow(TIMER0_Type* Timx);
+
+/**
+  * @brief  Get current counter of timer
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @retval uint32_t current counter
+	*/
+uint32_t TIM_GetCounter(TIMER0_Type* Timx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CMEM7_TIM_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_uart.h

+/**
+	*****************************************************************************
+	* @file     cmem7_uart.h
+	*
+	* @brief    CMEM7 uart header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+
+#ifndef __CMEM7_UART_H
+#define __CMEM7_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+#define IS_UART_ALL_PERIPH(PERIPH) (((PERIPH) == UART0) || \
+                                     ((PERIPH) == UART1) || \
+                                     ((PERIPH) == UART2))
+	
+/** @defgroup UART_StopBits
+  * @{
+  */
+#define UART_StopBits_0_5                 0
+#define UART_StopBits_1                   1
+#define UART_StopBits_1_5                 2
+#define UART_StopBits_2                   3
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
+                                     ((STOPBITS) == UART_StopBits_0_5) || \
+                                     ((STOPBITS) == UART_StopBits_2) || \
+                                     ((STOPBITS) == UART_StopBits_1_5))
+/**
+  * @}
+  */
+
+/** @defgroup UART_Parity
+  * @{
+  */
+#define UART_Parity_Even                  0
+#define UART_Parity_Odd                   1
+#define UART_Parity_None                  2
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_Even) || \
+                                 ((PARITY) == UART_Parity_Odd) || \
+																 ((PARITY) == UART_Parity_None))										 
+/**
+  * @}
+  */
+
+/** @defgroup UART_Int
+  * @{
+  */
+#define UART_Int_RxNotEmpty               0x00000001    
+#define UART_Int_TxEmpty                  0x00000002
+#define UART_Int_TxHalfEmpty              0x00000004
+#define UART_Int_TxTimeoutNotEmpty        0x00000008
+#define UART_Int_TxTimeoutEmpty           0x00000010
+#define UART_Int_RxHalfFull               0x00000020
+#define UART_Int_TxFull                   0x00000040
+#define UART_Int_ParityError              0x00000080
+#define UART_Int_FrameError               0x00000100
+#define UART_Int_OverrunError             0x00000200
+#define UART_Int_RxThresholdReach         0x00000400
+#define UART_Int_All                      0x000007FF
+
+#define IS_UART_INT(INT)        (((INT) != 0) && (((INT) & ~UART_Int_All) == 0))
+
+/**
+  * @}
+  */
+	
+/**
+  * @brief  UART initialization structure
+	*/ 
+typedef struct
+{
+	uint32_t UART_BaudRate;            /*!< Baudrate */																	  
+	uint8_t UART_StopBits;             /*!< Specifies the number of stop bits transmitted, 
+																					It's a value of @ref UART_StopBits */
+	uint8_t UART_Parity;               /*!< Specifies the parity mode. 
+																					It's a value of @ref UART_Parity */
+	BOOL UART_LoopBack;                /*!< loop back mode */
+	BOOL UART_RxEn;                    /*!< Receive enable bit */
+	BOOL UART_CtsEn;                   /*!< Clear to set */
+} UART_InitTypeDef;
+
+/**
+  * @brief  UART initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] init A pointer to structure UART_InitTypeDef
+  * @retval None
+	*/ 
+void UART_Init(UART0_Type* UARTx, UART_InitTypeDef *init);
+
+/**
+  * @brief  Enable or disable UART interrupt. 
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @retval None
+	*/ 
+void UART_EnableInt(UART0_Type* UARTx, uint32_t Int, BOOL Enable);
+
+/**
+  * @brief  Enable or disable UART. 
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Enable The bit indicates if the specific UART is enable or not
+  * @retval None
+	*/ 
+void UART_Enable(UART0_Type* UARTx, BOOL enable);
+
+/**
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
+  * @retval BOOL The bit indicates if specific interrupts are set or not
+	*/
+BOOL UART_GetIntStatus(UART0_Type* UARTx, uint32_t Int);
+
+/**
+  * @brief  Clear specific interrupts
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
+  * @retval None
+	*/
+void UART_ClearInt(UART0_Type* UARTx, uint32_t Int);
+
+/**
+  * @brief  Write data to UART
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Size Expected data size to be written
+	* @param[in] Data A pointer to the data to be written
+  * @retval uint8_t Actual written data size
+	*/
+uint8_t UART_Write(UART0_Type* UARTx, uint8_t Size, uint8_t* Data);
+
+/**
+  * @brief  Read data from UART
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Size Expected data size to be read
+	* @param[out] Data A user-allocated buffer to fetch data to be read
+  * @retval uint8_t Actual read data size
+	*/
+uint8_t UART_Read(UART0_Type* UARTx, uint8_t Size, uint8_t* Data);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_UART_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h

+/**
+	*****************************************************************************
+	* @file     cmem7_wdg.h
+	*
+	* @brief    CMEM7 watchdog header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#ifndef __CMEM7_WDG_H
+#define __CMEM7_WDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup WDG_INT
+  * @{
+  */
+#define WDG_INT_QUARTER                 0
+#define WDG_INT_HALF                    1
+#define IS_WDG_INT(INT)                 (((INT) == WDG_INT_QUARTER) || \
+                                         ((INT) == WDG_INT_HALF))
+/**
+  * @}
+  */
+
+/** @defgroup WDG_TRIGGER_MODE
+  * @{
+  */
+#define WDG_TRIGGER_MODE_EDGE           0
+#define WDG_TRIGGER_MODE_LEVEL          1
+#define IS_WDG_TRIGGER_MODE(TRI)        (((TRI) == WDG_TRIGGER_MODE_EDGE) || \
+                                         ((TRI) == WDG_TRIGGER_MODE_LEVEL))
+/**
+  * @}
+  */
+
+/**
+  * @brief  Watchdog initialization
+  * @note   This function should be called at first before any other interfaces.
+	* @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE
+	* @param[in] ResetMicroSecond MicroSeconds lasts before global reset
+  * @retval None
+	*/ 
+void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond);
+
+/**
+  * @brief  Enable or disable watchdog interrupt. 
+	* @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT
+	* @param[in] Enable The bit indicates if the specific interrupt are enable or not
+  * @retval None
+	*/ 
+void WDG_EnableInt(uint8_t Int, BOOL Enable);
+
+/**
+  * @brief  Check the specific interrupt are set or not 
+	* @param	None
+  * @retval BOOL The bit indicates if the specific interrupt are set or not
+	*/
+BOOL WDG_GetIntStatus(void);
+
+/**
+  * @brief  Clear the specific interrupt
+	* @param	None
+  * @retval None
+	*/
+void WDG_ClearInt(void);
+
+/**
+  * @brief  Enable or disable watchdog. 
+	* @param[in] Enable The bit indicates if watchdog is enable or not
+  * @retval None
+	*/ 
+void WDG_Enable(BOOL Enable);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_WDG_H */
+

bsp/CME_M7/StdPeriph_Driver/inc/system_cmem7.h

+/**
+	*****************************************************************************
+	* @file     system_cmem7.h
+	*
+	* @brief    CMEM7 system initial header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note      
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+
+#ifndef __SYSTEM_CMEM7_H
+#define __SYSTEM_CMEM7_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @note   This function should be used only after reset.
+	* @param  None
+  * @retval None
+	*/  
+void SystemInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_CMEM7_H */
+

bsp/CME_M7/StdPeriph_Driver/src/cmem7_aes.c

+/**
+	*****************************************************************************
+	* @file     cmem7_aes.c
+	*
+	* @brief    CMEM7 AES source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
+#include "cmem7_aes.h"
+
+BOOL AES_Decrypt(const void *src, void *dst, uint32_t len)
+{
+	uint32_t *po = dst;
+	const uint32_t *pi = src;
+
+	if (len & 0xF)
+		return FALSE;
+
+	AES->FIFO_CLEAR = 1;
+	AES->FIFO_CLEAR = 0;
+	GLOBAL_CTRL->AES_BURST_TYPE = 0x1;						// Cannot be 0
+	while (len > 0) {
+		while (0 == GLOBAL_CTRL->AES_STATUS_b.IDLE);		// 0x41007010
+		udelay(2);
+		GLOBAL_CTRL->AES_TARGET_ADDR = (uint32_t)po;		// 0x41800000;
+		po += 4;
+		len -= 4 * sizeof(uint32_t);
+		while (0 == GLOBAL_CTRL->AES_STATUS_b.RD_EMPTY);	// 0x41007010
+		AES->FIFO = *pi++;
+		AES->FIFO = *pi++;
+		AES->FIFO = *pi++;
+		AES->FIFO = *pi++;
+	}
+	return TRUE;
+}

bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c

+/**
+	*****************************************************************************
+	* @file     cmem7_misc.c
+	*
+	* @brief    CMEM7 miscellaneous file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+
+#include "cmem7_misc.h"
+
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+  
+  /* Check the parameters */
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != FALSE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+    tmppriority = tmppriority << 0x04;
+        
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{ 
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  
+  if (!NewState)
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  } else {
+		SCB->SCR |= LowPowerMode;
+	}
+}
+
+void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn) {
+	int n;
+	
+	GLOBAL_CTRL->IBUSOFF = GLOBAL_CTRL->DBUSOFF = (from - to);
+	GLOBAL_CTRL->EXTADDR = to;
+	
+	// Delay several cycles 
+	for (n = 0; n < 100; n++);
+	GLOBAL_CTRL->ICACHE_b.EN = isIcacheOn;
+	for (n = 0; n < 100; n++);
+}
+
+void GLB_SetNmiIrqNum(uint32_t irq) {
+	GLOBAL_CTRL->NMI_SEL_b.NMI = irq;
+}
+
+void GLB_SelectSysClkSource(uint8_t source) {
+	switch (source) {
+	case SYS_CLK_SEL_DLL :
+		// M7's DLL clock should be fixed at PLL loation 2
+		// In constrast, it's C2R1.
+		// Wait DLL clock stable
+		while (PDLOCK->GCLK_b.C2R1D == 0) ;
+		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_DLL;
+		break;
+	case SYS_CLK_SEL_CRYSTAL :
+		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_CRYSTAL;
+		break;
+	case SYS_CLK_SEL_EXTERNAL :
+		// TODO, Add the condition that makes sure input
+		// external clock is stable
+		// For example :
+		//	PLL location 0
+		// 	while (PDLOCK->GCLK_b.C1R1P == 0) ;
+		// 	DLL location 0
+		// 	while (PDLOCK->GCLK_b.C1R1D == 0) ;
+		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_EXTERNAL;
+		break;
+	case SYS_CLK_SEL_OSC :
+		// Fall through
+	default :
+		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_OSC;
+		break;		
+	}
+}

bsp/CME_M7/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/CME_M7/drivers/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')