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北理工网安-杨杰-MMA_HCMA双模盲均衡FPGA实现

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北理工网安-杨杰-MMA_HCMA双模盲均衡FPGA实现

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2021/09/25 19:19:04
// Design Name:
// Module Name: balance_MMA_HCMA_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module balance_MMA_HCMA_top
#(
parameter switch_num = 4000
)
(
input clk ,
input rst ,
input signed[31:0] yi , //16clk
input signed[31:0] yq ,
input [0:0] sync , //先0后1
input [31:0] d ,
output reg signed[63:0] bi ,
output reg signed[63:0] bq ,
output reg [0:0] b_sync ,
output wire[32:0]point ,
output reg [32:0]er_out ,
output reg [32:0]ei_out
);
//同步时钟转脉冲,构造周期计数器，标记每周期16clk
reg [0:0]sync_d;
reg [3:0]clk_counter;
always@(posedge clk)begin
if(rst)begin
sync_d<=1'b0;
clk_counter<=4'b0;
end
else begin
sync_d<=sync;
if((sync == 1'b0)&&(sync_d == 1'b1))
clk_counter<=4'b0001;
else
clk_counter<=clk_counter+1'b1;
end
end
//M= 10
//18位全部作为小数位防止溢出，这样1+32
wire signed[32:0]yi_l,yq_l;
assign yi_l = yi;
assign yq_l = yq;
///////////////////////////////////////////////////////////////////////
//fir
//数据移位进入抽头滤波
reg signed[32:0]xr [9:0];
reg signed[32:0]xi [9:0];
always@(posedge clk)begin
if(rst)begin
xr[0]<=33'b0;
xr[1]<=33'b0;
xr[2]<=33'b0;
xr[3]<=33'b0;
xr[4]<=33'b0;
xr[5]<=33'b0;
xr[6]<=33'b0;
xr[7]<=33'b0;
xr[8]<=33'b0;
xr[9]<=33'b0;
xi[0]<=33'b0;
xi[1]<=33'b0;
xi[2]<=33'b0;
xi[3]<=33'b0;
xi[4]<=33'b0;
xi[5]<=33'b0;
xi[6]<=33'b0;
xi[7]<=33'b0;
xi[8]<=33'b0;
xi[9]<=33'b0;
end
else begin
if(clk_counter == 4'b0000)begin
xr[9]<= yi_l;
xr[8]<=xr[9];
xr[7]<=xr[8];
xr[6]<=xr[7];
xr[5]<=xr[6];
xr[4]<=xr[5];
xr[3]<=xr[4];
xr[2]<=xr[3];
xr[1]<=xr[2];
xr[0]<=xr[1];
xi[9]<=yq_l;
xi[8]<=xi[9];
xi[7]<=xi[8];
xi[6]<=xi[7];
xi[5]<=xi[6];
xi[4]<=xi[5];
xi[3]<=xi[4];
xi[2]<=xi[3];
xi[1]<=xi[2];
xi[0]<=xi[1];
end
end
end
//mux ,
reg signed[32:0]x_mix[9:0];
always@(posedge clk)begin
if(rst)begin
x_mix[0]<=33'b0;
x_mix[1]<=33'b0;
x_mix[2]<=33'b0;
x_mix[3]<=33'b0;
x_mix[4]<=33'b0;
x_mix[5]<=33'b0;
x_mix[6]<=33'b0;
x_mix[7]<=33'b0;
x_mix[8]<=33'b0;
x_mix[9]<=33'b0;
end
else begin
case(clk_counter)
4'b0001: begin
x_mix[0]<= xr[0];
x_mix[1]<= xr[1];
x_mix[2]<= xr[2];
x_mix[3]<= xr[3];
x_mix[4]<= xr[4];
x_mix[5]<= xr[5];
x_mix[6]<= xr[6];
x_mix[7]<= xr[7];
x_mix[8]<= xr[8];
x_mix[9]<= xr[9];
end
4'b0010: begin
x_mix[0]<= xr[0];
x_mix[1]<= xr[1];
x_mix[2]<= xr[2];
x_mix[3]<= xr[3];
x_mix[4]<= xr[4];
x_mix[5]<= xr[5];
x_mix[6]<= xr[6];
x_mix[7]<= xr[7];
x_mix[8]<= xr[8];
x_mix[9]<= xr[9];
end
4'b0011: begin
x_mix[0]<=-xi[0];
x_mix[1]<=-xi[1];
x_mix[2]<=-xi[2];
x_mix[3]<=-xi[3];
x_mix[4]<=-xi[4];
x_mix[5]<=-xi[5];
x_mix[6]<=-xi[6];
x_mix[7]<=-xi[7];
x_mix[8]<=-xi[8];
x_mix[9]<=-xi[9];
end
4'b0100: begin
x_mix[0]<=xi[0];
x_mix[1]<=xi[1];
x_mix[2]<=xi[2];
x_mix[3]<=xi[3];
x_mix[4]<=xi[4];
x_mix[5]<=xi[5];
x_mix[6]<=xi[6];
x_mix[7]<=xi[7];
x_mix[8]<=xi[8];
x_mix[9]<=xi[9];
end
default: begin
x_mix[9]<=19'b0;
x_mix[8]<=19'b0;
x_mix[7]<=19'b0;
x_mix[6]<=19'b0;
x_mix[5]<=19'b0;
x_mix[4]<=19'b0;
x_mix[3]<=19'b0;
x_mix[2]<=19'b0;
x_mix[1]<=19'b0;
x_mix[0]<=19'b0;
end
endcase
end
end
// y = (wr*xr - wi*xi) + i * (wr*xi + xr*wi)
//0 1 2 3 4 5 6 7 8 9 A B C D E F clk_counter
//- r r r r r r r r r r r r r r r xr
//- i i i i i i i i i i i i i i i xi
//- - r r -i i - - - - - - - - - - x_mix
//- - r i i r - - - - - - - - - - w_mix
//- - - 2 3 4 5 xw_mix_long
//- - - 2 3 4 5 xw_mix_sum
//- - - - - - r r r r r r r r r r dsr
//- - - - - - - i i i i i i i i i dsi
//ds(i) = w*conj(y');
wire signed[65:0]xw_mix_long[9:0]; // 2+64
//1+32 * 1+2+30 = //1+3+62
tap_times_x10 u_tap_times_x10_xw( // 相对x_mix一个clk延时
.clk(clk ),
.rst(rst ),
.a0(x_mix[9]),
.a1(x_mix[8]),
.a2(x_mix[7]),
.a3(x_mix[6]),
.a4(x_mix[5]),
.a5(x_mix[4]),
.a6(x_mix[3]),
.a7(x_mix[2]),
.a8(x_mix[1]),
.a9(x_mix[0]),
.b0(w_mix[0]),
.b1(w_mix[1]),
.b2(w_mix[2]),
.b3(w_mix[3]),
.b4(w_mix[4]),
.b5(w_mix[5]),
.b6(w_mix[6]),
.b7(w_mix[7]),
.b8(w_mix[8]),
.b9(w_mix[9]),
.p0(xw_mix_long[0]),
.p1(xw_mix_long[1]),
.p2(xw_mix_long[2]),
.p3(xw_mix_long[3]),
.p4(xw_mix_long[4]),
.p5(xw_mix_long[5]),
.p6(xw_mix_long[6]),
.p7(xw_mix_long[7]),
.p8(xw_mix_long[8]),
.p9(xw_mix_long[9])
);
//求和
wire signed[65:0]xw_mix_sum; //6+64
assign xw_mix_sum = (rst)? 66'b0:xw_mix_long[0]+xw_mix_long[1]+xw_mix_long[2]+xw_mix_long[3]+xw_mix_long[4]+xw_mix_long[5]+xw_mix_long[6]+xw_mix_long[7]+xw_mix_long[8]+xw_mix_long[9]; //10个数相加补4位
reg signed[65:0]dsr_long, dsi_long;
always@(posedge clk)begin
if(rst)begin
dsr_long<=66'b0;
dsi_long<=66'b0;
end
else begin
case(clk_counter)
4'b0011:dsr_long<=xw_mix_sum;
4'b0100:dsi_long<=xw_mix_sum;
4'b0101:dsr_long<=dsr_long+xw_mix_sum;
4'b0110:dsi_long<=dsi_long+xw_mix_sum;
endcase
end
end
wire signed [32:0]dsr,dsi;
assign dsr = dsr_long[62:30];
assign dsi = dsi_long[62:30];
//1+3+62
//1+32
always@(posedge clk)begin
if(rst)begin
bi<=64'b0;
bq<=64'b0;
b_sync<=1'b0;
end
else begin
if(clk_counter == 4'b0111)begin
bi<=dsr_long[63:0];
bq<=dsi_long[63:0];
b_sync<=1'b1;
end
else
b_sync<=1'b0;
end
end
/////////////////////////////////////////////////////////////////
//ei
//计数器，根据计数器切换MMA和HCMA状态
reg [63:0]mode_counter;
always@(posedge clk)begin
if(rst)
mode_counter<=10'b0;
else if(clk_counter == 4'b0001)begin
if(mode_counter < switch_num)
mode_counter<=mode_counter+1'b1;
end
end
//模式控制
wire [0:0]ma_mode;
assign ma_mode = (mode_counter == switch_num)? 1'b1:1'b0; //HCMA:MMA
//0 1 2 3 4 5 6 7 8 9 A B C D E F clk_counter
//- - m m m m m m m m m m m m m m ma_mode
//- - - - - - r r r r r r r r r r dsr
//- - - - - - - i i i i i i i i i dsi
//- - - - - - - r r r r r r r r r dsr2
//- - - - - - - - i i i i i i i i dsi2
//获取ds^2,
wire [65:0]dsr2,dsi2;
//1+1+64
mult33_33 u_ds_times_dsr2 (
.CLK(clk),
.A(dsr),
.B(dsr),
.P(dsr2)
);
mult33_33 u_ds_times_dsi2 (
.CLK(clk),
.A(dsi),
.B(dsi),
.P(dsi2)
);
wire [65:0]d2; //d2 = d^2
mult33_33 u_d_d(
.CLK(clk),
.A({1'b0,d}),
.B({1'b0,d}),
.P(d2)
);
wire signed[32:0]er1,ei1,er2,ei2,er,ei,e_mix1,e_mix2,e_mix;
//计算误差 延时？
ei_MMA u_ei_MMA(
.clk (clk ),
.rst (rst||(ma_mode) ),
.clk_counter (clk_counter ),
.dsr (dsr ),
.dsi (dsi ),
.dsr2 (dsr2 ),
.dsi2 (dsi2 ),
.d (d ),
.d2 (d2 ),
.er (er1 ),
.ei (ei1 ),
.e_mix (e_mix1 )
);
ei_HCMA u_ei_HCMA(
.clk (clk ),
.rst (rst||(~ma_mode) ),
.clk_counter (clk_counter ),
.dsr (dsr ),
.dsi (dsi ),
.dsr2 (dsr2 ),
.dsi2 (dsi2 ),
.d (d ),
.d2 (d2 ),
.er (er2 ),
.ei (ei2 ),
.e_mix (e_mix2 )
);
//D
assign er = (ma_mode)? er2:er1;
assign ei = (ma_mode)? ei2:ei1;
assign e_mix = (ma_mode)? e_mix2:e_mix1;
/////////////////////////////////////////////////////////////////
//wn
//0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 clk_counter
//- - - - - - - - - - x x d d d d er
//- - - - - - - - - - - x x d d d ei
//- - - - - - - - - - - - r r-i i x_mix_d
//- - - - - - - - - - - - r i i r e_mix
//- - - - - - - - - - - - - c d e f ex_long
//- - - - - - - - - - - - x x x x r r exr
//- - - - - - - - - - - - - x x x x i exi
// - r r r wr
// - - i i wi
// - - r r -i i - - - - - - - - - - x_mix
// - - r i i r - - - - - - - - - - w_mix
//0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 clk_counter
// w=w-uc*e(i)*conj(y);
//建议延迟x，重新组x_mix_d
reg signed[32:0]x_mix_d[9:0];
always@(posedge clk)begin
if(rst)begin
x_mix_d[0]<=33'b0;
x_mix_d[1]<=33'b0;
x_mix_d[2]<=33'b0;
x_mix_d[3]<=33'b0;
x_mix_d[4]<=33'b0;
x_mix_d[5]<=33'b0;
x_mix_d[6]<=33'b0;
x_mix_d[7]<=33'b0;
x_mix_d[8]<=33'b0;
x_mix_d[9]<=33'b0;
end
else begin
case(clk_counter)
4'b1011:begin
x_mix_d[0]<=xr[0];
x_mix_d[1]<=xr[1];
x_mix_d[2]<=xr[2];
x_mix_d[3]<=xr[3];
x_mix_d[4]<=xr[4];
x_mix_d[5]<=xr[5];
x_mix_d[6]<=xr[6];
x_mix_d[7]<=xr[7];
x_mix_d[8]<=xr[8];
x_mix_d[9]<=xr[9];
end
4'b1100:begin
x_mix_d[0]<=xr[0];
x_mix_d[1]<=xr[1];
x_mix_d[2]<=xr[2];
x_mix_d[3]<=xr[3];
x_mix_d[4]<=xr[4];
x_mix_d[5]<=xr[5];
x_mix_d[6]<=xr[6];
x_mix_d[7]<=xr[7];
x_mix_d[8]<=xr[8];
x_mix_d[9]<=xr[9];
end
4'b1101:begin
x_mix_d[0]<=xi[0];
x_mix_d[1]<=xi[1];
x_mix_d[2]<=xi[2];
x_mix_d[3]<=xi[3];
x_mix_d[4]<=xi[4];
x_mix_d[5]<=xi[5];
x_mix_d[6]<=xi[6];
x_mix_d[7]<=xi[7];
x_mix_d[8]<=xi[8];
x_mix_d[9]<=xi[9];
end
4'b1110:begin
x_mix_d[0]<=-xi[0];
x_mix_d[1]<=-xi[1];
x_mix_d[2]<=-xi[2];
x_mix_d[3]<=-xi[3];
x_mix_d[4]<=-xi[4];
x_mix_d[5]<=-xi[5];
x_mix_d[6]<=-xi[6];
x_mix_d[7]<=-xi[7];
x_mix_d[8]<=-xi[8];
x_mix_d[9]<=-xi[9];
end
default: begin
x_mix_d[0]<=19'b0;
x_mix_d[1]<=19'b0;
x_mix_d[2]<=19'b0;
x_mix_d[3]<=19'b0;
x_mix_d[4]<=19'b0;
x_mix_d[5]<=19'b0;
x_mix_d[6]<=19'b0;
x_mix_d[7]<=19'b0;
x_mix_d[8]<=19'b0;
x_mix_d[9]<=19'b0;
end
endcase
end
end
wire signed[65:0]ex_long[9:0];
tap_times_x10 u_tap_times_x10_ex(
.clk(clk ),
.rst(rst ),
.a0(x_mix_d[9]),
.a1(x_mix_d[8]),
.a2(x_mix_d[7]),
.a3(x_mix_d[6]),
.a4(x_mix_d[5]),
.a5(x_mix_d[4]),
.a6(x_mix_d[3]),
.a7(x_mix_d[2]),
.a8(x_mix_d[1]),
.a9(x_mix_d[0]),
.b0(e_mix),
.b1(e_mix),
.b2(e_mix),
.b3(e_mix),
.b4(e_mix),
.b5(e_mix),
.b6(e_mix),
.b7(e_mix),
.b8(e_mix),
.b9(e_mix),
.p0(ex_long[0]),
.p1(ex_long[1]),
.p2(ex_long[2]),
.p3(ex_long[3]),
.p4(ex_long[4]),
.p5(ex_long[5]),
.p6(ex_long[6]),
.p7(ex_long[7]),
.p8(ex_long[8]),
.p9(ex_long[9])
);
//但要是只需要读一位或者多个位，就要麻烦一点，因为Verilog不允许读/写一个位。这时，就需要使用一个变量转换一下：（wolf点评：菜鸟易犯的错误，注意！）
reg signed[32:0]wr[9:0];
reg signed[32:0]wi[9:0];
reg signed[32:0]w_mix[9:0];
reg signed[65:0]exr[9:0];
reg signed[65:0]exi[9:0];
wire signed[65:0]exr0;
wire signed[65:0]exr1;
wire signed[65:0]exr2;
wire signed[65:0]exr3;
wire signed[65:0]exr4;
wire signed[65:0]exr5;
wire signed[65:0]exr6;
wire signed[65:0]exr7;
wire signed[65:0]exr8;
wire signed[65:0]exr9;
wire signed[65:0]exi0;
wire signed[65:0]exi1;
wire signed[65:0]exi2;
wire signed[65:0]exi3;
wire signed[65:0]exi4;
wire signed[65:0]exi5;
wire signed[65:0]exi6;
wire signed[65:0]exi7;
wire signed[65:0]exi8;
wire signed[65:0]exi9;
wire signed[32:0]exr0_cut;
wire signed[32:0]exr1_cut;
wire signed[32:0]exr2_cut;
wire signed[32:0]exr3_cut;
wire signed[32:0]exr4_cut;
wire signed[32:0]exr5_cut;
wire signed[32:0]exr6_cut;
wire signed[32:0]exr7_cut;
wire signed[32:0]exr8_cut;
wire signed[32:0]exr9_cut;
wire signed[32:0]exi0_cut;
wire signed[32:0]exi1_cut;
wire signed[32:0]exi2_cut;
wire signed[32:0]exi3_cut;
wire signed[32:0]exi4_cut;
wire signed[32:0]exi5_cut;
wire signed[32:0]exi6_cut;
wire signed[32:0]exi7_cut;
wire signed[32:0]exi8_cut;
wire signed[32:0]exi9_cut;
assign exr0 = exr[0];
assign exr1 = exr[1];
assign exr2 = exr[2];
assign exr3 = exr[3];
assign exr4 = exr[4];
assign exr5 = exr[5];
assign exr6 = exr[6];
assign exr7 = exr[7];
assign exr8 = exr[8];
assign exr9 = exr[9];
assign exi0 = exi[0];
assign exi1 = exi[1];
assign exi2 = exi[2];
assign exi3 = exi[3];
assign exi4 = exi[4];
assign exi5 = exi[5];
assign exi6 = exi[6];
assign exi7 = exi[7];
assign exi8 = exi[8];
assign exi9 = exi[9];
//hcma mma
//3+30 //2+64 *3*4
assign exr0_cut= (ma_mode)? exr0[63:31]:exr0[62:30];
assign exr1_cut= (ma_mode)? exr1[63:31]:exr1[62:30];
assign exr2_cut= (ma_mode)? exr2[63:31]:exr2[62:30];
assign exr3_cut= (ma_mode)? exr3[63:31]:exr3[62:30];
assign exr4_cut= (ma_mode)? exr4[63:31]:exr4[62:30];
assign exr5_cut= (ma_mode)? exr5[63:31]:exr5[62:30];
assign exr6_cut= (ma_mode)? exr6[63:31]:exr6[62:30];
assign exr7_cut= (ma_mode)? exr7[63:31]:exr7[62:30];
assign exr8_cut= (ma_mode)? exr8[63:31]:exr8[62:30];
assign exr9_cut= (ma_mode)? exr9[63:31]:exr9[62:30];
assign exi0_cut= (ma_mode)? exi0[63:31]:exi0[62:30];
assign exi1_cut= (ma_mode)? exi1[63:31]:exi1[62:30];
assign exi2_cut= (ma_mode)? exi2[63:31]:exi2[62:30];
assign exi3_cut= (ma_mode)? exi3[63:31]:exi3[62:30];
assign exi4_cut= (ma_mode)? exi4[63:31]:exi4[62:30];
assign exi5_cut= (ma_mode)? exi5[63:31]:exi5[62:30];
assign exi6_cut= (ma_mode)? exi6[63:31]:exi6[62:30];
assign exi7_cut= (ma_mode)? exi7[63:31]:exi7[62:30];
assign exi8_cut= (ma_mode)? exi8[63:31]:exi8[62:30];
assign exi9_cut= (ma_mode)? exi9[63:31]:exi9[62:30];
always@(posedge clk)begin
if(rst)begin
exr[0]<=66'b0;
exr[1]<=66'b0;
exr[2]<=66'b0;
exr[3]<=66'b0;
exr[4]<=66'b0;
exr[5]<=66'b0;
exr[6]<=66'b0;
exr[7]<=66'b0;
exr[8]<=66'b0;
exr[9]<=66'b0;
exi[0]<=66'b0;
exi[1]<=66'b0;
exi[2]<=66'b0;
exi[3]<=66'b0;
exi[4]<=66'b0;
exi[5]<=66'b0;
exi[6]<=66'b0;
exi[7]<=66'b0;
exi[8]<=66'b0;
exi[9]<=66'b0;
w_mix[0]<=33'd0;//
w_mix[1]<=33'b0;
w_mix[2]<=33'b0;
w_mix[3]<=33'b0;
w_mix[4]<=33'b0;
w_mix[5]<=33'b0;
w_mix[6]<=33'b0;
w_mix[7]<=33'b0;
w_mix[8]<=33'b0;
w_mix[9]<=33'b0;
wr[0]<=33'b0;
wr[1]<=33'b0;
wr[2]<=33'b0;
wr[3]<=33'b001000000000000000000000000000000;
wr[4]<=33'b0;
wr[5]<=33'b0;
wr[6]<=33'b0;
wr[7]<=33'b0;
wr[8]<=33'b0;
wr[9]<=33'b0;
wi[0]<=33'b0;
wi[1]<=33'b0;
wi[2]<=33'b0;
wi[3]<=33'b0;
wi[4]<=33'b0;
wi[5]<=33'b0;
wi[6]<=33'b0;
wi[7]<=33'b0;
wi[8]<=33'b0;
wi[9]<=33'b0;
end
else begin
case(clk_counter)
4'b1101:begin
//exr[9:0] < = ex_long[9:0];
exr[0]<=ex_long[0];
exr[1]<=ex_long[1];
exr[2]<=ex_long[2];
exr[3]<=ex_long[3];
exr[4]<=ex_long[4];
exr[5]<=ex_long[5];
exr[6]<=ex_long[6];
exr[7]<=ex_long[7];
exr[8]<=ex_long[8];
exr[9]<=ex_long[9];
end
4'b1110:begin
//exi[9:0] < = ex_long[9:0];
exi[0]<=ex_long[0];
exi[1]<=ex_long[1];
exi[2]<=ex_long[2];
exi[3]<=ex_long[3];
exi[4]<=ex_long[4];
exi[5]<=ex_long[5];
exi[6]<=ex_long[6];
exi[7]<=ex_long[7];
exi[8]<=ex_long[8];
exi[9]<=ex_long[9];
end
4'b1111:begin
//exr[9:0] < =exr[9:0] + ex_long[9:0];
exr[0]<=exr[0]+ex_long[0];
exr[1]<=exr[1]+ex_long[1];
exr[2]<=exr[2]+ex_long[2];
exr[3]<=exr[3]+ex_long[3];
exr[4]<=exr[4]+ex_long[4];
exr[5]<=exr[5]+ex_long[5];
exr[6]<=exr[6]+ex_long[6];
exr[7]<=exr[7]+ex_long[7];
exr[8]<=exr[8]+ex_long[8];
exr[9]<=exr[9]+ex_long[9];
er_out<=er;
ei_out<=ei;
end
4'b0000:begin
//exi[9:0] < =exi[9:0] + ex_long[9:0];
exi[0]<=exi[0]+ex_long[0];
exi[1]<=exi[1]+ex_long[1];
exi[2]<=exi[2]+ex_long[2];
exi[3]<=exi[3]+ex_long[3];
exi[4]<=exi[4]+ex_long[4];
exi[5]<=exi[5]+ex_long[5];
exi[6]<=exi[6]+ex_long[6];
exi[7]<=exi[7]+ex_long[7];
exi[8]<=exi[8]+ex_long[8];
exi[9]<=exi[9]+ex_long[9];
//wr[9:0] <= wr[9:0] - [mu1]exr[9:0];
//1+2+30 //1+32
wr[0]<=wr[0]-exr0_cut;
wr[1]<=wr[1]-exr1_cut;
wr[2]<=wr[2]-exr2_cut;
wr[3]<=wr[3]-exr3_cut;
wr[4]<=wr[4]-exr4_cut;
wr[5]<=wr[5]-exr5_cut;
wr[6]<=wr[6]-exr6_cut;
wr[7]<=wr[7]-exr7_cut;
wr[8]<=wr[8]-exr8_cut;
wr[9]<=wr[9]-exr9_cut;
end
4'b0001:begin
//wi[9:0] <= wi[9:0] - [mu1]exi[9:0];
wi[0]<=wi[0]-exi0_cut;
wi[1]<=wi[1]-exi1_cut;
wi[2]<=wi[2]-exi2_cut;
wi[3]<=wi[3]-exi3_cut;
wi[4]<=wi[4]-exi4_cut;
wi[5]<=wi[5]-exi5_cut;
wi[6]<=wi[6]-exi6_cut;
wi[7]<=wi[7]-exi7_cut;
wi[8]<=wi[8]-exi8_cut;
wi[9]<=wi[9]-exi9_cut;
//w_mix[9:0] <= wr[9:0];
//w_mix<=wr;
w_mix[0]<=wr[0];
w_mix[1]<=wr[1];
w_mix[2]<=wr[2];
w_mix[3]<=wr[3];
w_mix[4]<=wr[4];
w_mix[5]<=wr[5];
w_mix[6]<=wr[6];
w_mix[7]<=wr[7];
w_mix[8]<=wr[8];
w_mix[9]<=wr[9];
end
4'b0010:begin
//w_mix[9:0] <= wi[9:0];
w_mix[0]<=wi[0];
w_mix[1]<=wi[1];
w_mix[2]<=wi[2];
w_mix[3]<=wi[3];
w_mix[4]<=wi[4];
w_mix[5]<=wi[5];
w_mix[6]<=wi[6];
w_mix[7]<=wi[7];
w_mix[8]<=wi[8];
w_mix[9]<=wi[9];
end
4'b0011:begin
//w_mix[9:0] <= wi[9:0];
w_mix[0]<=wi[0];
w_mix[1]<=wi[1];
w_mix[2]<=wi[2];
w_mix[3]<=wi[3];
w_mix[4]<=wi[4];
w_mix[5]<=wi[5];
w_mix[6]<=wi[6];
w_mix[7]<=wi[7];
w_mix[8]<=wi[8];
w_mix[9]<=wi[9];
end
4'b0100:begin
//w_mix[9:0] <= wr[9:0];
w_mix[0]<=wr[0];
w_mix[1]<=wr[1];
w_mix[2]<=wr[2];
w_mix[3]<=wr[3];
w_mix[4]<=wr[4];
w_mix[5]<=wr[5];
w_mix[6]<=wr[6];
w_mix[7]<=wr[7];
w_mix[8]<=wr[8];
w_mix[9]<=wr[9];
end
endcase
end
end
assign point = wr[0];
endmodule
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