* Update Verilog courses

Renamed `SystemVerilog` section to `Verilog / VHDL / SystemVerilog` because they are 3 different hardware description languages. Grouped them together so that all the Verilog resources can be found in one spot. Added new course as suggested in #2151

* Reorder Verilog courses by alphabetical order

* Add new course suggested by @mramdas

* Reorder Verilog courses