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f2a66e12
编写于
12月 30, 2022
作者:
嵌入式浪子
提交者:
mysterywolf
1月 02, 2023
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电子邮件补丁
差异文件
[libcpu][riscv]移除cv32e40p中部分文件,采用common中的文件
上级
e97ba95f
变更
6
隐藏空白更改
内联
并排
Showing
6 changed file
with
2 addition
and
340 deletion
+2
-340
bsp/core-v-mcu/core-v-cv32e40p/rtconfig.py
bsp/core-v-mcu/core-v-cv32e40p/rtconfig.py
+1
-1
libcpu/risc-v/SConscript
libcpu/risc-v/SConscript
+0
-2
libcpu/risc-v/common/SConscript
libcpu/risc-v/common/SConscript
+1
-1
libcpu/risc-v/cv32e40p/context_gcc.S
libcpu/risc-v/cv32e40p/context_gcc.S
+0
-181
libcpu/risc-v/cv32e40p/cpuport.c
libcpu/risc-v/cv32e40p/cpuport.c
+0
-130
libcpu/risc-v/cv32e40p/cpuport.h
libcpu/risc-v/cv32e40p/cpuport.h
+0
-25
未找到文件。
bsp/core-v-mcu/core-v-cv32e40p/rtconfig.py
浏览文件 @
f2a66e12
...
...
@@ -49,7 +49,7 @@ if PLATFORM == 'gcc':
LFLAGS
=
DEVICE
LFLAGS
+=
' -Wl,--gc-sections,-cref,-Map='
+
MAP_FILE
LFLAGS
+=
' -T '
+
LINK_FILE
AFLAGS
+=
' -I. '
CPATH
=
''
LPATH
=
''
...
...
libcpu/risc-v/SConscript
浏览文件 @
f2a66e12
...
...
@@ -22,8 +22,6 @@ elif rtconfig.CPU == "ch32" :
group
=
group
elif
rtconfig
.
CPU
==
"hpmicro"
:
group
=
group
elif
rtconfig
.
CPU
==
"cv32e40p"
:
group
=
group
else
:
group
=
group
+
SConscript
(
os
.
path
.
join
(
'common'
,
'SConscript'
))
...
...
libcpu/risc-v/common/SConscript
浏览文件 @
f2a66e12
...
...
@@ -5,7 +5,7 @@ from building import *
cwd
=
GetCurrentDir
()
src
=
Glob
(
'*.c'
)
+
Glob
(
'*.cpp'
)
+
Glob
(
'*_gcc.S'
)
CPPPATH
=
[
cwd
]
ASFLAGS
=
'
'
ASFLAGS
=
'
-I '
+
cwd
group
=
DefineGroup
(
'CPU'
,
src
,
depend
=
[
''
],
CPPPATH
=
CPPPATH
,
ASFLAGS
=
ASFLAGS
)
...
...
libcpu/risc-v/cv32e40p/context_gcc.S
已删除
100644 → 0
浏览文件 @
e97ba95f
/*
*
Copyright
(
c
)
2006
-
2018
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
*
Change
Logs
:
*
Date
Author
Notes
*
2018
/
10
/
28
Bernard
The
unify
RISC
-
V
porting
implementation
*
2018
/
12
/
27
Jesven
Add
SMP
support
*/
#include "cpuport.h"
#ifdef RT_USING_SMP
#define rt_hw_interrupt_disable rt_hw_local_irq_disable
#define rt_hw_interrupt_enable rt_hw_local_irq_enable
#endif
/*
*
rt_base_t
rt_hw_interrupt_disable
(
void
)
;
*/
.
globl
rt_hw_interrupt_disable
rt_hw_interrupt_disable
:
csrrci
a0
,
mstatus
,
8
ret
/*
*
void
rt_hw_interrupt_enable
(
rt_base_t
level
)
;
*/
.
globl
rt_hw_interrupt_enable
rt_hw_interrupt_enable
:
csrw
mstatus
,
a0
ret
/*
*
#
ifdef
RT_USING_SMP
*
void
rt_hw_context_switch_to
(
rt_ubase_t
to
,
stuct
rt_thread
*
to_thread
)
;
*
#
else
*
void
rt_hw_context_switch_to
(
rt_ubase_t
to
)
;
*
#
endif
*
a0
-->
to
*
a1
-->
to_thread
*/
.
globl
rt_hw_context_switch_to
rt_hw_context_switch_to
:
LOAD
sp
,
(
a0
)
LOAD
a0
,
2
*
REGBYTES
(
sp
)
csrw
mstatus
,
a0
j
rt_hw_context_switch_exit
/*
*
#
ifdef
RT_USING_SMP
*
void
rt_hw_context_switch
(
rt_ubase_t
from
,
rt_ubase_t
to
,
struct
rt_thread
*
to_thread
)
;
*
#
else
*
void
rt_hw_context_switch
(
rt_ubase_t
from
,
rt_ubase_t
to
)
;
*
#
endif
*
*
a0
-->
from
*
a1
-->
to
*
a2
-->
to_thread
*/
.
globl
rt_hw_context_switch
rt_hw_context_switch
:
/
*
saved
from
thread
context
*
x1
/
ra
->
sp
(
0
)
*
x1
/
ra
->
sp
(
1
)
*
mstatus
.
mie
->
sp
(
2
)
*
x
(
i
)
->
sp
(
i
-
4
)
*/
addi
sp
,
sp
,
-
32
*
REGBYTES
STORE
sp
,
(
a0
)
STORE
x1
,
0
*
REGBYTES
(
sp
)
STORE
x1
,
1
*
REGBYTES
(
sp
)
csrr
a0
,
mstatus
andi
a0
,
a0
,
8
beqz
a0
,
save_mpie
li
a0
,
0x80
save_mpie
:
STORE
a0
,
2
*
REGBYTES
(
sp
)
STORE
x4
,
4
*
REGBYTES
(
sp
)
STORE
x5
,
5
*
REGBYTES
(
sp
)
STORE
x6
,
6
*
REGBYTES
(
sp
)
STORE
x7
,
7
*
REGBYTES
(
sp
)
STORE
x8
,
8
*
REGBYTES
(
sp
)
STORE
x9
,
9
*
REGBYTES
(
sp
)
STORE
x10
,
10
*
REGBYTES
(
sp
)
STORE
x11
,
11
*
REGBYTES
(
sp
)
STORE
x12
,
12
*
REGBYTES
(
sp
)
STORE
x13
,
13
*
REGBYTES
(
sp
)
STORE
x14
,
14
*
REGBYTES
(
sp
)
STORE
x15
,
15
*
REGBYTES
(
sp
)
STORE
x16
,
16
*
REGBYTES
(
sp
)
STORE
x17
,
17
*
REGBYTES
(
sp
)
STORE
x18
,
18
*
REGBYTES
(
sp
)
STORE
x19
,
19
*
REGBYTES
(
sp
)
STORE
x20
,
20
*
REGBYTES
(
sp
)
STORE
x21
,
21
*
REGBYTES
(
sp
)
STORE
x22
,
22
*
REGBYTES
(
sp
)
STORE
x23
,
23
*
REGBYTES
(
sp
)
STORE
x24
,
24
*
REGBYTES
(
sp
)
STORE
x25
,
25
*
REGBYTES
(
sp
)
STORE
x26
,
26
*
REGBYTES
(
sp
)
STORE
x27
,
27
*
REGBYTES
(
sp
)
STORE
x28
,
28
*
REGBYTES
(
sp
)
STORE
x29
,
29
*
REGBYTES
(
sp
)
STORE
x30
,
30
*
REGBYTES
(
sp
)
STORE
x31
,
31
*
REGBYTES
(
sp
)
/
*
restore
to
thread
context
*
sp
(
0
)
->
epc
;
*
sp
(
1
)
->
ra
;
*
sp
(
i
)
->
x
(
i
+
2
)
*/
LOAD
sp
,
(
a1
)
j
rt_hw_context_switch_exit
.
global
rt_hw_context_switch_exit
rt_hw_context_switch_exit
:
#ifdef RT_USING_SMP
#ifdef RT_USING_SIGNALS
mv
a0
,
sp
csrr
t0
,
mhartid
/
*
switch
interrupt
stack
of
current
cpu
*/
la
sp
,
__stack_start__
addi
t1
,
t0
,
1
li
t2
,
__STACKSIZE__
mul
t1
,
t1
,
t2
add
sp
,
sp
,
t1
/*
sp
=
(
cpuid
+
1
)
*
__STACKSIZE__
+
__stack_start__
*/
call
rt_signal_check
mv
sp
,
a0
#endif
#endif
/
*
resw
ra
to
mepc
*/
LOAD
a0
,
0
*
REGBYTES
(
sp
)
csrw
mepc
,
a0
LOAD
x1
,
1
*
REGBYTES
(
sp
)
li
t0
,
0x00001800
csrs
mstatus
,
t0
LOAD
a0
,
2
*
REGBYTES
(
sp
)
csrs
mstatus
,
a0
LOAD
x4
,
4
*
REGBYTES
(
sp
)
LOAD
x5
,
5
*
REGBYTES
(
sp
)
LOAD
x6
,
6
*
REGBYTES
(
sp
)
LOAD
x7
,
7
*
REGBYTES
(
sp
)
LOAD
x8
,
8
*
REGBYTES
(
sp
)
LOAD
x9
,
9
*
REGBYTES
(
sp
)
LOAD
x10
,
10
*
REGBYTES
(
sp
)
LOAD
x11
,
11
*
REGBYTES
(
sp
)
LOAD
x12
,
12
*
REGBYTES
(
sp
)
LOAD
x13
,
13
*
REGBYTES
(
sp
)
LOAD
x14
,
14
*
REGBYTES
(
sp
)
LOAD
x15
,
15
*
REGBYTES
(
sp
)
LOAD
x16
,
16
*
REGBYTES
(
sp
)
LOAD
x17
,
17
*
REGBYTES
(
sp
)
LOAD
x18
,
18
*
REGBYTES
(
sp
)
LOAD
x19
,
19
*
REGBYTES
(
sp
)
LOAD
x20
,
20
*
REGBYTES
(
sp
)
LOAD
x21
,
21
*
REGBYTES
(
sp
)
LOAD
x22
,
22
*
REGBYTES
(
sp
)
LOAD
x23
,
23
*
REGBYTES
(
sp
)
LOAD
x24
,
24
*
REGBYTES
(
sp
)
LOAD
x25
,
25
*
REGBYTES
(
sp
)
LOAD
x26
,
26
*
REGBYTES
(
sp
)
LOAD
x27
,
27
*
REGBYTES
(
sp
)
LOAD
x28
,
28
*
REGBYTES
(
sp
)
LOAD
x29
,
29
*
REGBYTES
(
sp
)
LOAD
x30
,
30
*
REGBYTES
(
sp
)
LOAD
x31
,
31
*
REGBYTES
(
sp
)
addi
sp
,
sp
,
32
*
REGBYTES
mret
libcpu/risc-v/cv32e40p/cpuport.c
已删除
100644 → 0
浏览文件 @
e97ba95f
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/28 Bernard The unify RISC-V porting code.
* 2022/12/08 WangShun Change the parameters of rt_hw_context_switch_interrupt
*/
#include <rthw.h>
#include <rtthread.h>
#include "cpuport.h"
#ifndef RT_USING_SMP
volatile
rt_ubase_t
rt_interrupt_from_thread
=
0
;
volatile
rt_ubase_t
rt_interrupt_to_thread
=
0
;
volatile
rt_uint32_t
rt_thread_switch_interrupt_flag
=
0
;
#endif
struct
rt_hw_stack_frame
{
rt_ubase_t
epc
;
/* epc - epc - program counter */
rt_ubase_t
ra
;
/* x1 - ra - return address for jumps */
rt_ubase_t
mstatus
;
/* - machine status register */
rt_ubase_t
gp
;
/* x3 - gp - global pointer */
rt_ubase_t
tp
;
/* x4 - tp - thread pointer */
rt_ubase_t
t0
;
/* x5 - t0 - temporary register 0 */
rt_ubase_t
t1
;
/* x6 - t1 - temporary register 1 */
rt_ubase_t
t2
;
/* x7 - t2 - temporary register 2 */
rt_ubase_t
s0_fp
;
/* x8 - s0/fp - saved register 0 or frame pointer */
rt_ubase_t
s1
;
/* x9 - s1 - saved register 1 */
rt_ubase_t
a0
;
/* x10 - a0 - return value or function argument 0 */
rt_ubase_t
a1
;
/* x11 - a1 - return value or function argument 1 */
rt_ubase_t
a2
;
/* x12 - a2 - function argument 2 */
rt_ubase_t
a3
;
/* x13 - a3 - function argument 3 */
rt_ubase_t
a4
;
/* x14 - a4 - function argument 4 */
rt_ubase_t
a5
;
/* x15 - a5 - function argument 5 */
rt_ubase_t
a6
;
/* x16 - a6 - function argument 6 */
rt_ubase_t
a7
;
/* x17 - s7 - function argument 7 */
rt_ubase_t
s2
;
/* x18 - s2 - saved register 2 */
rt_ubase_t
s3
;
/* x19 - s3 - saved register 3 */
rt_ubase_t
s4
;
/* x20 - s4 - saved register 4 */
rt_ubase_t
s5
;
/* x21 - s5 - saved register 5 */
rt_ubase_t
s6
;
/* x22 - s6 - saved register 6 */
rt_ubase_t
s7
;
/* x23 - s7 - saved register 7 */
rt_ubase_t
s8
;
/* x24 - s8 - saved register 8 */
rt_ubase_t
s9
;
/* x25 - s9 - saved register 9 */
rt_ubase_t
s10
;
/* x26 - s10 - saved register 10 */
rt_ubase_t
s11
;
/* x27 - s11 - saved register 11 */
rt_ubase_t
t3
;
/* x28 - t3 - temporary register 3 */
rt_ubase_t
t4
;
/* x29 - t4 - temporary register 4 */
rt_ubase_t
t5
;
/* x30 - t5 - temporary register 5 */
rt_ubase_t
t6
;
/* x31 - t6 - temporary register 6 */
};
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t
*
rt_hw_stack_init
(
void
*
tentry
,
void
*
parameter
,
rt_uint8_t
*
stack_addr
,
void
*
texit
)
{
struct
rt_hw_stack_frame
*
frame
;
rt_uint8_t
*
stk
;
int
i
;
stk
=
stack_addr
+
sizeof
(
rt_ubase_t
);
stk
=
(
rt_uint8_t
*
)
RT_ALIGN_DOWN
((
rt_ubase_t
)
stk
,
REGBYTES
);
stk
-=
sizeof
(
struct
rt_hw_stack_frame
);
frame
=
(
struct
rt_hw_stack_frame
*
)
stk
;
for
(
i
=
0
;
i
<
sizeof
(
struct
rt_hw_stack_frame
)
/
sizeof
(
rt_ubase_t
);
i
++
)
{
((
rt_ubase_t
*
)
frame
)[
i
]
=
0xdeadbeef
;
}
frame
->
ra
=
(
rt_ubase_t
)
texit
;
frame
->
a0
=
(
rt_ubase_t
)
parameter
;
frame
->
epc
=
(
rt_ubase_t
)
tentry
;
/* force to machine mode(MPP=11) and set MPIE to 1 */
frame
->
mstatus
=
0x00007880
;
return
stk
;
}
/*
* #ifdef RT_USING_SMP
* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
* #else
* void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
* #endif
*/
#ifndef RT_USING_SMP
void
rt_hw_context_switch_interrupt
(
rt_ubase_t
from
,
rt_ubase_t
to
,
rt_thread_t
from_thread
,
rt_thread_t
to_thread
)
{
if
(
rt_thread_switch_interrupt_flag
==
0
)
rt_interrupt_from_thread
=
from
;
rt_interrupt_to_thread
=
to
;
rt_thread_switch_interrupt_flag
=
1
;
return
;
}
#endif
/* end of RT_USING_SMP */
/** shutdown CPU */
void
rt_hw_cpu_shutdown
()
{
rt_uint32_t
level
;
rt_kprintf
(
"shutdown...
\n
"
);
level
=
rt_hw_interrupt_disable
();
while
(
level
)
{
RT_ASSERT
(
0
);
}
}
libcpu/risc-v/cv32e40p/cpuport.h
已删除
100644 → 0
浏览文件 @
e97ba95f
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-03 Bernard The first version
*/
#ifndef CPUPORT_H__
#define CPUPORT_H__
/* bytes of register width */
#ifdef ARCH_CPU_64BIT
#define STORE sd
#define LOAD ld
#define REGBYTES 8
#else
#define STORE sw
#define LOAD lw
#define REGBYTES 4
#endif
#endif
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