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提交 ab818cda 编写于 作者: L liufeilong
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参照龙芯1c手册更正看门狗寄存器宏定义

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libcpu/mips/loongson_1c/ls1c.h
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......@@ -18,36 +18,36 @@
#include "../common/mipsregs.h"
#define LS1C_ACPI_IRQ 0
#define LS1C_HPET_IRQ 1
//#define LS1C_UART0_IRQ 3 // linux中是3，v1.4版本的1c手册中是2，暂屏蔽，待确认
#define LS1C_UART1_IRQ 4
#define LS1C_UART2_IRQ 5
#define LS1C_CAN0_IRQ 6
#define LS1C_CAN1_IRQ 7
#define LS1C_SPI0_IRQ 8
#define LS1C_SPI1_IRQ 9
#define LS1C_AC97_IRQ 10
#define LS1C_MS_IRQ 11
#define LS1C_KB_IRQ 12
#define LS1C_DMA0_IRQ 13
#define LS1C_DMA1_IRQ 14
#define LS1C_DMA2_IRQ 15
#define LS1C_NAND_IRQ 16
#define LS1C_PWM0_IRQ 17
#define LS1C_PWM1_IRQ 18
#define LS1C_PWM2_IRQ 19
#define LS1C_PWM3_IRQ 20
#define LS1C_ACPI_IRQ 0
#define LS1C_HPET_IRQ 1
//#define LS1C_UART0_IRQ 3 // linux中是3，v1.4版本的1c手册中是2，暂屏蔽，待确认
#define LS1C_UART1_IRQ 4
#define LS1C_UART2_IRQ 5
#define LS1C_CAN0_IRQ 6
#define LS1C_CAN1_IRQ 7
#define LS1C_SPI0_IRQ 8
#define LS1C_SPI1_IRQ 9
#define LS1C_AC97_IRQ 10
#define LS1C_MS_IRQ 11
#define LS1C_KB_IRQ 12
#define LS1C_DMA0_IRQ 13
#define LS1C_DMA1_IRQ 14
#define LS1C_DMA2_IRQ 15
#define LS1C_NAND_IRQ 16
#define LS1C_PWM0_IRQ 17
#define LS1C_PWM1_IRQ 18
#define LS1C_PWM2_IRQ 19
#define LS1C_PWM3_IRQ 20
#define LS1C_RTC_INT0_IRQ 21
#define LS1C_RTC_INT1_IRQ 22
#define LS1C_RTC_INT2_IRQ 23
#define LS1C_UART3_IRQ 29
#define LS1C_ADC_IRQ 30
#define LS1C_SDIO_IRQ 31
#define LS1C_UART3_IRQ 29
#define LS1C_ADC_IRQ 30
#define LS1C_SDIO_IRQ 31
#define LS1C_EHCI_IRQ (32+0)
#define LS1C_OHCI_IRQ (32+1)
#define LS1C_EHCI_IRQ (32+0)
#define LS1C_OHCI_IRQ (32+1)
#define LS1C_OTG_IRQ (32+2)
#define LS1C_MAC_IRQ (32+3)
#define LS1C_CAM_IRQ (32+4)
......@@ -64,7 +64,7 @@
#define LS1C_I2C0_IRQ (32+19)
#define LS1C_GPIO_IRQ 64
#define LS1C_GPIO_IRQ 64
#define LS1C_GPIO_FIRST_IRQ 64
#define LS1C_GPIO_IRQ_COUNT 96
#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
......@@ -84,72 +84,72 @@
struct ls1c_intc_regs
{
volatile unsigned int int_isr;
volatile unsigned int int_en;
volatile unsigned int int_set;
volatile unsigned int int_clr; /* offset 0x10*/
volatile unsigned int int_pol;
volatile unsigned int int_edge; /* offset 0 */
volatile unsigned int int_isr;
volatile unsigned int int_en;
volatile unsigned int int_set;
volatile unsigned int int_clr; /* offset 0x10*/
volatile unsigned int int_pol;
volatile unsigned int int_edge; /* offset 0 */
};
struct ls1c_cop_global_regs
{
volatile unsigned int control;
volatile unsigned int rd_inten;
volatile unsigned int wr_inten;
volatile unsigned int rd_intisr; /* offset 0x10*/
volatile unsigned int wr_intisr;
unsigned int unused[11];
volatile unsigned int control;
volatile unsigned int rd_inten;
volatile unsigned int wr_inten;
volatile unsigned int rd_intisr; /* offset 0x10*/
volatile unsigned int wr_intisr;
unsigned int unused[11];
} ;
struct ls1c_cop_channel_regs
{
volatile unsigned int rd_control;
volatile unsigned int rd_src;
volatile unsigned int rd_cnt;
volatile unsigned int rd_status; /* offset 0x10*/
volatile unsigned int wr_control;
volatile unsigned int wr_src;
volatile unsigned int wr_cnt;
volatile unsigned int wr_status; /* offset 0x10*/
volatile unsigned int rd_control;
volatile unsigned int rd_src;
volatile unsigned int rd_cnt;
volatile unsigned int rd_status; /* offset 0x10*/
volatile unsigned int wr_control;
volatile unsigned int wr_src;
volatile unsigned int wr_cnt;
volatile unsigned int wr_status; /* offset 0x10*/
} ;
struct ls1c_cop_regs
{
struct ls1c_cop_global_regs global;
struct ls1c_cop_channel_regs chan[8][2];
struct ls1c_cop_global_regs global;
struct ls1c_cop_channel_regs chan[8][2];
} ;
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define GMAC0_BASE 0xBFE10000
#define GMAC0_DMA_BASE 0xBFE11000
#define GMAC1_BASE 0xBFE20000
#define GMAC1_DMA_BASE 0xBFE21000
#define I2C0_BASE 0xBFE58000
#define PWM0_BASE 0xBFE5C000
#define PWM1_BASE 0xBFE5C010
#define PWM2_BASE 0xBFE5C020
#define PWM3_BASE 0xBFE5C030
#define WDT_BASE 0xBFE5C060
#define RTC_BASE 0xBFE64000
#define I2C1_BASE 0xBFE68000
#define I2C2_BASE 0xBFE70000
#define AC97_BASE 0xBFE74000
#define NAND_BASE 0xBFE78000
#define SPI_BASE 0xBFE80000
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define GMAC0_BASE 0xBFE10000
#define GMAC0_DMA_BASE 0xBFE11000
#define GMAC1_BASE 0xBFE20000
#define GMAC1_DMA_BASE 0xBFE21000
#define I2C0_BASE 0xBFE58000
#define PWM0_BASE 0xBFE5C000
#define PWM1_BASE 0xBFE5C010
#define PWM2_BASE 0xBFE5C020
#define PWM3_BASE 0xBFE5C030
#define WDT_BASE 0xBFE5C060
#define RTC_BASE 0xBFE64000
#define I2C1_BASE 0xBFE68000
#define I2C2_BASE 0xBFE70000
#define AC97_BASE 0xBFE74000
#define NAND_BASE 0xBFE78000
#define SPI_BASE 0xBFE80000
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
/* Watch Dog registers */
#define WDT_EN __REG32(WDT_BASE + 0x00)
#define WDT_SET __REG32(WDT_BASE + 0x04)
#define WDT_TIMER __REG32(WDT_BASE + 0x08)
#define WDT_EN __REG32(WDT_BASE + 0x00)
#define WDT_SET __REG32(WDT_BASE + 0x08)
#define WDT_TIMER __REG32(WDT_BASE + 0x04)
#define PLL_FREQ __REG32(0xbfe78030)
#define PLL_DIV_PARAM __REG32(0xbfe78034)
#define PLL_FREQ __REG32(0xbfe78030)
#define PLL_DIV_PARAM __REG32(0xbfe78034)
#endif
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