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6c907c3a
编写于
3月 27, 2021
作者:
mysterywolf
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电子邮件补丁
差异文件
[libcpu] auto formatted
上级
1ba020f3
变更
225
展开全部
隐藏空白更改
内联
并排
Showing
225 changed file
with
9844 addition
and
9844 deletion
+9844
-9844
libcpu/aarch64/common/armv8.h
libcpu/aarch64/common/armv8.h
+40
-40
libcpu/aarch64/common/cp15.h
libcpu/aarch64/common/cp15.h
+3
-3
libcpu/aarch64/common/cpu.c
libcpu/aarch64/common/cpu.c
+1
-1
libcpu/aarch64/common/gic/gic_pl400.c
libcpu/aarch64/common/gic/gic_pl400.c
+1
-1
libcpu/aarch64/common/gic/gic_pl400.h
libcpu/aarch64/common/gic/gic_pl400.h
+1
-1
libcpu/aarch64/common/mmu.c
libcpu/aarch64/common/mmu.c
+16
-16
libcpu/aarch64/common/mmu.h
libcpu/aarch64/common/mmu.h
+1
-1
libcpu/aarch64/cortex-a53/interrupt.c
libcpu/aarch64/cortex-a53/interrupt.c
+5
-5
libcpu/aarch64/cortex-a53/interrupt.h
libcpu/aarch64/cortex-a53/interrupt.h
+1
-1
libcpu/aarch64/cortex-a53/stack.c
libcpu/aarch64/cortex-a53/stack.c
+54
-54
libcpu/aarch64/cortex-a53/trap.c
libcpu/aarch64/cortex-a53/trap.c
+10
-10
libcpu/aarch64/cortex-a72/interrupt.c
libcpu/aarch64/cortex-a72/interrupt.c
+1
-1
libcpu/aarch64/cortex-a72/interrupt.h
libcpu/aarch64/cortex-a72/interrupt.h
+1
-1
libcpu/aarch64/cortex-a72/stack.c
libcpu/aarch64/cortex-a72/stack.c
+54
-54
libcpu/aarch64/cortex-a72/trap.c
libcpu/aarch64/cortex-a72/trap.c
+10
-10
libcpu/arc/em/cpuport.c
libcpu/arc/em/cpuport.c
+12
-12
libcpu/arm/AT91SAM7S/AT91SAM7S.h
libcpu/arm/AT91SAM7S/AT91SAM7S.h
+239
-239
libcpu/arm/AT91SAM7S/cpu.c
libcpu/arm/AT91SAM7S/cpu.c
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-3
libcpu/arm/AT91SAM7S/interrupt.c
libcpu/arm/AT91SAM7S/interrupt.c
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-23
libcpu/arm/AT91SAM7S/serial.c
libcpu/arm/AT91SAM7S/serial.c
+291
-291
libcpu/arm/AT91SAM7S/serial.h
libcpu/arm/AT91SAM7S/serial.h
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-38
libcpu/arm/AT91SAM7S/stack.c
libcpu/arm/AT91SAM7S/stack.c
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-1
libcpu/arm/AT91SAM7S/trap.c
libcpu/arm/AT91SAM7S/trap.c
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-5
libcpu/arm/AT91SAM7X/cpu.c
libcpu/arm/AT91SAM7X/cpu.c
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-3
libcpu/arm/AT91SAM7X/interrupt.c
libcpu/arm/AT91SAM7X/interrupt.c
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-33
libcpu/arm/AT91SAM7X/stack.c
libcpu/arm/AT91SAM7X/stack.c
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-1
libcpu/arm/AT91SAM7X/trap.c
libcpu/arm/AT91SAM7X/trap.c
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-12
libcpu/arm/am335x/am33xx.h
libcpu/arm/am335x/am33xx.h
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-45
libcpu/arm/am335x/cpu.c
libcpu/arm/am335x/cpu.c
+56
-56
libcpu/arm/am335x/interrupt.c
libcpu/arm/am335x/interrupt.c
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-4
libcpu/arm/am335x/interrupt.h
libcpu/arm/am335x/interrupt.h
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-21
libcpu/arm/am335x/mmu.c
libcpu/arm/am335x/mmu.c
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-54
libcpu/arm/am335x/mmu.h
libcpu/arm/am335x/mmu.h
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-22
libcpu/arm/am335x/stack.c
libcpu/arm/am335x/stack.c
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-1
libcpu/arm/am335x/trap.c
libcpu/arm/am335x/trap.c
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-33
libcpu/arm/arm926/cpuport.c
libcpu/arm/arm926/cpuport.c
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-1
libcpu/arm/arm926/machine.c
libcpu/arm/arm926/machine.c
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-1
libcpu/arm/arm926/mmu.c
libcpu/arm/arm926/mmu.c
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-1
libcpu/arm/arm926/mmu.h
libcpu/arm/arm926/mmu.h
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-1
libcpu/arm/arm926/stack.c
libcpu/arm/arm926/stack.c
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libcpu/arm/arm926/trap.c
libcpu/arm/arm926/trap.c
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-1
libcpu/arm/armv6/armv6.h
libcpu/arm/armv6/armv6.h
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-21
libcpu/arm/armv6/cpuport.c
libcpu/arm/armv6/cpuport.c
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libcpu/arm/armv6/mmu.c
libcpu/arm/armv6/mmu.c
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-319
libcpu/arm/armv6/mmu.h
libcpu/arm/armv6/mmu.h
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-27
libcpu/arm/armv6/stack.c
libcpu/arm/armv6/stack.c
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libcpu/arm/armv6/vfp.c
libcpu/arm/armv6/vfp.c
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-1
libcpu/arm/armv6/vfp.h
libcpu/arm/armv6/vfp.h
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libcpu/arm/common/backtrace.c
libcpu/arm/common/backtrace.c
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libcpu/arm/common/div0.c
libcpu/arm/common/div0.c
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libcpu/arm/common/showmem.c
libcpu/arm/common/showmem.c
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libcpu/arm/cortex-a/armv7.h
libcpu/arm/cortex-a/armv7.h
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libcpu/arm/cortex-a/cache.c
libcpu/arm/cortex-a/cache.c
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libcpu/arm/cortex-a/cp15.h
libcpu/arm/cortex-a/cp15.h
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libcpu/arm/cortex-a/cpu.c
libcpu/arm/cortex-a/cpu.c
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-1
libcpu/arm/cortex-a/gic.c
libcpu/arm/cortex-a/gic.c
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-1
libcpu/arm/cortex-a/gic.h
libcpu/arm/cortex-a/gic.h
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-1
libcpu/arm/cortex-a/interrupt.c
libcpu/arm/cortex-a/interrupt.c
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-1
libcpu/arm/cortex-a/interrupt.h
libcpu/arm/cortex-a/interrupt.h
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-1
libcpu/arm/cortex-a/mmu.c
libcpu/arm/cortex-a/mmu.c
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-1
libcpu/arm/cortex-a/mmu.h
libcpu/arm/cortex-a/mmu.h
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-1
libcpu/arm/cortex-a/pmu.c
libcpu/arm/cortex-a/pmu.c
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-1
libcpu/arm/cortex-a/pmu.h
libcpu/arm/cortex-a/pmu.h
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-1
libcpu/arm/cortex-a/stack.c
libcpu/arm/cortex-a/stack.c
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-1
libcpu/arm/cortex-a/trap.c
libcpu/arm/cortex-a/trap.c
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-1
libcpu/arm/cortex-m0/cpuport.c
libcpu/arm/cortex-m0/cpuport.c
+1
-1
libcpu/arm/cortex-m23/cpuport.c
libcpu/arm/cortex-m23/cpuport.c
+1
-1
libcpu/arm/cortex-m3/cpuport.c
libcpu/arm/cortex-m3/cpuport.c
+1
-1
libcpu/arm/cortex-m33/cpuport.c
libcpu/arm/cortex-m33/cpuport.c
+2
-2
libcpu/arm/cortex-m33/trustzone.c
libcpu/arm/cortex-m33/trustzone.c
+3
-3
libcpu/arm/cortex-m4/cpuport.c
libcpu/arm/cortex-m4/cpuport.c
+2
-2
libcpu/arm/cortex-m7/cpu_cache.c
libcpu/arm/cortex-m7/cpu_cache.c
+2
-2
libcpu/arm/cortex-m7/cpuport.c
libcpu/arm/cortex-m7/cpuport.c
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-1
libcpu/arm/cortex-r4/armv7.h
libcpu/arm/cortex-r4/armv7.h
+18
-18
libcpu/arm/cortex-r4/cpu.c
libcpu/arm/cortex-r4/cpu.c
+9
-9
libcpu/arm/cortex-r4/interrupt.c
libcpu/arm/cortex-r4/interrupt.c
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-26
libcpu/arm/cortex-r4/stack.c
libcpu/arm/cortex-r4/stack.c
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-1
libcpu/arm/cortex-r4/trap.c
libcpu/arm/cortex-r4/trap.c
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libcpu/arm/dm36x/cpuport.c
libcpu/arm/dm36x/cpuport.c
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libcpu/arm/dm36x/mmu.c
libcpu/arm/dm36x/mmu.c
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libcpu/arm/dm36x/mmu.h
libcpu/arm/dm36x/mmu.h
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-11
libcpu/arm/dm36x/stack.c
libcpu/arm/dm36x/stack.c
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libcpu/arm/lpc214x/cpuport.c
libcpu/arm/lpc214x/cpuport.c
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-67
libcpu/arm/lpc214x/lpc214x.h
libcpu/arm/lpc214x/lpc214x.h
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-24
libcpu/arm/lpc24xx/LPC24xx.h
libcpu/arm/lpc24xx/LPC24xx.h
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-340
libcpu/arm/lpc24xx/cpu.c
libcpu/arm/lpc24xx/cpu.c
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libcpu/arm/lpc24xx/interrupt.c
libcpu/arm/lpc24xx/interrupt.c
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-38
libcpu/arm/lpc24xx/stack.c
libcpu/arm/lpc24xx/stack.c
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-1
libcpu/arm/lpc24xx/trap.c
libcpu/arm/lpc24xx/trap.c
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libcpu/arm/realview-a8-vmm/armv7.h
libcpu/arm/realview-a8-vmm/armv7.h
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libcpu/arm/realview-a8-vmm/cp15.h
libcpu/arm/realview-a8-vmm/cp15.h
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libcpu/arm/realview-a8-vmm/cpu.c
libcpu/arm/realview-a8-vmm/cpu.c
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-8
libcpu/arm/realview-a8-vmm/gic.c
libcpu/arm/realview-a8-vmm/gic.c
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-1
libcpu/arm/realview-a8-vmm/gic.h
libcpu/arm/realview-a8-vmm/gic.h
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libcpu/arm/realview-a8-vmm/interrupt.c
libcpu/arm/realview-a8-vmm/interrupt.c
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libcpu/arm/realview-a8-vmm/interrupt.h
libcpu/arm/realview-a8-vmm/interrupt.h
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libcpu/arm/realview-a8-vmm/mmu.c
libcpu/arm/realview-a8-vmm/mmu.c
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-1
libcpu/arm/realview-a8-vmm/pmu.c
libcpu/arm/realview-a8-vmm/pmu.c
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libcpu/arm/realview-a8-vmm/pmu.h
libcpu/arm/realview-a8-vmm/pmu.h
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-1
libcpu/arm/realview-a8-vmm/stack.c
libcpu/arm/realview-a8-vmm/stack.c
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libcpu/arm/realview-a8-vmm/trap.c
libcpu/arm/realview-a8-vmm/trap.c
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-2
libcpu/arm/s3c24x0/cpu.c
libcpu/arm/s3c24x0/cpu.c
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libcpu/arm/s3c24x0/interrupt.c
libcpu/arm/s3c24x0/interrupt.c
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libcpu/arm/s3c24x0/mmu.c
libcpu/arm/s3c24x0/mmu.c
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libcpu/arm/s3c24x0/rtc.c
libcpu/arm/s3c24x0/rtc.c
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libcpu/arm/s3c24x0/rtc.h
libcpu/arm/s3c24x0/rtc.h
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libcpu/arm/s3c24x0/s3c24x0.h
libcpu/arm/s3c24x0/s3c24x0.h
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libcpu/arm/s3c24x0/stack.c
libcpu/arm/s3c24x0/stack.c
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libcpu/arm/s3c24x0/system_clock.c
libcpu/arm/s3c24x0/system_clock.c
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-54
libcpu/arm/s3c24x0/trap.c
libcpu/arm/s3c24x0/trap.c
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libcpu/arm/s3c44b0/cpu.c
libcpu/arm/s3c44b0/cpu.c
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libcpu/arm/s3c44b0/interrupt.c
libcpu/arm/s3c44b0/interrupt.c
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libcpu/arm/s3c44b0/s3c44b0.h
libcpu/arm/s3c44b0/s3c44b0.h
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libcpu/arm/s3c44b0/serial.c
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libcpu/arm/s3c44b0/stack.c
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libcpu/arm/s3c44b0/trap.c
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libcpu/arm/sep4020/clk.c
libcpu/arm/sep4020/clk.c
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libcpu/arm/sep4020/cpu.c
libcpu/arm/sep4020/cpu.c
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libcpu/arm/sep4020/interrupt.c
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libcpu/arm/sep4020/sep4020.h
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libcpu/arm/sep4020/serial.c
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libcpu/arm/sep4020/serial.h
libcpu/arm/sep4020/serial.h
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libcpu/arm/sep4020/stack.c
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libcpu/arm/sep4020/trap.c
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libcpu/arm/zynqmp-r5/armv7.h
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libcpu/arm/zynqmp-r5/cache.c
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libcpu/arm/zynqmp-r5/xreg_cortexr5.h
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libcpu/avr32/uc3/serial.h
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libcpu/blackfin/bf53x/serial.c
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libcpu/blackfin/bf53x/serial.h
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libcpu/c-sky/ck802/core_ck802.h
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libcpu/ia32/__udivsi3.c
libcpu/ia32/__udivsi3.c
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libcpu/ia32/__umodsi3.c
libcpu/ia32/__umodsi3.c
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libcpu/ia32/cpuport.c
libcpu/ia32/cpuport.c
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libcpu/ia32/interrupt.c
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libcpu/ia32/trap.c
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libcpu/m16c/m16c62p/cpuport.c
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libcpu/mips/common/exception.c
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libcpu/mips/common/exception.h
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libcpu/mips/common/mips.h
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libcpu/mips/common/mips_cache.c
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libcpu/mips/common/mips_cfg.h
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libcpu/mips/common/mips_fpu.h
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libcpu/mips/common/ptrace.h
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libcpu/mips/common/stack.c
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libcpu/mips/common/stackframe.h
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libcpu/mips/gs232/gs232.h
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libcpu/mips/gs232/interrupt.c
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libcpu/mips/gs232/ls1b.h
libcpu/mips/gs232/ls1b.h
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libcpu/mips/gs232/ls1c.h
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libcpu/mips/gs232/timer.c
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libcpu/mips/gs264/cache.c
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libcpu/mips/gs264/cache.h
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libcpu/mips/gs264/mips_mmu.c
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libcpu/mips/gs264/mmu.c
libcpu/mips/gs264/mmu.c
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libcpu/mips/gs264/mmu.h
libcpu/mips/gs264/mmu.h
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libcpu/mips/pic32/cpuport.c
libcpu/mips/pic32/cpuport.c
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libcpu/mips/pic32/exceptions.c
libcpu/mips/pic32/exceptions.c
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libcpu/nios/nios_ii/stack.c
libcpu/nios/nios_ii/stack.c
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-34
libcpu/ppc/common/ptrace.h
libcpu/ppc/common/ptrace.h
+47
-47
libcpu/ppc/common/stack.c
libcpu/ppc/common/stack.c
+2
-2
libcpu/ppc/ppc405/context.h
libcpu/ppc/ppc405/context.h
+2
-2
libcpu/ppc/ppc405/include/asm/ppc405.h
libcpu/ppc/ppc405/include/asm/ppc405.h
+714
-714
libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h
libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h
+37
-37
libcpu/ppc/ppc405/include/asm/ppc4xx.h
libcpu/ppc/ppc405/include/asm/ppc4xx.h
+58
-58
libcpu/ppc/ppc405/include/asm/ppc_defs.h
libcpu/ppc/ppc405/include/asm/ppc_defs.h
+46
-46
libcpu/ppc/ppc405/include/asm/processor.h
libcpu/ppc/ppc405/include/asm/processor.h
+905
-905
libcpu/ppc/ppc405/include/asm/ptrace.h
libcpu/ppc/ppc405/include/asm/ptrace.h
+56
-56
libcpu/ppc/ppc405/include/asm/types.h
libcpu/ppc/ppc405/include/asm/types.h
+1
-1
libcpu/ppc/ppc405/include/config.h
libcpu/ppc/ppc405/include/config.h
+18
-18
libcpu/ppc/ppc405/interrupt.c
libcpu/ppc/ppc405/interrupt.c
+46
-46
libcpu/ppc/ppc405/io.h
libcpu/ppc/ppc405/io.h
+35
-35
libcpu/ppc/ppc405/serial.c
libcpu/ppc/ppc405/serial.c
+247
-247
libcpu/ppc/ppc405/traps.c
libcpu/ppc/ppc405/traps.c
+2
-2
libcpu/risc-v/common/cpuport.c
libcpu/risc-v/common/cpuport.c
+1
-1
libcpu/risc-v/common/cpuport.h
libcpu/risc-v/common/cpuport.h
+3
-3
libcpu/risc-v/common/riscv-ops.h
libcpu/risc-v/common/riscv-ops.h
+1
-1
libcpu/risc-v/common/riscv-plic.h
libcpu/risc-v/common/riscv-plic.h
+1
-1
libcpu/risc-v/k210/cpuport_smp.c
libcpu/risc-v/k210/cpuport_smp.c
+1
-1
libcpu/risc-v/k210/interrupt.c
libcpu/risc-v/k210/interrupt.c
+1
-1
libcpu/risc-v/k210/tick.c
libcpu/risc-v/k210/tick.c
+1
-1
libcpu/risc-v/k210/tick.h
libcpu/risc-v/k210/tick.h
+1
-1
libcpu/risc-v/nuclei/cpuport.c
libcpu/risc-v/nuclei/cpuport.c
+19
-19
libcpu/risc-v/nuclei/cpuport.h
libcpu/risc-v/nuclei/cpuport.h
+1
-1
libcpu/risc-v/rv32m1/interrupt.c
libcpu/risc-v/rv32m1/interrupt.c
+1
-1
libcpu/risc-v/t-head/e906/cpuport.c
libcpu/risc-v/t-head/e906/cpuport.c
+3
-3
libcpu/risc-v/t-head/e906/cpuport.h
libcpu/risc-v/t-head/e906/cpuport.h
+3
-3
libcpu/rx/cpuport.c
libcpu/rx/cpuport.c
+33
-33
libcpu/sim/posix/cpu_port.c
libcpu/sim/posix/cpu_port.c
+2
-2
libcpu/sim/win32/cpu_port.c
libcpu/sim/win32/cpu_port.c
+26
-26
libcpu/ti-dsp/c28x/cpuport.c
libcpu/ti-dsp/c28x/cpuport.c
+1
-1
libcpu/unicore32/sep6200/cpu.c
libcpu/unicore32/sep6200/cpu.c
+53
-53
libcpu/unicore32/sep6200/interrupt.c
libcpu/unicore32/sep6200/interrupt.c
+63
-63
libcpu/unicore32/sep6200/sep6200.h
libcpu/unicore32/sep6200/sep6200.h
+109
-109
libcpu/unicore32/sep6200/serial.c
libcpu/unicore32/sep6200/serial.c
+202
-202
libcpu/unicore32/sep6200/serial.h
libcpu/unicore32/sep6200/serial.h
+33
-33
libcpu/unicore32/sep6200/stack.c
libcpu/unicore32/sep6200/stack.c
+38
-38
libcpu/unicore32/sep6200/trap.c
libcpu/unicore32/sep6200/trap.c
+34
-34
libcpu/xilinx/microblaze/cpu.c
libcpu/xilinx/microblaze/cpu.c
+2
-2
libcpu/xilinx/microblaze/serial.c
libcpu/xilinx/microblaze/serial.c
+224
-224
libcpu/xilinx/microblaze/stack.c
libcpu/xilinx/microblaze/stack.c
+36
-36
libcpu/xilinx/microblaze/trap.c
libcpu/xilinx/microblaze/trap.c
+101
-101
未找到文件。
libcpu/aarch64/common/armv8.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-202
0
, RT-Thread Development Team
* Copyright (c) 2006-202
1
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -14,47 +14,47 @@
/* the exception stack without VFP registers */
struct
rt_hw_exp_stack
{
unsigned
long
long
pc
;
unsigned
long
long
spsr
;
unsigned
long
long
x30
;
unsigned
long
long
xz
;
unsigned
long
long
x28
;
unsigned
long
long
x29
;
unsigned
long
long
x26
;
unsigned
long
long
x27
;
unsigned
long
long
x24
;
unsigned
long
long
x25
;
unsigned
long
long
x22
;
unsigned
long
long
x23
;
unsigned
long
long
x20
;
unsigned
long
long
x21
;
unsigned
long
long
x18
;
unsigned
long
long
x19
;
unsigned
long
long
x16
;
unsigned
long
long
x17
;
unsigned
long
long
x14
;
unsigned
long
long
x15
;
unsigned
long
long
x12
;
unsigned
long
long
x13
;
unsigned
long
long
x10
;
unsigned
long
long
x11
;
unsigned
long
long
x8
;
unsigned
long
long
x9
;
unsigned
long
long
x6
;
unsigned
long
long
x7
;
unsigned
long
long
x4
;
unsigned
long
long
x5
;
unsigned
long
long
x2
;
unsigned
long
long
x3
;
unsigned
long
long
x0
;
unsigned
long
long
x1
;
unsigned
long
long
pc
;
unsigned
long
long
spsr
;
unsigned
long
long
x30
;
unsigned
long
long
xz
;
unsigned
long
long
x28
;
unsigned
long
long
x29
;
unsigned
long
long
x26
;
unsigned
long
long
x27
;
unsigned
long
long
x24
;
unsigned
long
long
x25
;
unsigned
long
long
x22
;
unsigned
long
long
x23
;
unsigned
long
long
x20
;
unsigned
long
long
x21
;
unsigned
long
long
x18
;
unsigned
long
long
x19
;
unsigned
long
long
x16
;
unsigned
long
long
x17
;
unsigned
long
long
x14
;
unsigned
long
long
x15
;
unsigned
long
long
x12
;
unsigned
long
long
x13
;
unsigned
long
long
x10
;
unsigned
long
long
x11
;
unsigned
long
long
x8
;
unsigned
long
long
x9
;
unsigned
long
long
x6
;
unsigned
long
long
x7
;
unsigned
long
long
x4
;
unsigned
long
long
x5
;
unsigned
long
long
x2
;
unsigned
long
long
x3
;
unsigned
long
long
x0
;
unsigned
long
long
x1
;
};
#define SP_ELx
( ( unsigned long long ) 0x01 )
#define SP_EL0
( ( unsigned long long ) 0x00 )
#define PSTATE_EL1
( ( unsigned long long ) 0x04 )
#define PSTATE_EL2
( ( unsigned long long ) 0x08 )
#define PSTATE_EL3
( ( unsigned long long ) 0x0c )
#define SP_ELx
( ( unsigned long long ) 0x01 )
#define SP_EL0
( ( unsigned long long ) 0x00 )
#define PSTATE_EL1
( ( unsigned long long ) 0x04 )
#define PSTATE_EL2
( ( unsigned long long ) 0x08 )
#define PSTATE_EL3
( ( unsigned long long ) 0x0c )
rt_ubase_t
rt_hw_get_current_el
(
void
);
void
rt_hw_set_elx_env
(
void
);
...
...
libcpu/aarch64/common/cp15.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-202
0
, RT-Thread Development Team
* Copyright (c) 2006-202
1
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -55,7 +55,7 @@ static inline void send_ipi_msg(int cpu, int ipi_vector)
static
inline
void
setup_bootstrap_addr
(
int
cpu
,
int
addr
)
{
CORE_MAILBOX3_SET
(
cpu
)
=
addr
;
CORE_MAILBOX3_SET
(
cpu
)
=
addr
;
}
static
inline
void
enable_cpu_ipi_intr
(
int
cpu
)
...
...
@@ -65,7 +65,7 @@ static inline void enable_cpu_ipi_intr(int cpu)
static
inline
void
enable_cpu_timer_intr
(
int
cpu
)
{
CORETIMER_INTCTL
(
cpu
)
=
0x8
;
CORETIMER_INTCTL
(
cpu
)
=
0x8
;
}
static
inline
void
enable_cntv
(
void
)
...
...
libcpu/aarch64/common/cpu.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
19
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/aarch64/common/gic/gic_pl400.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/aarch64/common/gic/gic_pl400.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/aarch64/common/mmu.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-202
0
, RT-Thread Development Team
* Copyright (c) 2006-202
1
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -52,7 +52,7 @@ void mmu_memset(char *dst, char v, size_t len)
}
static
unsigned
long
__page_off
=
0
;
static
unsigned
long
get_free_page
(
void
)
static
unsigned
long
get_free_page
(
void
)
{
__page_off
+=
512
;
return
(
unsigned
long
)(
main_tbl
+
__page_off
);
...
...
@@ -128,7 +128,7 @@ void mmu_enable(void)
}
static
int
map_single_page_2M
(
unsigned
long
*
lv0_tbl
,
unsigned
long
va
,
unsigned
long
pa
,
unsigned
long
attr
)
static
int
map_single_page_2M
(
unsigned
long
*
lv0_tbl
,
unsigned
long
va
,
unsigned
long
pa
,
unsigned
long
attr
)
{
int
level
;
unsigned
long
*
cur_lv_tbl
=
lv0_tbl
;
...
...
@@ -136,22 +136,22 @@ static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned
unsigned
long
off
;
int
level_shift
=
39
;
if
(
va
&
(
0x200000UL
-
1
))
if
(
va
&
(
0x200000UL
-
1
))
{
return
MMU_MAP_ERROR_VANOTALIGN
;
}
if
(
pa
&
(
0x200000UL
-
1
))
if
(
pa
&
(
0x200000UL
-
1
))
{
return
MMU_MAP_ERROR_PANOTALIGN
;
}
for
(
level
=
0
;
level
<
2
;
level
++
)
for
(
level
=
0
;
level
<
2
;
level
++
)
{
off
=
(
va
>>
level_shift
);
off
&=
MMU_LEVEL_MASK
;
if
((
cur_lv_tbl
[
off
]
&
1
)
==
0
)
if
((
cur_lv_tbl
[
off
]
&
1
)
==
0
)
{
page
=
get_free_page
();
if
(
!
page
)
if
(
!
page
)
{
return
MMU_MAP_ERROR_NOPAGE
;
}
...
...
@@ -159,7 +159,7 @@ static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned
cur_lv_tbl
[
off
]
=
page
|
0x3UL
;
}
page
=
cur_lv_tbl
[
off
];
if
(
!
(
page
&
0x2
))
if
(
!
(
page
&
0x2
))
{
//is block! error!
return
MMU_MAP_ERROR_CONFLICT
;
...
...
@@ -239,8 +239,8 @@ static int level2shift(int level)
static
uint64_t
*
get_level_table
(
uint64_t
*
pte
)
{
uint64_t
*
table
=
(
uint64_t
*
)(
*
pte
&
XLAT_ADDR_MASK
);
if
(
pte_type
(
pte
)
!=
PMD_TYPE_TABLE
)
if
(
pte_type
(
pte
)
!=
PMD_TYPE_TABLE
)
{
table
=
create_table
();
set_table
(
pte
,
table
);
...
...
@@ -259,10 +259,10 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
int
level
=
0
;
addr
=
virt
;
while
(
size
)
while
(
size
)
{
table
=
&
main_tbl
[
0
];
for
(
level
=
0
;
level
<
4
;
level
++
)
for
(
level
=
0
;
level
<
4
;
level
++
)
{
block_shift
=
level2shift
(
level
);
idx
=
addr
>>
block_shift
;
...
...
@@ -270,7 +270,7 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
block_size
=
(
uint64_t
)(
1L
<<
block_shift
);
pte
=
table
+
idx
;
if
(
size
>=
block_size
&&
IS_ALIGNED
(
addr
,
block_size
))
if
(
size
>=
block_size
&&
IS_ALIGNED
(
addr
,
block_size
))
{
attr
&=
0xfff0000000000ffcUL
;
if
(
level
!=
3
)
...
...
@@ -298,7 +298,7 @@ void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned
void
rt_hw_dcache_enable
(
void
)
{
if
(
!
(
get_sctlr
()
&
CR_M
))
if
(
!
(
get_sctlr
()
&
CR_M
))
{
rt_kprintf
(
"please init mmu!
\n
"
);
}
...
...
@@ -364,4 +364,4 @@ void rt_hw_icache_invalidate_all(void)
void
rt_hw_icache_disable
(
void
)
{
set_sctlr
(
get_sctlr
()
&
~
CR_I
);
}
\ No newline at end of file
}
libcpu/aarch64/common/mmu.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-202
0
, RT-Thread Development Team
* Copyright (c) 2006-202
1
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/aarch64/cortex-a53/interrupt.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
19
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -7,7 +7,7 @@
* Date Author Notes
* 2018/5/3 Bernard first version
* 2019-07-28 zdzn add smp support
* 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues,
* 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues,
* write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
*/
...
...
@@ -160,15 +160,15 @@ void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
}
if
(
cpu_mask
&
0x2
)
{
send_ipi_msg
(
1
,
ipi_vector
);
send_ipi_msg
(
1
,
ipi_vector
);
}
if
(
cpu_mask
&
0x4
)
{
send_ipi_msg
(
2
,
ipi_vector
);
send_ipi_msg
(
2
,
ipi_vector
);
}
if
(
cpu_mask
&
0x8
)
{
send_ipi_msg
(
3
,
ipi_vector
);
send_ipi_msg
(
3
,
ipi_vector
);
}
__DSB
();
}
...
...
libcpu/aarch64/cortex-a53/interrupt.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-202
0
, RT-Thread Development Team
* Copyright (c) 2006-202
1
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/aarch64/cortex-a53/stack.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
19
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -21,70 +21,70 @@
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t
*
rt_hw_stack_init
(
void
*
tentry
,
void
*
parameter
,
rt_uint8_t
*
stack_addr
,
void
*
texit
)
rt_uint8_t
*
stack_addr
,
void
*
texit
)
{
rt_ubase_t
*
stk
;
rt_ubase_t
current_el
;
rt_ubase_t
*
stk
;
rt_ubase_t
current_el
;
stk
=
(
rt_ubase_t
*
)
stack_addr
;
stk
=
(
rt_ubase_t
*
)
stack_addr
;
*
(
--
stk
)
=
(
rt_ubase_t
)
11
;
/* X1 */
*
(
--
stk
)
=
(
rt_ubase_t
)
parameter
;
/* X0 */
*
(
--
stk
)
=
(
rt_ubase_t
)
33
;
/* X3 */
*
(
--
stk
)
=
(
rt_ubase_t
)
22
;
/* X2 */
*
(
--
stk
)
=
(
rt_ubase_t
)
55
;
/* X5 */
*
(
--
stk
)
=
(
rt_ubase_t
)
44
;
/* X4 */
*
(
--
stk
)
=
(
rt_ubase_t
)
77
;
/* X7 */
*
(
--
stk
)
=
(
rt_ubase_t
)
66
;
/* X6 */
*
(
--
stk
)
=
(
rt_ubase_t
)
99
;
/* X9 */
*
(
--
stk
)
=
(
rt_ubase_t
)
88
;
/* X8 */
*
(
--
stk
)
=
(
rt_ubase_t
)
11
;
/* X11 */
*
(
--
stk
)
=
(
rt_ubase_t
)
10
;
/* X10 */
*
(
--
stk
)
=
(
rt_ubase_t
)
13
;
/* X13 */
*
(
--
stk
)
=
(
rt_ubase_t
)
12
;
/* X12 */
*
(
--
stk
)
=
(
rt_ubase_t
)
15
;
/* X15 */
*
(
--
stk
)
=
(
rt_ubase_t
)
14
;
/* X14 */
*
(
--
stk
)
=
(
rt_ubase_t
)
17
;
/* X17 */
*
(
--
stk
)
=
(
rt_ubase_t
)
16
;
/* X16 */
*
(
--
stk
)
=
(
rt_ubase_t
)
19
;
/* X19 */
*
(
--
stk
)
=
(
rt_ubase_t
)
18
;
/* X18 */
*
(
--
stk
)
=
(
rt_ubase_t
)
21
;
/* X21 */
*
(
--
stk
)
=
(
rt_ubase_t
)
20
;
/* X20 */
*
(
--
stk
)
=
(
rt_ubase_t
)
23
;
/* X23 */
*
(
--
stk
)
=
(
rt_ubase_t
)
22
;
/* X22 */
*
(
--
stk
)
=
(
rt_ubase_t
)
25
;
/* X25 */
*
(
--
stk
)
=
(
rt_ubase_t
)
24
;
/* X24 */
*
(
--
stk
)
=
(
rt_ubase_t
)
27
;
/* X27 */
*
(
--
stk
)
=
(
rt_ubase_t
)
26
;
/* X26 */
*
(
--
stk
)
=
(
rt_ubase_t
)
29
;
/* X29 */
*
(
--
stk
)
=
(
rt_ubase_t
)
28
;
/* X28 */
*
(
--
stk
)
=
(
rt_ubase_t
)
0
;
/* XZR - has no effect, used so there are an even number of registers. */
*
(
--
stk
)
=
(
rt_ubase_t
)
texit
;
/* X30 - procedure call link register. */
*
(
--
stk
)
=
(
rt_ubase_t
)
11
;
/* X1 */
*
(
--
stk
)
=
(
rt_ubase_t
)
parameter
;
/* X0 */
*
(
--
stk
)
=
(
rt_ubase_t
)
33
;
/* X3 */
*
(
--
stk
)
=
(
rt_ubase_t
)
22
;
/* X2 */
*
(
--
stk
)
=
(
rt_ubase_t
)
55
;
/* X5 */
*
(
--
stk
)
=
(
rt_ubase_t
)
44
;
/* X4 */
*
(
--
stk
)
=
(
rt_ubase_t
)
77
;
/* X7 */
*
(
--
stk
)
=
(
rt_ubase_t
)
66
;
/* X6 */
*
(
--
stk
)
=
(
rt_ubase_t
)
99
;
/* X9 */
*
(
--
stk
)
=
(
rt_ubase_t
)
88
;
/* X8 */
*
(
--
stk
)
=
(
rt_ubase_t
)
11
;
/* X11 */
*
(
--
stk
)
=
(
rt_ubase_t
)
10
;
/* X10 */
*
(
--
stk
)
=
(
rt_ubase_t
)
13
;
/* X13 */
*
(
--
stk
)
=
(
rt_ubase_t
)
12
;
/* X12 */
*
(
--
stk
)
=
(
rt_ubase_t
)
15
;
/* X15 */
*
(
--
stk
)
=
(
rt_ubase_t
)
14
;
/* X14 */
*
(
--
stk
)
=
(
rt_ubase_t
)
17
;
/* X17 */
*
(
--
stk
)
=
(
rt_ubase_t
)
16
;
/* X16 */
*
(
--
stk
)
=
(
rt_ubase_t
)
19
;
/* X19 */
*
(
--
stk
)
=
(
rt_ubase_t
)
18
;
/* X18 */
*
(
--
stk
)
=
(
rt_ubase_t
)
21
;
/* X21 */
*
(
--
stk
)
=
(
rt_ubase_t
)
20
;
/* X20 */
*
(
--
stk
)
=
(
rt_ubase_t
)
23
;
/* X23 */
*
(
--
stk
)
=
(
rt_ubase_t
)
22
;
/* X22 */
*
(
--
stk
)
=
(
rt_ubase_t
)
25
;
/* X25 */
*
(
--
stk
)
=
(
rt_ubase_t
)
24
;
/* X24 */
*
(
--
stk
)
=
(
rt_ubase_t
)
27
;
/* X27 */
*
(
--
stk
)
=
(
rt_ubase_t
)
26
;
/* X26 */
*
(
--
stk
)
=
(
rt_ubase_t
)
29
;
/* X29 */
*
(
--
stk
)
=
(
rt_ubase_t
)
28
;
/* X28 */
*
(
--
stk
)
=
(
rt_ubase_t
)
0
;
/* XZR - has no effect, used so there are an even number of registers. */
*
(
--
stk
)
=
(
rt_ubase_t
)
texit
;
/* X30 - procedure call link register. */
current_el
=
rt_hw_get_current_el
();
current_el
=
rt_hw_get_current_el
();
if
(
current_el
==
3
)
{
*
(
--
stk
)
=
INITIAL_SPSR_EL3
;
}
else
if
(
current_el
==
2
)
{
*
(
--
stk
)
=
INITIAL_SPSR_EL2
;
}
else
{
*
(
--
stk
)
=
INITIAL_SPSR_EL1
;
}
if
(
current_el
==
3
)
{
*
(
--
stk
)
=
INITIAL_SPSR_EL3
;
}
else
if
(
current_el
==
2
)
{
*
(
--
stk
)
=
INITIAL_SPSR_EL2
;
}
else
{
*
(
--
stk
)
=
INITIAL_SPSR_EL1
;
}
*
(
--
stk
)
=
(
rt_ubase_t
)
tentry
;
/* Exception return address. */
*
(
--
stk
)
=
(
rt_ubase_t
)
tentry
;
/* Exception return address. */
/* return task's current stack address */
return
(
rt_uint8_t
*
)
stk
;
/* return task's current stack address */
return
(
rt_uint8_t
*
)
stk
;
}
libcpu/aarch64/cortex-a53/trap.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-202
0
, RT-Thread Development Team
* Copyright (c) 2006-202
1
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
*
* Date Author Notes
* 2018-10-06 ZhaoXiaowei the first version
*/
...
...
@@ -28,14 +28,14 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
rt_kprintf
(
"Execption:
\n
"
);
rt_kprintf
(
"r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx
\n
"
,
regs
->
x0
,
regs
->
x1
,
regs
->
x2
,
regs
->
x3
);
rt_kprintf
(
"r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx
\n
"
,
regs
->
x4
,
regs
->
x5
,
regs
->
x6
,
regs
->
x7
);
rt_kprintf
(
"r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx
\n
"
,
regs
->
x8
,
regs
->
x9
,
regs
->
x10
,
regs
->
x11
);
rt_kprintf
(
"r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx
\n
"
,
regs
->
x12
,
regs
->
x13
,
regs
->
x14
,
regs
->
x15
);
rt_kprintf
(
"r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx
\n
"
,
regs
->
x16
,
regs
->
x17
,
regs
->
x18
,
regs
->
x19
);
rt_kprintf
(
"r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx
\n
"
,
regs
->
x20
,
regs
->
x21
,
regs
->
x22
,
regs
->
x23
);
rt_kprintf
(
"r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx
\n
"
,
regs
->
x8
,
regs
->
x9
,
regs
->
x10
,
regs
->
x11
);
rt_kprintf
(
"r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx
\n
"
,
regs
->
x12
,
regs
->
x13
,
regs
->
x14
,
regs
->
x15
);
rt_kprintf
(
"r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx
\n
"
,
regs
->
x16
,
regs
->
x17
,
regs
->
x18
,
regs
->
x19
);
rt_kprintf
(
"r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx
\n
"
,
regs
->
x20
,
regs
->
x21
,
regs
->
x22
,
regs
->
x23
);
rt_kprintf
(
"r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx
\n
"
,
regs
->
x24
,
regs
->
x25
,
regs
->
x26
,
regs
->
x27
);
rt_kprintf
(
"r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx
\n
"
,
regs
->
x28
,
regs
->
x29
,
regs
->
x30
);
rt_kprintf
(
"spsr:0x%16.16lx
\n
"
,
regs
->
spsr
);
rt_kprintf
(
"return pc:0x%16.16lx
\n
"
,
regs
->
pc
);
rt_kprintf
(
"r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx
\n
"
,
regs
->
x28
,
regs
->
x29
,
regs
->
x30
);
rt_kprintf
(
"spsr:0x%16.16lx
\n
"
,
regs
->
spsr
);
rt_kprintf
(
"return pc:0x%16.16lx
\n
"
,
regs
->
pc
);
}
/**
...
...
@@ -57,7 +57,7 @@ void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
}
#define GIC_ACK_INTID_MASK (0x000003ff)
#define CORE0_IRQ_SOURCE
(0x40000060)
#define CORE0_IRQ_SOURCE
(0x40000060)
void
rt_hw_trap_irq
(
void
)
{
...
...
libcpu/aarch64/cortex-a72/interrupt.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-202
0
, RT-Thread Development Team
* Copyright (c) 2006-202
1
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/aarch64/cortex-a72/interrupt.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-202
0
, RT-Thread Development Team
* Copyright (c) 2006-202
1
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/aarch64/cortex-a72/stack.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
19
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -21,70 +21,70 @@
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t
*
rt_hw_stack_init
(
void
*
tentry
,
void
*
parameter
,
rt_uint8_t
*
stack_addr
,
void
*
texit
)
rt_uint8_t
*
stack_addr
,
void
*
texit
)
{
rt_ubase_t
*
stk
;
rt_ubase_t
current_el
;
rt_ubase_t
*
stk
;
rt_ubase_t
current_el
;
stk
=
(
rt_ubase_t
*
)
stack_addr
;
stk
=
(
rt_ubase_t
*
)
stack_addr
;
*
(
--
stk
)
=
(
rt_ubase_t
)
11
;
/* X1 */
*
(
--
stk
)
=
(
rt_ubase_t
)
parameter
;
/* X0 */
*
(
--
stk
)
=
(
rt_ubase_t
)
33
;
/* X3 */
*
(
--
stk
)
=
(
rt_ubase_t
)
22
;
/* X2 */
*
(
--
stk
)
=
(
rt_ubase_t
)
55
;
/* X5 */
*
(
--
stk
)
=
(
rt_ubase_t
)
44
;
/* X4 */
*
(
--
stk
)
=
(
rt_ubase_t
)
77
;
/* X7 */
*
(
--
stk
)
=
(
rt_ubase_t
)
66
;
/* X6 */
*
(
--
stk
)
=
(
rt_ubase_t
)
99
;
/* X9 */
*
(
--
stk
)
=
(
rt_ubase_t
)
88
;
/* X8 */
*
(
--
stk
)
=
(
rt_ubase_t
)
11
;
/* X11 */
*
(
--
stk
)
=
(
rt_ubase_t
)
10
;
/* X10 */
*
(
--
stk
)
=
(
rt_ubase_t
)
13
;
/* X13 */
*
(
--
stk
)
=
(
rt_ubase_t
)
12
;
/* X12 */
*
(
--
stk
)
=
(
rt_ubase_t
)
15
;
/* X15 */
*
(
--
stk
)
=
(
rt_ubase_t
)
14
;
/* X14 */
*
(
--
stk
)
=
(
rt_ubase_t
)
17
;
/* X17 */
*
(
--
stk
)
=
(
rt_ubase_t
)
16
;
/* X16 */
*
(
--
stk
)
=
(
rt_ubase_t
)
19
;
/* X19 */
*
(
--
stk
)
=
(
rt_ubase_t
)
18
;
/* X18 */
*
(
--
stk
)
=
(
rt_ubase_t
)
21
;
/* X21 */
*
(
--
stk
)
=
(
rt_ubase_t
)
20
;
/* X20 */
*
(
--
stk
)
=
(
rt_ubase_t
)
23
;
/* X23 */
*
(
--
stk
)
=
(
rt_ubase_t
)
22
;
/* X22 */
*
(
--
stk
)
=
(
rt_ubase_t
)
25
;
/* X25 */
*
(
--
stk
)
=
(
rt_ubase_t
)
24
;
/* X24 */
*
(
--
stk
)
=
(
rt_ubase_t
)
27
;
/* X27 */
*
(
--
stk
)
=
(
rt_ubase_t
)
26
;
/* X26 */
*
(
--
stk
)
=
(
rt_ubase_t
)
29
;
/* X29 */
*
(
--
stk
)
=
(
rt_ubase_t
)
28
;
/* X28 */
*
(
--
stk
)
=
(
rt_ubase_t
)
0
;
/* XZR - has no effect, used so there are an even number of registers. */
*
(
--
stk
)
=
(
rt_ubase_t
)
texit
;
/* X30 - procedure call link register. */
*
(
--
stk
)
=
(
rt_ubase_t
)
11
;
/* X1 */
*
(
--
stk
)
=
(
rt_ubase_t
)
parameter
;
/* X0 */
*
(
--
stk
)
=
(
rt_ubase_t
)
33
;
/* X3 */
*
(
--
stk
)
=
(
rt_ubase_t
)
22
;
/* X2 */
*
(
--
stk
)
=
(
rt_ubase_t
)
55
;
/* X5 */
*
(
--
stk
)
=
(
rt_ubase_t
)
44
;
/* X4 */
*
(
--
stk
)
=
(
rt_ubase_t
)
77
;
/* X7 */
*
(
--
stk
)
=
(
rt_ubase_t
)
66
;
/* X6 */
*
(
--
stk
)
=
(
rt_ubase_t
)
99
;
/* X9 */
*
(
--
stk
)
=
(
rt_ubase_t
)
88
;
/* X8 */
*
(
--
stk
)
=
(
rt_ubase_t
)
11
;
/* X11 */
*
(
--
stk
)
=
(
rt_ubase_t
)
10
;
/* X10 */
*
(
--
stk
)
=
(
rt_ubase_t
)
13
;
/* X13 */
*
(
--
stk
)
=
(
rt_ubase_t
)
12
;
/* X12 */
*
(
--
stk
)
=
(
rt_ubase_t
)
15
;
/* X15 */
*
(
--
stk
)
=
(
rt_ubase_t
)
14
;
/* X14 */
*
(
--
stk
)
=
(
rt_ubase_t
)
17
;
/* X17 */
*
(
--
stk
)
=
(
rt_ubase_t
)
16
;
/* X16 */
*
(
--
stk
)
=
(
rt_ubase_t
)
19
;
/* X19 */
*
(
--
stk
)
=
(
rt_ubase_t
)
18
;
/* X18 */
*
(
--
stk
)
=
(
rt_ubase_t
)
21
;
/* X21 */
*
(
--
stk
)
=
(
rt_ubase_t
)
20
;
/* X20 */
*
(
--
stk
)
=
(
rt_ubase_t
)
23
;
/* X23 */
*
(
--
stk
)
=
(
rt_ubase_t
)
22
;
/* X22 */
*
(
--
stk
)
=
(
rt_ubase_t
)
25
;
/* X25 */
*
(
--
stk
)
=
(
rt_ubase_t
)
24
;
/* X24 */
*
(
--
stk
)
=
(
rt_ubase_t
)
27
;
/* X27 */
*
(
--
stk
)
=
(
rt_ubase_t
)
26
;
/* X26 */
*
(
--
stk
)
=
(
rt_ubase_t
)
29
;
/* X29 */
*
(
--
stk
)
=
(
rt_ubase_t
)
28
;
/* X28 */
*
(
--
stk
)
=
(
rt_ubase_t
)
0
;
/* XZR - has no effect, used so there are an even number of registers. */
*
(
--
stk
)
=
(
rt_ubase_t
)
texit
;
/* X30 - procedure call link register. */
current_el
=
rt_hw_get_current_el
();
current_el
=
rt_hw_get_current_el
();
if
(
current_el
==
3
)
{
*
(
--
stk
)
=
INITIAL_SPSR_EL3
;
}
else
if
(
current_el
==
2
)
{
*
(
--
stk
)
=
INITIAL_SPSR_EL2
;
}
else
{
*
(
--
stk
)
=
INITIAL_SPSR_EL1
;
}
if
(
current_el
==
3
)
{
*
(
--
stk
)
=
INITIAL_SPSR_EL3
;
}
else
if
(
current_el
==
2
)
{
*
(
--
stk
)
=
INITIAL_SPSR_EL2
;
}
else
{
*
(
--
stk
)
=
INITIAL_SPSR_EL1
;
}
*
(
--
stk
)
=
(
rt_ubase_t
)
tentry
;
/* Exception return address. */
*
(
--
stk
)
=
(
rt_ubase_t
)
tentry
;
/* Exception return address. */
/* return task's current stack address */
return
(
rt_uint8_t
*
)
stk
;
/* return task's current stack address */
return
(
rt_uint8_t
*
)
stk
;
}
libcpu/aarch64/cortex-a72/trap.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-202
0
, RT-Thread Development Team
* Copyright (c) 2006-202
1
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
*
* Date Author Notes
* 2018-10-06 ZhaoXiaowei the first version
*/
...
...
@@ -28,14 +28,14 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
rt_kprintf
(
"Execption:
\n
"
);
rt_kprintf
(
"r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx
\n
"
,
regs
->
x0
,
regs
->
x1
,
regs
->
x2
,
regs
->
x3
);
rt_kprintf
(
"r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx
\n
"
,
regs
->
x4
,
regs
->
x5
,
regs
->
x6
,
regs
->
x7
);
rt_kprintf
(
"r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx
\n
"
,
regs
->
x8
,
regs
->
x9
,
regs
->
x10
,
regs
->
x11
);
rt_kprintf
(
"r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx
\n
"
,
regs
->
x12
,
regs
->
x13
,
regs
->
x14
,
regs
->
x15
);
rt_kprintf
(
"r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx
\n
"
,
regs
->
x16
,
regs
->
x17
,
regs
->
x18
,
regs
->
x19
);
rt_kprintf
(
"r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx
\n
"
,
regs
->
x20
,
regs
->
x21
,
regs
->
x22
,
regs
->
x23
);
rt_kprintf
(
"r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx
\n
"
,
regs
->
x8
,
regs
->
x9
,
regs
->
x10
,
regs
->
x11
);
rt_kprintf
(
"r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx
\n
"
,
regs
->
x12
,
regs
->
x13
,
regs
->
x14
,
regs
->
x15
);
rt_kprintf
(
"r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx
\n
"
,
regs
->
x16
,
regs
->
x17
,
regs
->
x18
,
regs
->
x19
);
rt_kprintf
(
"r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx
\n
"
,
regs
->
x20
,
regs
->
x21
,
regs
->
x22
,
regs
->
x23
);
rt_kprintf
(
"r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx
\n
"
,
regs
->
x24
,
regs
->
x25
,
regs
->
x26
,
regs
->
x27
);
rt_kprintf
(
"r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx
\n
"
,
regs
->
x28
,
regs
->
x29
,
regs
->
x30
);
rt_kprintf
(
"spsr:0x%16.16lx
\n
"
,
regs
->
spsr
);
rt_kprintf
(
"return pc:0x%16.16lx
\n
"
,
regs
->
pc
);
rt_kprintf
(
"r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx
\n
"
,
regs
->
x28
,
regs
->
x29
,
regs
->
x30
);
rt_kprintf
(
"spsr:0x%16.16lx
\n
"
,
regs
->
spsr
);
rt_kprintf
(
"return pc:0x%16.16lx
\n
"
,
regs
->
pc
);
}
/**
...
...
@@ -64,7 +64,7 @@ void rt_hw_interrupt_ack(int fiq_irq);
void
rt_hw_trap_irq
(
void
)
{
void
*
param
;
int
ir
;
int
ir
;
rt_isr_handler_t
isr_func
;
extern
struct
rt_irq_desc
isr_table
[];
...
...
libcpu/arc/em/cpuport.c
浏览文件 @
6c907c3a
...
...
@@ -22,11 +22,11 @@ rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t
exc_nest_count
;
struct
init_stack_frame
{
rt_uint32_t
pc
;
rt_uint32_t
blink
;
rt_uint32_t
task
;
rt_uint32_t
status32
;
rt_uint32_t
r0
;
rt_uint32_t
pc
;
rt_uint32_t
blink
;
rt_uint32_t
task
;
rt_uint32_t
status32
;
rt_uint32_t
r0
;
};
/**
...
...
@@ -55,7 +55,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
stack_frame
->
blink
=
(
rt_uint32_t
)
texit
;
stack_frame
->
task
=
(
rt_uint32_t
)
tentry
;
stack_frame
->
status32
=
ARC_INIT_STATUS
;
stack_frame
->
r0
=
(
rt_uint32_t
)
parameter
;
stack_frame
->
r0
=
(
rt_uint32_t
)
parameter
;
return
stk
;
}
...
...
@@ -74,14 +74,14 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
void
set_hw_stack_check
(
rt_uint32_t
*
from
,
rt_uint32_t
*
to
)
{
struct
rt_thread
*
rt_thread_to
;
if
(
to
!=
NULL
)
{
if
(
to
!=
NULL
)
{
rt_thread_to
=
rt_container_of
(
to
,
struct
rt_thread
,
sp
);
#if ARC_FEATURE_SEC_PRESENT
arc_aux_write
(
AUX_S_KSTACK_TOP
,
(
uint32_t
)(
rt_thread_to
->
stack_addr
));
arc_aux_write
(
AUX_S_KSTACK_BASE
,
(
uint32_t
)(
rt_thread_to
->
stack_addr
)
+
rt_thread_to
->
stack_size
);
arc_aux_write
(
AUX_S_KSTACK_TOP
,
(
uint32_t
)(
rt_thread_to
->
stack_addr
));
arc_aux_write
(
AUX_S_KSTACK_BASE
,
(
uint32_t
)(
rt_thread_to
->
stack_addr
)
+
rt_thread_to
->
stack_size
);
#else
arc_aux_write
(
AUX_KSTACK_TOP
,
(
uint32_t
)(
rt_thread_to
->
stack_addr
));
arc_aux_write
(
AUX_KSTACK_BASE
,
(
uint32_t
)(
rt_thread_to
->
stack_addr
)
+
rt_thread_to
->
stack_size
);
arc_aux_write
(
AUX_KSTACK_TOP
,
(
uint32_t
)(
rt_thread_to
->
stack_addr
));
arc_aux_write
(
AUX_KSTACK_BASE
,
(
uint32_t
)(
rt_thread_to
->
stack_addr
)
+
rt_thread_to
->
stack_size
);
#endif
}
}
}
libcpu/arm/AT91SAM7S/AT91SAM7S.h
浏览文件 @
6c907c3a
此差异已折叠。
点击以展开。
libcpu/arm/AT91SAM7S/cpu.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset()
*/
RT_WEAK
void
rt_hw_cpu_shutdown
()
{
rt_kprintf
(
"shutdown...
\n
"
);
rt_kprintf
(
"shutdown...
\n
"
);
while
(
1
);
while
(
1
);
}
/*@}*/
libcpu/arm/AT91SAM7S/interrupt.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -11,7 +11,7 @@
#include <rtthread.h>
#include "AT91SAM7S.h"
#define MAX_HANDLERS
32
#define MAX_HANDLERS
32
extern
rt_uint32_t
rt_interrupt_nest
;
...
...
@@ -25,7 +25,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
void
rt_hw_interrupt_handler
(
int
vector
)
{
rt_kprintf
(
"Unhandled interrupt %d occured!!!
\n
"
,
vector
);
rt_kprintf
(
"Unhandled interrupt %d occured!!!
\n
"
,
vector
);
}
/**
...
...
@@ -33,18 +33,18 @@ void rt_hw_interrupt_handler(int vector)
*/
void
rt_hw_interrupt_init
()
{
rt_base_t
index
;
rt_base_t
index
;
for
(
index
=
0
;
index
<
MAX_HANDLERS
;
index
++
)
{
AT91C_AIC_SVR
(
index
)
=
(
rt_uint32_t
)
rt_hw_interrupt_handler
;
}
for
(
index
=
0
;
index
<
MAX_HANDLERS
;
index
++
)
{
AT91C_AIC_SVR
(
index
)
=
(
rt_uint32_t
)
rt_hw_interrupt_handler
;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest
=
0
;
rt_interrupt_from_thread
=
0
;
rt_interrupt_to_thread
=
0
;
rt_thread_switch_interrupt_flag
=
0
;
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest
=
0
;
rt_interrupt_from_thread
=
0
;
rt_interrupt_to_thread
=
0
;
rt_thread_switch_interrupt_flag
=
0
;
}
/**
...
...
@@ -53,11 +53,11 @@ void rt_hw_interrupt_init()
*/
void
rt_hw_interrupt_mask
(
int
vector
)
{
/* disable interrupt */
AT91C_AIC_IDCR
=
1
<<
vector
;
/* disable interrupt */
AT91C_AIC_IDCR
=
1
<<
vector
;
/* clear interrupt */
AT91C_AIC_ICCR
=
1
<<
vector
;
/* clear interrupt */
AT91C_AIC_ICCR
=
1
<<
vector
;
}
/**
...
...
@@ -66,7 +66,7 @@ void rt_hw_interrupt_mask(int vector)
*/
void
rt_hw_interrupt_umask
(
int
vector
)
{
AT91C_AIC_IECR
=
1
<<
vector
;
AT91C_AIC_IECR
=
1
<<
vector
;
}
/**
...
...
@@ -77,11 +77,11 @@ void rt_hw_interrupt_umask(int vector)
*/
void
rt_hw_interrupt_install
(
int
vector
,
rt_isr_handler_t
new_handler
,
rt_isr_handler_t
*
old_handler
)
{
if
(
vector
>=
0
&&
vector
<
MAX_HANDLERS
)
{
if
(
*
old_handler
!=
RT_NULL
)
*
old_handler
=
(
rt_isr_handler_t
)
AT91C_AIC_SVR
(
vector
);
if
(
new_handler
!=
RT_NULL
)
AT91C_AIC_SVR
(
vector
)
=
(
rt_uint32_t
)
new_handler
;
}
if
(
vector
>=
0
&&
vector
<
MAX_HANDLERS
)
{
if
(
*
old_handler
!=
RT_NULL
)
*
old_handler
=
(
rt_isr_handler_t
)
AT91C_AIC_SVR
(
vector
);
if
(
new_handler
!=
RT_NULL
)
AT91C_AIC_SVR
(
vector
)
=
(
rt_uint32_t
)
new_handler
;
}
}
/*@}*/
libcpu/arm/AT91SAM7S/serial.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -22,46 +22,46 @@
typedef
volatile
rt_uint32_t
REG32
;
struct
rt_at91serial_hw
{
REG32
US_CR
;
// Control Register
REG32
US_MR
;
// Mode Register
REG32
US_IER
;
// Interrupt Enable Register
REG32
US_IDR
;
// Interrupt Disable Register
REG32
US_IMR
;
// Interrupt Mask Register
REG32
US_CSR
;
// Channel Status Register
REG32
US_RHR
;
// Receiver Holding Register
REG32
US_THR
;
// Transmitter Holding Register
REG32
US_BRGR
;
// Baud Rate Generator Register
REG32
US_RTOR
;
// Receiver Time-out Register
REG32
US_TTGR
;
// Transmitter Time-guard Register
REG32
Reserved0
[
5
];
//
REG32
US_FIDI
;
// FI_DI_Ratio Register
REG32
US_NER
;
// Nb Errors Register
REG32
Reserved1
[
1
];
//
REG32
US_IF
;
// IRDA_FILTER Register
REG32
Reserved2
[
44
];
//
REG32
US_RPR
;
// Receive Pointer Register
REG32
US_RCR
;
// Receive Counter Register
REG32
US_TPR
;
// Transmit Pointer Register
REG32
US_TCR
;
// Transmit Counter Register
REG32
US_RNPR
;
// Receive Next Pointer Register
REG32
US_RNCR
;
// Receive Next Counter Register
REG32
US_TNPR
;
// Transmit Next Pointer Register
REG32
US_TNCR
;
// Transmit Next Counter Register
REG32
US_PTCR
;
// PDC Transfer Control Register
REG32
US_PTSR
;
// PDC Transfer Status Register
REG32
US_CR
;
// Control Register
REG32
US_MR
;
// Mode Register
REG32
US_IER
;
// Interrupt Enable Register
REG32
US_IDR
;
// Interrupt Disable Register
REG32
US_IMR
;
// Interrupt Mask Register
REG32
US_CSR
;
// Channel Status Register
REG32
US_RHR
;
// Receiver Holding Register
REG32
US_THR
;
// Transmitter Holding Register
REG32
US_BRGR
;
// Baud Rate Generator Register
REG32
US_RTOR
;
// Receiver Time-out Register
REG32
US_TTGR
;
// Transmitter Time-guard Register
REG32
Reserved0
[
5
];
//
REG32
US_FIDI
;
// FI_DI_Ratio Register
REG32
US_NER
;
// Nb Errors Register
REG32
Reserved1
[
1
];
//
REG32
US_IF
;
// IRDA_FILTER Register
REG32
Reserved2
[
44
];
//
REG32
US_RPR
;
// Receive Pointer Register
REG32
US_RCR
;
// Receive Counter Register
REG32
US_TPR
;
// Transmit Pointer Register
REG32
US_TCR
;
// Transmit Counter Register
REG32
US_RNPR
;
// Receive Next Pointer Register
REG32
US_RNCR
;
// Receive Next Counter Register
REG32
US_TNPR
;
// Transmit Next Pointer Register
REG32
US_TNCR
;
// Transmit Next Counter Register
REG32
US_PTCR
;
// PDC Transfer Control Register
REG32
US_PTSR
;
// PDC Transfer Status Register
};
struct
rt_at91serial
{
struct
rt_device
parent
;
struct
rt_device
parent
;
struct
rt_at91serial_hw
*
hw_base
;
rt_uint16_t
peripheral_id
;
rt_uint32_t
baudrate
;
struct
rt_at91serial_hw
*
hw_base
;
rt_uint16_t
peripheral_id
;
rt_uint32_t
baudrate
;
/* reception field */
rt_uint16_t
save_index
,
read_index
;
rt_uint8_t
rx_buffer
[
RT_UART_RX_BUFFER_SIZE
];
/* reception field */
rt_uint16_t
save_index
,
read_index
;
rt_uint8_t
rx_buffer
[
RT_UART_RX_BUFFER_SIZE
];
};
#ifdef RT_USING_UART1
struct
rt_at91serial
serial1
;
...
...
@@ -72,312 +72,312 @@ struct rt_at91serial serial2;
static
void
rt_hw_serial_isr
(
int
irqno
)
{
rt_base_t
level
;
struct
rt_device
*
device
;
struct
rt_at91serial
*
serial
=
RT_NULL
;
rt_base_t
level
;
struct
rt_device
*
device
;
struct
rt_at91serial
*
serial
=
RT_NULL
;
if
(
irqno
==
AT91C_ID_US0
)
{
if
(
irqno
==
AT91C_ID_US0
)
{
#ifdef RT_USING_UART1
/* serial 1 */
serial
=
&
serial1
;
/* serial 1 */
serial
=
&
serial1
;
#endif
}
else
if
(
irqno
==
AT91C_ID_US1
)
{
}
else
if
(
irqno
==
AT91C_ID_US1
)
{
#ifdef RT_USING_UART2
/* serial 2 */
serial
=
&
serial2
;
/* serial 2 */
serial
=
&
serial2
;
#endif
}
RT_ASSERT
(
serial
!=
RT_NULL
);
}
RT_ASSERT
(
serial
!=
RT_NULL
);
/* get generic device object */
device
=
(
rt_device_t
)
serial
;
/* get generic device object */
device
=
(
rt_device_t
)
serial
;
/* disable interrupt */
level
=
rt_hw_interrupt_disable
();
/* disable interrupt */
level
=
rt_hw_interrupt_disable
();
/* get received character */
serial
->
rx_buffer
[
serial
->
save_index
]
=
serial
->
hw_base
->
US_RHR
;
/* get received character */
serial
->
rx_buffer
[
serial
->
save_index
]
=
serial
->
hw_base
->
US_RHR
;
/* move to next position */
serial
->
save_index
++
;
if
(
serial
->
save_index
>=
RT_UART_RX_BUFFER_SIZE
)
serial
->
save_index
=
0
;
/* move to next position */
serial
->
save_index
++
;
if
(
serial
->
save_index
>=
RT_UART_RX_BUFFER_SIZE
)
serial
->
save_index
=
0
;
/* if the next position is read index, discard this 'read char' */
if
(
serial
->
save_index
==
serial
->
read_index
)
{
serial
->
read_index
++
;
if
(
serial
->
read_index
>=
RT_UART_RX_BUFFER_SIZE
)
serial
->
read_index
=
0
;
}
/* if the next position is read index, discard this 'read char' */
if
(
serial
->
save_index
==
serial
->
read_index
)
{
serial
->
read_index
++
;
if
(
serial
->
read_index
>=
RT_UART_RX_BUFFER_SIZE
)
serial
->
read_index
=
0
;
}
/* enable interrupt */
rt_hw_interrupt_enable
(
level
);
/* enable interrupt */
rt_hw_interrupt_enable
(
level
);
/* indicate to upper layer application */
if
(
device
->
rx_indicate
!=
RT_NULL
)
device
->
rx_indicate
(
device
,
1
);
/* indicate to upper layer application */
if
(
device
->
rx_indicate
!=
RT_NULL
)
device
->
rx_indicate
(
device
,
1
);
/* ack interrupt */
AT91C_AIC_EOICR
=
1
;
/* ack interrupt */
AT91C_AIC_EOICR
=
1
;
}
static
rt_err_t
rt_serial_init
(
rt_device_t
dev
)
{
rt_uint32_t
bd
;
struct
rt_at91serial
*
serial
=
(
struct
rt_at91serial
*
)
dev
;
RT_ASSERT
(
serial
!=
RT_NULL
);
/* must be US0 or US1 */
RT_ASSERT
(((
serial
->
peripheral_id
==
AT91C_ID_US0
)
||
(
serial
->
peripheral_id
==
AT91C_ID_US1
)));
/* Enable Clock for USART */
AT91C_PMC_PCER
=
1
<<
serial
->
peripheral_id
;
/* Enable RxD0 and TxDO Pin */
if
(
serial
->
peripheral_id
==
AT91C_ID_US0
)
{
/* set pinmux */
AT91C_PIO_PDR
=
(
1
<<
5
)
|
(
1
<<
6
);
}
else
if
(
serial
->
peripheral_id
==
AT91C_ID_US1
)
{
/* set pinmux */
AT91C_PIO_PDR
=
(
1
<<
21
)
|
(
1
<<
22
);
}
serial
->
hw_base
->
US_CR
=
AT91C_US_RSTRX
|
/* Reset Receiver */
AT91C_US_RSTTX
|
/* Reset Transmitter */
AT91C_US_RXDIS
|
/* Receiver Disable */
AT91C_US_TXDIS
;
/* Transmitter Disable */
serial
->
hw_base
->
US_MR
=
AT91C_US_USMODE_NORMAL
|
/* Normal Mode */
AT91C_US_CLKS_CLOCK
|
/* Clock = MCK */
AT91C_US_CHRL_8_BITS
|
/* 8-bit Data */
AT91C_US_PAR_NONE
|
/* No Parity */
AT91C_US_NBSTOP_1_BIT
;
/* 1 Stop Bit */
/* set baud rate divisor */
bd
=
((
MCK
*
10
)
/
(
serial
->
baudrate
*
16
));
if
((
bd
%
10
)
>=
5
)
bd
=
(
bd
/
10
)
+
1
;
else
bd
/=
10
;
serial
->
hw_base
->
US_BRGR
=
bd
;
serial
->
hw_base
->
US_CR
=
AT91C_US_RXEN
|
/* Receiver Enable */
AT91C_US_TXEN
;
/* Transmitter Enable */
/* reset rx index */
serial
->
save_index
=
0
;
serial
->
read_index
=
0
;
/* reset rx buffer */
rt_memset
(
serial
->
rx_buffer
,
0
,
RT_UART_RX_BUFFER_SIZE
);
return
RT_EOK
;
rt_uint32_t
bd
;
struct
rt_at91serial
*
serial
=
(
struct
rt_at91serial
*
)
dev
;
RT_ASSERT
(
serial
!=
RT_NULL
);
/* must be US0 or US1 */
RT_ASSERT
(((
serial
->
peripheral_id
==
AT91C_ID_US0
)
||
(
serial
->
peripheral_id
==
AT91C_ID_US1
)));
/* Enable Clock for USART */
AT91C_PMC_PCER
=
1
<<
serial
->
peripheral_id
;
/* Enable RxD0 and TxDO Pin */
if
(
serial
->
peripheral_id
==
AT91C_ID_US0
)
{
/* set pinmux */
AT91C_PIO_PDR
=
(
1
<<
5
)
|
(
1
<<
6
);
}
else
if
(
serial
->
peripheral_id
==
AT91C_ID_US1
)
{
/* set pinmux */
AT91C_PIO_PDR
=
(
1
<<
21
)
|
(
1
<<
22
);
}
serial
->
hw_base
->
US_CR
=
AT91C_US_RSTRX
|
/* Reset Receiver */
AT91C_US_RSTTX
|
/* Reset Transmitter */
AT91C_US_RXDIS
|
/* Receiver Disable */
AT91C_US_TXDIS
;
/* Transmitter Disable */
serial
->
hw_base
->
US_MR
=
AT91C_US_USMODE_NORMAL
|
/* Normal Mode */
AT91C_US_CLKS_CLOCK
|
/* Clock = MCK */
AT91C_US_CHRL_8_BITS
|
/* 8-bit Data */
AT91C_US_PAR_NONE
|
/* No Parity */
AT91C_US_NBSTOP_1_BIT
;
/* 1 Stop Bit */
/* set baud rate divisor */
bd
=
((
MCK
*
10
)
/
(
serial
->
baudrate
*
16
));
if
((
bd
%
10
)
>=
5
)
bd
=
(
bd
/
10
)
+
1
;
else
bd
/=
10
;
serial
->
hw_base
->
US_BRGR
=
bd
;
serial
->
hw_base
->
US_CR
=
AT91C_US_RXEN
|
/* Receiver Enable */
AT91C_US_TXEN
;
/* Transmitter Enable */
/* reset rx index */
serial
->
save_index
=
0
;
serial
->
read_index
=
0
;
/* reset rx buffer */
rt_memset
(
serial
->
rx_buffer
,
0
,
RT_UART_RX_BUFFER_SIZE
);
return
RT_EOK
;
}
static
rt_err_t
rt_serial_open
(
rt_device_t
dev
,
rt_uint16_t
oflag
)
{
struct
rt_at91serial
*
serial
=
(
struct
rt_at91serial
*
)
dev
;
RT_ASSERT
(
serial
!=
RT_NULL
);
if
(
dev
->
flag
&
RT_DEVICE_FLAG_INT_RX
)
{
/* enable UART rx interrupt */
serial
->
hw_base
->
US_IER
=
1
<<
0
;
/* RxReady interrupt */
serial
->
hw_base
->
US_IMR
|=
1
<<
0
;
/* umask RxReady interrupt */
/* install UART handler */
rt_hw_interrupt_install
(
serial
->
peripheral_id
,
rt_hw_serial_isr
,
RT_NULL
);
AT91C_AIC_SMR
(
serial
->
peripheral_id
)
=
5
|
(
0x01
<<
5
);
rt_hw_interrupt_umask
(
serial
->
peripheral_id
);
}
return
RT_EOK
;
struct
rt_at91serial
*
serial
=
(
struct
rt_at91serial
*
)
dev
;
RT_ASSERT
(
serial
!=
RT_NULL
);
if
(
dev
->
flag
&
RT_DEVICE_FLAG_INT_RX
)
{
/* enable UART rx interrupt */
serial
->
hw_base
->
US_IER
=
1
<<
0
;
/* RxReady interrupt */
serial
->
hw_base
->
US_IMR
|=
1
<<
0
;
/* umask RxReady interrupt */
/* install UART handler */
rt_hw_interrupt_install
(
serial
->
peripheral_id
,
rt_hw_serial_isr
,
RT_NULL
);
AT91C_AIC_SMR
(
serial
->
peripheral_id
)
=
5
|
(
0x01
<<
5
);
rt_hw_interrupt_umask
(
serial
->
peripheral_id
);
}
return
RT_EOK
;
}
static
rt_err_t
rt_serial_close
(
rt_device_t
dev
)
{
struct
rt_at91serial
*
serial
=
(
struct
rt_at91serial
*
)
dev
;
RT_ASSERT
(
serial
!=
RT_NULL
);
struct
rt_at91serial
*
serial
=
(
struct
rt_at91serial
*
)
dev
;
RT_ASSERT
(
serial
!=
RT_NULL
);
if
(
dev
->
flag
&
RT_DEVICE_FLAG_INT_RX
)
{
/* disable interrupt */
serial
->
hw_base
->
US_IDR
=
1
<<
0
;
/* RxReady interrupt */
serial
->
hw_base
->
US_IMR
&=
~
(
1
<<
0
);
/* mask RxReady interrupt */
}
if
(
dev
->
flag
&
RT_DEVICE_FLAG_INT_RX
)
{
/* disable interrupt */
serial
->
hw_base
->
US_IDR
=
1
<<
0
;
/* RxReady interrupt */
serial
->
hw_base
->
US_IMR
&=
~
(
1
<<
0
);
/* mask RxReady interrupt */
}
return
RT_EOK
;
return
RT_EOK
;
}
static
rt_size_t
rt_serial_read
(
rt_device_t
dev
,
rt_off_t
pos
,
void
*
buffer
,
rt_size_t
size
)
{
rt_uint8_t
*
ptr
;
struct
rt_at91serial
*
serial
=
(
struct
rt_at91serial
*
)
dev
;
RT_ASSERT
(
serial
!=
RT_NULL
);
/* point to buffer */
ptr
=
(
rt_uint8_t
*
)
buffer
;
if
(
dev
->
flag
&
RT_DEVICE_FLAG_INT_RX
)
{
while
(
size
)
{
/* interrupt receive */
rt_base_t
level
;
/* disable interrupt */
level
=
rt_hw_interrupt_disable
();
if
(
serial
->
read_index
!=
serial
->
save_index
)
{
*
ptr
=
serial
->
rx_buffer
[
serial
->
read_index
];
serial
->
read_index
++
;
if
(
serial
->
read_index
>=
RT_UART_RX_BUFFER_SIZE
)
serial
->
read_index
=
0
;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable
(
level
);
break
;
}
/* enable interrupt */
rt_hw_interrupt_enable
(
level
);
ptr
++
;
size
--
;
}
return
(
rt_uint32_t
)
ptr
-
(
rt_uint32_t
)
buffer
;
}
else
if
(
dev
->
flag
&
RT_DEVICE_FLAG_DMA_RX
)
{
/* not support right now */
RT_ASSERT
(
0
);
}
else
{
/* poll mode */
while
(
size
)
{
/* Wait for Full Rx Buffer */
while
(
!
(
serial
->
hw_base
->
US_CSR
&
AT91C_US_RXRDY
));
/* Read Character */
*
ptr
=
serial
->
hw_base
->
US_RHR
;
ptr
++
;
size
--
;
}
return
(
rt_size_t
)
ptr
-
(
rt_size_t
)
buffer
;
}
return
0
;
rt_uint8_t
*
ptr
;
struct
rt_at91serial
*
serial
=
(
struct
rt_at91serial
*
)
dev
;
RT_ASSERT
(
serial
!=
RT_NULL
);
/* point to buffer */
ptr
=
(
rt_uint8_t
*
)
buffer
;
if
(
dev
->
flag
&
RT_DEVICE_FLAG_INT_RX
)
{
while
(
size
)
{
/* interrupt receive */
rt_base_t
level
;
/* disable interrupt */
level
=
rt_hw_interrupt_disable
();
if
(
serial
->
read_index
!=
serial
->
save_index
)
{
*
ptr
=
serial
->
rx_buffer
[
serial
->
read_index
];
serial
->
read_index
++
;
if
(
serial
->
read_index
>=
RT_UART_RX_BUFFER_SIZE
)
serial
->
read_index
=
0
;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable
(
level
);
break
;
}
/* enable interrupt */
rt_hw_interrupt_enable
(
level
);
ptr
++
;
size
--
;
}
return
(
rt_uint32_t
)
ptr
-
(
rt_uint32_t
)
buffer
;
}
else
if
(
dev
->
flag
&
RT_DEVICE_FLAG_DMA_RX
)
{
/* not support right now */
RT_ASSERT
(
0
);
}
else
{
/* poll mode */
while
(
size
)
{
/* Wait for Full Rx Buffer */
while
(
!
(
serial
->
hw_base
->
US_CSR
&
AT91C_US_RXRDY
));
/* Read Character */
*
ptr
=
serial
->
hw_base
->
US_RHR
;
ptr
++
;
size
--
;
}
return
(
rt_size_t
)
ptr
-
(
rt_size_t
)
buffer
;
}
return
0
;
}
static
rt_size_t
rt_serial_write
(
rt_device_t
dev
,
rt_off_t
pos
,
const
void
*
buffer
,
rt_size_t
size
)
{
rt_uint8_t
*
ptr
;
struct
rt_at91serial
*
serial
=
(
struct
rt_at91serial
*
)
dev
;
RT_ASSERT
(
serial
!=
RT_NULL
);
ptr
=
(
rt_uint8_t
*
)
buffer
;
if
(
dev
->
open_flag
&
RT_DEVICE_OFLAG_WRONLY
)
{
if
(
dev
->
flag
&
RT_DEVICE_FLAG_STREAM
)
{
/* it's a stream mode device */
while
(
size
)
{
/* stream mode */
if
(
*
ptr
==
'\n'
)
{
while
(
!
(
serial
->
hw_base
->
US_CSR
&
AT91C_US_TXRDY
));
serial
->
hw_base
->
US_THR
=
'\r'
;
}
/* Wait for Empty Tx Buffer */
while
(
!
(
serial
->
hw_base
->
US_CSR
&
AT91C_US_TXRDY
));
/* Transmit Character */
serial
->
hw_base
->
US_THR
=
*
ptr
;
ptr
++
;
size
--
;
}
}
else
{
while
(
size
)
{
/* Wait for Empty Tx Buffer */
while
(
!
(
serial
->
hw_base
->
US_CSR
&
AT91C_US_TXRDY
));
/* Transmit Character */
serial
->
hw_base
->
US_THR
=
*
ptr
;
ptr
++
;
size
--
;
}
}
}
return
(
rt_size_t
)
ptr
-
(
rt_size_t
)
buffer
;
rt_uint8_t
*
ptr
;
struct
rt_at91serial
*
serial
=
(
struct
rt_at91serial
*
)
dev
;
RT_ASSERT
(
serial
!=
RT_NULL
);
ptr
=
(
rt_uint8_t
*
)
buffer
;
if
(
dev
->
open_flag
&
RT_DEVICE_OFLAG_WRONLY
)
{
if
(
dev
->
flag
&
RT_DEVICE_FLAG_STREAM
)
{
/* it's a stream mode device */
while
(
size
)
{
/* stream mode */
if
(
*
ptr
==
'\n'
)
{
while
(
!
(
serial
->
hw_base
->
US_CSR
&
AT91C_US_TXRDY
));
serial
->
hw_base
->
US_THR
=
'\r'
;
}
/* Wait for Empty Tx Buffer */
while
(
!
(
serial
->
hw_base
->
US_CSR
&
AT91C_US_TXRDY
));
/* Transmit Character */
serial
->
hw_base
->
US_THR
=
*
ptr
;
ptr
++
;
size
--
;
}
}
else
{
while
(
size
)
{
/* Wait for Empty Tx Buffer */
while
(
!
(
serial
->
hw_base
->
US_CSR
&
AT91C_US_TXRDY
));
/* Transmit Character */
serial
->
hw_base
->
US_THR
=
*
ptr
;
ptr
++
;
size
--
;
}
}
}
return
(
rt_size_t
)
ptr
-
(
rt_size_t
)
buffer
;
}
static
rt_err_t
rt_serial_control
(
rt_device_t
dev
,
int
cmd
,
void
*
args
)
{
return
RT_EOK
;
return
RT_EOK
;
}
rt_err_t
rt_hw_serial_init
()
{
rt_device_t
device
;
rt_device_t
device
;
#ifdef RT_USING_UART1
device
=
(
rt_device_t
)
&
serial1
;
/* init serial device private data */
serial1
.
hw_base
=
(
struct
rt_at91serial_hw
*
)
AT91C_BASE_US0
;
serial1
.
peripheral_id
=
AT91C_ID_US0
;
serial1
.
baudrate
=
115200
;
/* set device virtual interface */
device
->
init
=
rt_serial_init
;
device
->
open
=
rt_serial_open
;
device
->
close
=
rt_serial_close
;
device
->
read
=
rt_serial_read
;
device
->
write
=
rt_serial_write
;
device
->
control
=
rt_serial_control
;
/* register uart1 on device subsystem */
rt_device_register
(
device
,
"uart1"
,
RT_DEVICE_FLAG_RDWR
|
RT_DEVICE_FLAG_INT_RX
);
device
=
(
rt_device_t
)
&
serial1
;
/* init serial device private data */
serial1
.
hw_base
=
(
struct
rt_at91serial_hw
*
)
AT91C_BASE_US0
;
serial1
.
peripheral_id
=
AT91C_ID_US0
;
serial1
.
baudrate
=
115200
;
/* set device virtual interface */
device
->
init
=
rt_serial_init
;
device
->
open
=
rt_serial_open
;
device
->
close
=
rt_serial_close
;
device
->
read
=
rt_serial_read
;
device
->
write
=
rt_serial_write
;
device
->
control
=
rt_serial_control
;
/* register uart1 on device subsystem */
rt_device_register
(
device
,
"uart1"
,
RT_DEVICE_FLAG_RDWR
|
RT_DEVICE_FLAG_INT_RX
);
#endif
#ifdef RT_USING_UART2
device
=
(
rt_device_t
)
&
serial2
;
serial2
.
hw_base
=
(
struct
rt_at91serial_hw
*
)
AT91C_BASE_US1
;
serial2
.
peripheral_id
=
AT91C_ID_US1
;
serial2
.
baudrate
=
115200
;
/* set device virtual interface */
device
->
init
=
rt_serial_init
;
device
->
open
=
rt_serial_open
;
device
->
close
=
rt_serial_close
;
device
->
read
=
rt_serial_read
;
device
->
write
=
rt_serial_write
;
device
->
control
=
rt_serial_control
;
/* register uart2 on device subsystem */
rt_device_register
(
device
,
"uart2"
,
RT_DEVICE_FLAG_RDWR
|
RT_DEVICE_FLAG_INT_RX
);
device
=
(
rt_device_t
)
&
serial2
;
serial2
.
hw_base
=
(
struct
rt_at91serial_hw
*
)
AT91C_BASE_US1
;
serial2
.
peripheral_id
=
AT91C_ID_US1
;
serial2
.
baudrate
=
115200
;
/* set device virtual interface */
device
->
init
=
rt_serial_init
;
device
->
open
=
rt_serial_open
;
device
->
close
=
rt_serial_close
;
device
->
read
=
rt_serial_read
;
device
->
write
=
rt_serial_write
;
device
->
control
=
rt_serial_control
;
/* register uart2 on device subsystem */
rt_device_register
(
device
,
"uart2"
,
RT_DEVICE_FLAG_RDWR
|
RT_DEVICE_FLAG_INT_RX
);
#endif
return
RT_EOK
;
return
RT_EOK
;
}
/*@}*/
libcpu/arm/AT91SAM7S/serial.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -17,48 +17,48 @@
#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
#endif
#define AT91C_US_RXRDY
((unsigned int) 0x1 << 0)
/* US RXRDY Interrupt */
#define AT91C_US_TXRDY
((unsigned int) 0x1 << 1)
/* US TXRDY Interrupt */
#define AT91C_US_RSTRX
((unsigned int) 0x1 << 2)
/* US Reset Receiver */
#define AT91C_US_RSTTX
((unsigned int) 0x1 << 3)
/* US Reset Transmitter */
#define AT91C_US_RXEN
((unsigned int) 0x1 << 4)
/* US Receiver Enable */
#define AT91C_US_RXDIS
((unsigned int) 0x1 << 5)
/* US Receiver Disable */
#define AT91C_US_TXEN
((unsigned int) 0x1 << 6)
/* US Transmitter Enable */
#define AT91C_US_TXDIS
((unsigned int) 0x1 << 7)
/* US Transmitter Disable */
#define AT91C_US_RSTSTA
((unsigned int) 0x1 << 8)
/* US Reset Status Bits */
#define AT91C_US_RXRDY
((unsigned int) 0x1 << 0)
/* US RXRDY Interrupt */
#define AT91C_US_TXRDY
((unsigned int) 0x1 << 1)
/* US TXRDY Interrupt */
#define AT91C_US_RSTRX
((unsigned int) 0x1 << 2)
/* US Reset Receiver */
#define AT91C_US_RSTTX
((unsigned int) 0x1 << 3)
/* US Reset Transmitter */
#define AT91C_US_RXEN
((unsigned int) 0x1 << 4)
/* US Receiver Enable */
#define AT91C_US_RXDIS
((unsigned int) 0x1 << 5)
/* US Receiver Disable */
#define AT91C_US_TXEN
((unsigned int) 0x1 << 6)
/* US Transmitter Enable */
#define AT91C_US_TXDIS
((unsigned int) 0x1 << 7)
/* US Transmitter Disable */
#define AT91C_US_RSTSTA
((unsigned int) 0x1 << 8)
/* US Reset Status Bits */
#define AT91C_US_USMODE_NORMAL
((unsigned int) 0x0)
/* USAR) Normal */
#define AT91C_US_USMODE_RS485
((unsigned int) 0x1)
/* USAR) RS485 */
#define AT91C_US_USMODE_HWHSH
((unsigned int) 0x2)
/* USAR) Hardware Handshaking */
#define AT91C_US_USMODE_MODEM
((unsigned int) 0x3)
/* USAR) Modem */
#define AT91C_US_USMODE_ISO7816_0
((unsigned int) 0x4)
/* USAR) ISO7816 protocol: T = 0 */
#define AT91C_US_USMODE_ISO7816_1
((unsigned int) 0x6)
/* USAR) ISO7816 protocol: T = 1 */
#define AT91C_US_USMODE_IRDA
((unsigned int) 0x8)
/* USAR) IrDA */
#define AT91C_US_USMODE_SWHSH
((unsigned int) 0xC)
/* USAR) Software Handshaking */
#define AT91C_US_USMODE_NORMAL
((unsigned int) 0x0)
/* USAR) Normal */
#define AT91C_US_USMODE_RS485
((unsigned int) 0x1)
/* USAR) RS485 */
#define AT91C_US_USMODE_HWHSH
((unsigned int) 0x2)
/* USAR) Hardware Handshaking */
#define AT91C_US_USMODE_MODEM
((unsigned int) 0x3)
/* USAR) Modem */
#define AT91C_US_USMODE_ISO7816_0
((unsigned int) 0x4)
/* USAR) ISO7816 protocol: T = 0 */
#define AT91C_US_USMODE_ISO7816_1
((unsigned int) 0x6)
/* USAR) ISO7816 protocol: T = 1 */
#define AT91C_US_USMODE_IRDA
((unsigned int) 0x8)
/* USAR) IrDA */
#define AT91C_US_USMODE_SWHSH
((unsigned int) 0xC)
/* USAR) Software Handshaking */
#define AT91C_US_CLKS_CLOCK
((unsigned int) 0x0 << 4)
/* USAR) Clock */
#define AT91C_US_CLKS_FDIV1
((unsigned int) 0x1 << 4)
/* USAR) fdiv1 */
#define AT91C_US_CLKS_SLOW
((unsigned int) 0x2 << 4)
/* USAR) slow_clock (ARM) */
#define AT91C_US_CLKS_EXT
((unsigned int) 0x3 << 4)
/* USAR) External (SCK) */
#define AT91C_US_CLKS_CLOCK
((unsigned int) 0x0 << 4)
/* USAR) Clock */
#define AT91C_US_CLKS_FDIV1
((unsigned int) 0x1 << 4)
/* USAR) fdiv1 */
#define AT91C_US_CLKS_SLOW
((unsigned int) 0x2 << 4)
/* USAR) slow_clock (ARM) */
#define AT91C_US_CLKS_EXT
((unsigned int) 0x3 << 4)
/* USAR) External (SCK) */
#define AT91C_US_CHRL_5_BITS
((unsigned int) 0x0 << 6)
/* USAR) Character Length: 5 bits */
#define AT91C_US_CHRL_6_BITS
((unsigned int) 0x1 << 6)
/* USAR) Character Length: 6 bits */
#define AT91C_US_CHRL_7_BITS
((unsigned int) 0x2 << 6)
/* USAR) Character Length: 7 bits */
#define AT91C_US_CHRL_8_BITS
((unsigned int) 0x3 << 6)
/* USAR) Character Length: 8 bits */
#define AT91C_US_CHRL_5_BITS
((unsigned int) 0x0 << 6)
/* USAR) Character Length: 5 bits */
#define AT91C_US_CHRL_6_BITS
((unsigned int) 0x1 << 6)
/* USAR) Character Length: 6 bits */
#define AT91C_US_CHRL_7_BITS
((unsigned int) 0x2 << 6)
/* USAR) Character Length: 7 bits */
#define AT91C_US_CHRL_8_BITS
((unsigned int) 0x3 << 6)
/* USAR) Character Length: 8 bits */
#define AT91C_US_PAR_EVEN
((unsigned int) 0x0 << 9)
/* DBGU Even Parity */
#define AT91C_US_PAR_ODD
((unsigned int) 0x1 << 9)
/* DBGU Odd Parity */
#define AT91C_US_PAR_SPACE
((unsigned int) 0x2 << 9)
/* DBGU Parity forced to 0 (Space) */
#define AT91C_US_PAR_MARK
((unsigned int) 0x3 << 9)
/* DBGU Parity forced to 1 (Mark) */
#define AT91C_US_PAR_NONE
((unsigned int) 0x4 << 9)
/* DBGU No Parity */
#define AT91C_US_PAR_MULTI_DROP
((unsigned int) 0x6 << 9)
/* DBGU Multi-drop mode */
#define AT91C_US_PAR_EVEN
((unsigned int) 0x0 << 9)
/* DBGU Even Parity */
#define AT91C_US_PAR_ODD
((unsigned int) 0x1 << 9)
/* DBGU Odd Parity */
#define AT91C_US_PAR_SPACE
((unsigned int) 0x2 << 9)
/* DBGU Parity forced to 0 (Space) */
#define AT91C_US_PAR_MARK
((unsigned int) 0x3 << 9)
/* DBGU Parity forced to 1 (Mark) */
#define AT91C_US_PAR_NONE
((unsigned int) 0x4 << 9)
/* DBGU No Parity */
#define AT91C_US_PAR_MULTI_DROP
((unsigned int) 0x6 << 9)
/* DBGU Multi-drop mode */
#define AT91C_US_NBSTOP_1_BIT
((unsigned int) 0x0 << 12)
/* USART 1 stop bit */
#define AT91C_US_NBSTOP_15_BIT
((unsigned int) 0x1 << 12)
/* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
#define AT91C_US_NBSTOP_2_BIT
((unsigned int) 0x2 << 12)
/* USART 2 stop bits */
#define AT91C_US_NBSTOP_1_BIT
((unsigned int) 0x0 << 12)
/* USART 1 stop bit */
#define AT91C_US_NBSTOP_15_BIT
((unsigned int) 0x1 << 12)
/* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
#define AT91C_US_NBSTOP_2_BIT
((unsigned int) 0x2 << 12)
/* USART 2 stop bits */
#define MCK
48054857
#define BR
115200
/* Baud Rate */
#define BRD
(MCK/16/BR)
/* Baud Rate Divisor */
#define MCK
48054857
#define BR
115200
/* Baud Rate */
#define BRD
(MCK/16/BR)
/* Baud Rate Divisor */
#endif
libcpu/arm/AT91SAM7S/stack.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/AT91SAM7S/trap.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -20,12 +20,12 @@
void
rt_hw_trap_irq
()
{
rt_isr_handler_t
hander
=
(
rt_isr_handler_t
)
AT91C_AIC_IVR
;
rt_isr_handler_t
hander
=
(
rt_isr_handler_t
)
AT91C_AIC_IVR
;
hander
(
AT91C_AIC_ISR
);
hander
(
AT91C_AIC_ISR
);
/* end of interrupt */
AT91C_AIC_EOICR
=
0
;
/* end of interrupt */
AT91C_AIC_EOICR
=
0
;
}
void
rt_hw_trap_fiq
()
...
...
libcpu/arm/AT91SAM7X/cpu.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset()
*/
RT_WEAK
void
rt_hw_cpu_shutdown
()
{
rt_kprintf
(
"shutdown...
\n
"
);
rt_kprintf
(
"shutdown...
\n
"
);
while
(
1
);
while
(
1
);
}
/*@}*/
libcpu/arm/AT91SAM7X/interrupt.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -13,10 +13,10 @@
#include <rthw.h>
#include "AT91SAM7X256.h"
#define MAX_HANDLERS
32
#define MAX_HANDLERS
32
/* exception and interrupt handler table */
struct
rt_irq_desc
irq_desc
[
MAX_HANDLERS
];
struct
rt_irq_desc
irq_desc
[
MAX_HANDLERS
];
extern
rt_uint32_t
rt_interrupt_nest
;
...
...
@@ -30,7 +30,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
static
void
rt_hw_interrupt_handler
(
int
vector
,
void
*
param
)
{
rt_kprintf
(
"Unhandled interrupt %d occured!!!
\n
"
,
vector
);
rt_kprintf
(
"Unhandled interrupt %d occured!!!
\n
"
,
vector
);
}
/**
...
...
@@ -38,7 +38,7 @@ static void rt_hw_interrupt_handler(int vector, void *param)
*/
void
rt_hw_interrupt_init
(
void
)
{
rt_base_t
index
;
rt_base_t
index
;
/* init exceptions table */
for
(
index
=
0
;
index
<
MAX_HANDLERS
;
index
++
)
...
...
@@ -47,16 +47,16 @@ void rt_hw_interrupt_init(void)
irq_desc
[
index
].
param
=
RT_NULL
;
}
for
(
index
=
0
;
index
<
MAX_HANDLERS
;
index
++
)
{
AT91C_BASE_AIC
->
AIC_SVR
[
index
]
=
(
rt_uint32_t
)
rt_hw_interrupt_handler
;
}
for
(
index
=
0
;
index
<
MAX_HANDLERS
;
index
++
)
{
AT91C_BASE_AIC
->
AIC_SVR
[
index
]
=
(
rt_uint32_t
)
rt_hw_interrupt_handler
;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest
=
0
;
rt_interrupt_from_thread
=
0
;
rt_interrupt_to_thread
=
0
;
rt_thread_switch_interrupt_flag
=
0
;
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest
=
0
;
rt_interrupt_from_thread
=
0
;
rt_interrupt_to_thread
=
0
;
rt_thread_switch_interrupt_flag
=
0
;
}
/**
...
...
@@ -65,11 +65,11 @@ void rt_hw_interrupt_init(void)
*/
void
rt_hw_interrupt_mask
(
int
vector
)
{
/* disable interrupt */
AT91C_BASE_AIC
->
AIC_IDCR
=
1
<<
vector
;
/* disable interrupt */
AT91C_BASE_AIC
->
AIC_IDCR
=
1
<<
vector
;
/* clear interrupt */
AT91C_BASE_AIC
->
AIC_ICCR
=
1
<<
vector
;
/* clear interrupt */
AT91C_BASE_AIC
->
AIC_ICCR
=
1
<<
vector
;
}
/**
...
...
@@ -78,7 +78,7 @@ void rt_hw_interrupt_mask(int vector)
*/
void
rt_hw_interrupt_umask
(
int
vector
)
{
AT91C_BASE_AIC
->
AIC_IECR
=
1
<<
vector
;
AT91C_BASE_AIC
->
AIC_IECR
=
1
<<
vector
;
}
/**
...
...
@@ -90,21 +90,21 @@ void rt_hw_interrupt_umask(int vector)
*
* @return the old handler
*/
rt_isr_handler_t
rt_hw_interrupt_install
(
int
vector
,
rt_isr_handler_t
handler
,
void
*
param
,
const
char
*
name
)
rt_isr_handler_t
rt_hw_interrupt_install
(
int
vector
,
rt_isr_handler_t
handler
,
void
*
param
,
const
char
*
name
)
{
rt_isr_handler_t
old_handler
=
RT_NULL
;
if
(
vector
>=
0
&&
vector
<
MAX_HANDLERS
)
{
old_handler
=
irq_desc
[
vector
].
handler
;
if
(
handler
!=
RT_NULL
)
{
irq_desc
[
vector
].
handler
=
(
rt_isr_handler_t
)
handler
;
irq_desc
[
vector
].
param
=
param
;
}
}
return
old_handler
;
rt_isr_handler_t
old_handler
=
RT_NULL
;
if
(
vector
>=
0
&&
vector
<
MAX_HANDLERS
)
{
old_handler
=
irq_desc
[
vector
].
handler
;
if
(
handler
!=
RT_NULL
)
{
irq_desc
[
vector
].
handler
=
(
rt_isr_handler_t
)
handler
;
irq_desc
[
vector
].
param
=
param
;
}
}
return
old_handler
;
}
/*@}*/
libcpu/arm/AT91SAM7X/stack.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/AT91SAM7X/trap.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -20,17 +20,17 @@
void
rt_hw_trap_irq
(
void
)
{
int
irqno
;
extern
struct
rt_irq_desc
irq_desc
[];
int
irqno
;
extern
struct
rt_irq_desc
irq_desc
[];
/* get interrupt number */
irqno
=
AT91C_BASE_AIC
->
AIC_ISR
;
/* get interrupt number */
irqno
=
AT91C_BASE_AIC
->
AIC_ISR
;
/* invoke isr with parameters */
irq_desc
[
irqno
].
handler
(
irqno
,
irq_desc
[
irqno
].
param
);
/* invoke isr with parameters */
irq_desc
[
irqno
].
handler
(
irqno
,
irq_desc
[
irqno
].
param
);
/* end of interrupt */
AT91C_BASE_AIC
->
AIC_EOICR
=
0
;
/* end of interrupt */
AT91C_BASE_AIC
->
AIC_EOICR
=
0
;
}
void
rt_hw_trap_fiq
(
void
)
...
...
@@ -41,9 +41,9 @@ void rt_hw_trap_fiq(void)
extern
struct
rt_thread
*
rt_current_thread
;
void
rt_hw_trap_abort
(
void
)
{
rt_kprintf
(
"Abort occured!!! Thread [%s] suspended.
\n
"
,
rt_current_thread
->
name
);
rt_thread_suspend
(
rt_current_thread
);
rt_schedule
();
rt_kprintf
(
"Abort occured!!! Thread [%s] suspended.
\n
"
,
rt_current_thread
->
name
);
rt_thread_suspend
(
rt_current_thread
);
rt_schedule
();
}
/*@}*/
libcpu/arm/am335x/am33xx.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -9,8 +9,8 @@
#ifndef __AM33XX_H__
#define __AM33XX_H__
#define REG32(x)
(*((volatile unsigned int *)(x)))
#define REG16(x)
(*((volatile unsigned short *)(x)))
#define REG32(x)
(*((volatile unsigned int *)(x)))
#define REG16(x)
(*((volatile unsigned short *)(x)))
/** Cache Line size in ARM Cortex-A8. */
#define AM33XX_CACHELINE_SIZE (64)
...
...
@@ -198,22 +198,22 @@
#define CM_DPLL_CLKSEL_TIMER2_CLK(base) REG32(CM_DPLL(base) + 0x8)
/* timer registers */
#define DMTIMER_TIDR(base)
REG32(base + 0x0)
#define DMTIMER_TIOCP_CFG(base)
REG32(base + 0x10)
#define DMTIMER_IRQ_EOI(base)
REG32(base + 0x20)
#define DMTIMER_IRQSTATUS_RAW(base)
REG32(base + 0x24)
#define DMTIMER_IRQSTATUS(base)
REG32(base + 0x28)
#define DMTIMER_IRQENABLE_SET(base)
REG32(base + 0x2C)
#define DMTIMER_IRQENABLE_CLR(base)
REG32(base + 0x30)
#define DMTIMER_IRQWAKEEN(base)
REG32(base + 0x34)
#define DMTIMER_TCLR(base)
REG32(base + 0x38)
#define DMTIMER_TCRR(base)
REG32(base + 0x3C)
#define DMTIMER_TLDR(base)
REG32(base + 0x40)
#define DMTIMER_TTGR(base)
REG32(base + 0x44)
#define DMTIMER_TWPS(base)
REG32(base + 0x48)
#define DMTIMER_TMAR(base)
REG32(base + 0x4C)
#define DMTIMER_TCAR(base, n)
REG32(base + 0x50 + (((n) - 1) * 8))
#define DMTIMER_TSICR(base)
REG32(base + 0x54)
#define DMTIMER_TIDR(base)
REG32(base + 0x0)
#define DMTIMER_TIOCP_CFG(base)
REG32(base + 0x10)
#define DMTIMER_IRQ_EOI(base)
REG32(base + 0x20)
#define DMTIMER_IRQSTATUS_RAW(base)
REG32(base + 0x24)
#define DMTIMER_IRQSTATUS(base)
REG32(base + 0x28)
#define DMTIMER_IRQENABLE_SET(base)
REG32(base + 0x2C)
#define DMTIMER_IRQENABLE_CLR(base)
REG32(base + 0x30)
#define DMTIMER_IRQWAKEEN(base)
REG32(base + 0x34)
#define DMTIMER_TCLR(base)
REG32(base + 0x38)
#define DMTIMER_TCRR(base)
REG32(base + 0x3C)
#define DMTIMER_TLDR(base)
REG32(base + 0x40)
#define DMTIMER_TTGR(base)
REG32(base + 0x44)
#define DMTIMER_TWPS(base)
REG32(base + 0x48)
#define DMTIMER_TMAR(base)
REG32(base + 0x4C)
#define DMTIMER_TCAR(base, n)
REG32(base + 0x50 + (((n) - 1) * 8))
#define DMTIMER_TSICR(base)
REG32(base + 0x54)
#define EMU_INT 0
#define COMMTX_INT 1
...
...
@@ -317,33 +317,33 @@
struct
rt_hw_register
{
unsigned
long
r0
;
unsigned
long
r1
;
unsigned
long
r2
;
unsigned
long
r3
;
unsigned
long
r4
;
unsigned
long
r5
;
unsigned
long
r6
;
unsigned
long
r7
;
unsigned
long
r8
;
unsigned
long
r9
;
unsigned
long
r10
;
unsigned
long
fp
;
unsigned
long
ip
;
unsigned
long
sp
;
unsigned
long
lr
;
unsigned
long
pc
;
unsigned
long
cpsr
;
unsigned
long
ORIG_r0
;
unsigned
long
r0
;
unsigned
long
r1
;
unsigned
long
r2
;
unsigned
long
r3
;
unsigned
long
r4
;
unsigned
long
r5
;
unsigned
long
r6
;
unsigned
long
r7
;
unsigned
long
r8
;
unsigned
long
r9
;
unsigned
long
r10
;
unsigned
long
fp
;
unsigned
long
ip
;
unsigned
long
sp
;
unsigned
long
lr
;
unsigned
long
pc
;
unsigned
long
cpsr
;
unsigned
long
ORIG_r0
;
};
#define USERMODE
0x10
#define FIQMODE
0x11
#define IRQMODE
0x12
#define SVCMODE
0x13
#define ABORTMODE
0x17
#define UNDEFMODE
0x1b
#define MODEMASK
0x1f
#define NOINT
0xc0
#define USERMODE
0x10
#define FIQMODE
0x11
#define IRQMODE
0x12
#define SVCMODE
0x13
#define ABORTMODE
0x17
#define UNDEFMODE
0x1b
#define MODEMASK
0x1f
#define NOINT
0xc0
#endif
libcpu/arm/am335x/cpu.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -17,74 +17,74 @@
*/
/*@{*/
#define ICACHE_MASK
(rt_uint32_t)(1 << 12)
#define DCACHE_MASK
(rt_uint32_t)(1 << 2)
#define ICACHE_MASK
(rt_uint32_t)(1 << 12)
#define DCACHE_MASK
(rt_uint32_t)(1 << 2)
#if defined(__CC_ARM)
rt_inline
rt_uint32_t
cp15_rd
(
void
)
{
rt_uint32_t
i
;
rt_uint32_t
i
;
__asm
{
mrc
p15
,
0
,
i
,
c1
,
c0
,
0
}
__asm
{
mrc
p15
,
0
,
i
,
c1
,
c0
,
0
}
return
i
;
return
i
;
}
rt_inline
void
cache_enable
(
rt_uint32_t
bit
)
{
rt_uint32_t
value
;
__asm
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
orr
value
,
value
,
bit
mcr
p15
,
0
,
value
,
c1
,
c0
,
0
}
rt_uint32_t
value
;
__asm
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
orr
value
,
value
,
bit
mcr
p15
,
0
,
value
,
c1
,
c0
,
0
}
}
rt_inline
void
cache_disable
(
rt_uint32_t
bit
)
{
rt_uint32_t
value
;
__asm
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
bic
value
,
value
,
bit
mcr
p15
,
0
,
value
,
c1
,
c0
,
0
}
rt_uint32_t
value
;
__asm
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
bic
value
,
value
,
bit
mcr
p15
,
0
,
value
,
c1
,
c0
,
0
}
}
#elif defined(__GNUC__)
rt_inline
rt_uint32_t
cp15_rd
(
void
)
{
rt_uint32_t
i
;
rt_uint32_t
i
;
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
return
i
;
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
return
i
;
}
rt_inline
void
cache_enable
(
rt_uint32_t
bit
)
{
__asm__
__volatile__
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"orr r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
:
\
:
"r"
(
bit
)
\
:
"memory"
);
__asm__
__volatile__
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"orr r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
:
\
:
"r"
(
bit
)
\
:
"memory"
);
}
rt_inline
void
cache_disable
(
rt_uint32_t
bit
)
{
__asm__
__volatile__
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"bic r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
:
\
:
"r"
(
bit
)
\
:
"memory"
);
__asm__
__volatile__
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"bic r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
:
\
:
"r"
(
bit
)
\
:
"memory"
);
}
#endif
...
...
@@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
*/
void
rt_hw_cpu_icache_enable
()
{
cache_enable
(
ICACHE_MASK
);
cache_enable
(
ICACHE_MASK
);
}
/**
...
...
@@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable()
*/
void
rt_hw_cpu_icache_disable
()
{
cache_disable
(
ICACHE_MASK
);
cache_disable
(
ICACHE_MASK
);
}
/**
...
...
@@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable()
*/
rt_base_t
rt_hw_cpu_icache_status
()
{
return
(
cp15_rd
()
&
ICACHE_MASK
);
return
(
cp15_rd
()
&
ICACHE_MASK
);
}
/**
...
...
@@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status()
*/
void
rt_hw_cpu_dcache_enable
()
{
cache_enable
(
DCACHE_MASK
);
cache_enable
(
DCACHE_MASK
);
}
/**
...
...
@@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable()
*/
void
rt_hw_cpu_dcache_disable
()
{
cache_disable
(
DCACHE_MASK
);
cache_disable
(
DCACHE_MASK
);
}
/**
...
...
@@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable()
*/
rt_base_t
rt_hw_cpu_dcache_status
()
{
return
(
cp15_rd
()
&
DCACHE_MASK
);
return
(
cp15_rd
()
&
DCACHE_MASK
);
}
#endif
...
...
@@ -151,14 +151,14 @@ rt_base_t rt_hw_cpu_dcache_status()
*/
RT_WEAK
void
rt_hw_cpu_shutdown
()
{
rt_uint32_t
level
;
rt_kprintf
(
"shutdown...
\n
"
);
level
=
rt_hw_interrupt_disable
();
while
(
level
)
{
RT_ASSERT
(
0
);
}
rt_uint32_t
level
;
rt_kprintf
(
"shutdown...
\n
"
);
level
=
rt_hw_interrupt_disable
();
while
(
level
)
{
RT_ASSERT
(
0
);
}
}
/*@}*/
libcpu/arm/am335x/interrupt.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -17,7 +17,7 @@
#define AINTC_BASE AM33XX_AINTC_REGS
#define MAX_HANDLERS
128
#define MAX_HANDLERS
128
extern
volatile
rt_uint8_t
rt_interrupt_nest
;
...
...
@@ -59,13 +59,13 @@ extern int system_vectors;
static
void
rt_hw_vector_init
(
void
)
{
unsigned
int
*
dest
=
(
unsigned
int
*
)
AM335X_VECTOR_BASE
;
#ifdef __ICCARM__
unsigned
int
*
src
=
(
unsigned
int
*
)
&
__vector
;
#else
unsigned
int
*
src
=
(
unsigned
int
*
)
&
system_vectors
;
#endif
rt_memcpy
(
dest
,
src
,
16
*
4
);
rt_cpu_vector_set_base
(
AM335X_VECTOR_BASE
);
}
...
...
libcpu/arm/am335x/interrupt.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -14,28 +14,28 @@
#define INT_IRQ 0x00
#define INT_FIQ 0x01
#define INTC_REVISION(hw_base)
REG32((hw_base) + 0x0)
#define INTC_SYSCONFIG(hw_base)
REG32((hw_base) + 0x10)
#define INTC_SYSSTATUS(hw_base)
REG32((hw_base) + 0x14)
#define INTC_SIR_IRQ(hw_base)
REG32((hw_base) + 0x40)
#define INTC_SIR_FIQ(hw_base)
REG32((hw_base) + 0x44)
#define INTC_CONTROL(hw_base)
REG32((hw_base) + 0x48)
#define INTC_PROTECTION(hw_base)
REG32((hw_base) + 0x4c)
#define INTC_IDLE(hw_base)
REG32((hw_base) + 0x50)
#define INTC_IRQ_PRIORITY(hw_base)
REG32((hw_base) + 0x60)
#define INTC_FIQ_PRIORITY(hw_base)
REG32((hw_base) + 0x64)
#define INTC_THRESHOLD(hw_base)
REG32((hw_base) + 0x68)
#define INTC_SICR(hw_base)
REG32((hw_base) + 0x6c)
#define INTC_SCR(hw_base, n)
REG32((hw_base) + 0x70 + ((n) * 0x04))
#define INTC_ITR(hw_base, n)
REG32((hw_base) + 0x80 + ((n) * 0x20))
#define INTC_MIR(hw_base, n)
REG32((hw_base) + 0x84 + ((n) * 0x20))
#define INTC_MIR_CLEAR(hw_base, n)
REG32((hw_base) + 0x88 + ((n) * 0x20))
#define INTC_MIR_SET(hw_base, n)
REG32((hw_base) + 0x8c + ((n) * 0x20))
#define INTC_ISR_SET(hw_base, n)
REG32((hw_base) + 0x90 + ((n) * 0x20))
#define INTC_ISR_CLEAR(hw_base, n)
REG32((hw_base) + 0x94 + ((n) * 0x20))
#define INTC_REVISION(hw_base)
REG32((hw_base) + 0x0)
#define INTC_SYSCONFIG(hw_base)
REG32((hw_base) + 0x10)
#define INTC_SYSSTATUS(hw_base)
REG32((hw_base) + 0x14)
#define INTC_SIR_IRQ(hw_base)
REG32((hw_base) + 0x40)
#define INTC_SIR_FIQ(hw_base)
REG32((hw_base) + 0x44)
#define INTC_CONTROL(hw_base)
REG32((hw_base) + 0x48)
#define INTC_PROTECTION(hw_base)
REG32((hw_base) + 0x4c)
#define INTC_IDLE(hw_base)
REG32((hw_base) + 0x50)
#define INTC_IRQ_PRIORITY(hw_base)
REG32((hw_base) + 0x60)
#define INTC_FIQ_PRIORITY(hw_base)
REG32((hw_base) + 0x64)
#define INTC_THRESHOLD(hw_base)
REG32((hw_base) + 0x68)
#define INTC_SICR(hw_base)
REG32((hw_base) + 0x6c)
#define INTC_SCR(hw_base, n)
REG32((hw_base) + 0x70 + ((n) * 0x04))
#define INTC_ITR(hw_base, n)
REG32((hw_base) + 0x80 + ((n) * 0x20))
#define INTC_MIR(hw_base, n)
REG32((hw_base) + 0x84 + ((n) * 0x20))
#define INTC_MIR_CLEAR(hw_base, n)
REG32((hw_base) + 0x88 + ((n) * 0x20))
#define INTC_MIR_SET(hw_base, n)
REG32((hw_base) + 0x8c + ((n) * 0x20))
#define INTC_ISR_SET(hw_base, n)
REG32((hw_base) + 0x90 + ((n) * 0x20))
#define INTC_ISR_CLEAR(hw_base, n)
REG32((hw_base) + 0x94 + ((n) * 0x20))
#define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20))
#define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20))
#define INTC_ILR(hw_base, n)
REG32((hw_base) + 0x100 + ((n) * 0x04))
#define INTC_ILR(hw_base, n)
REG32((hw_base) + 0x100 + ((n) * 0x04))
void
rt_hw_interrupt_control
(
int
vector
,
int
priority
,
int
route
);
int
rt_hw_interrupt_get_active
(
int
fiq_irq
);
...
...
libcpu/arm/am335x/mmu.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -22,122 +22,122 @@ extern void rt_cpu_tlb_set(register rt_uint32_t i);
void
mmu_disable_dcache
()
{
rt_cpu_dcache_disable
();
rt_cpu_dcache_disable
();
}
void
mmu_enable_dcache
()
{
rt_hw_cpu_dcache_enable
();
rt_hw_cpu_dcache_enable
();
}
void
mmu_disable_icache
()
{
rt_cpu_icache_disable
();
rt_cpu_icache_disable
();
}
void
mmu_enable_icache
()
{
rt_hw_cpu_icache_enable
();
rt_hw_cpu_icache_enable
();
}
void
mmu_disable
()
{
rt_cpu_mmu_disable
();
rt_cpu_mmu_disable
();
}
void
mmu_enable
()
{
rt_cpu_mmu_enable
();
rt_cpu_mmu_enable
();
}
void
mmu_setttbase
(
register
rt_uint32_t
i
)
{
register
rt_uint32_t
value
;
register
rt_uint32_t
value
;
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
value
=
0
;
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
value
=
0
;
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
value
=
0x55555555
;
asm
volatile
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
rt_cpu_tlb_set
(
i
);
value
=
0x55555555
;
asm
volatile
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
rt_cpu_tlb_set
(
i
);
}
void
mmu_set_domain
(
register
rt_uint32_t
i
)
{
asm
volatile
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_alignfault
()
{
register
rt_uint32_t
i
;
register
rt_uint32_t
i
;
/* read control register */
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
/* read control register */
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
1
);
i
|=
(
1
<<
1
);
/* write back to control register */
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
/* write back to control register */
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_alignfault
()
{
register
rt_uint32_t
i
;
register
rt_uint32_t
i
;
/* read control register */
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
/* read control register */
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
1
);
i
&=
~
(
1
<<
1
);
/* write back to control register */
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
/* write back to control register */
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_clean_invalidated_cache_index
(
int
index
)
{
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
}
void
mmu_clean_dcache
(
rt_uint32_t
buffer
,
rt_uint32_t
size
)
{
unsigned
int
ptr
;
unsigned
int
ptr
;
ptr
=
buffer
&
~
0x1f
;
ptr
=
buffer
&
~
0x1f
;
while
(
ptr
<
buffer
+
size
)
{
asm
volatile
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
ptr
+=
32
;
}
while
(
ptr
<
buffer
+
size
)
{
asm
volatile
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
ptr
+=
32
;
}
}
void
mmu_invalidate_dcache
(
rt_uint32_t
buffer
,
rt_uint32_t
size
)
{
unsigned
int
ptr
;
unsigned
int
ptr
;
ptr
=
buffer
&
~
0x1f
;
ptr
=
buffer
&
~
0x1f
;
while
(
ptr
<
buffer
+
size
)
{
asm
volatile
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
ptr
+=
32
;
}
while
(
ptr
<
buffer
+
size
)
{
asm
volatile
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
ptr
+=
32
;
}
}
void
mmu_invalidate_tlb
()
{
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
}
void
mmu_invalidate_icache
()
{
asm
volatile
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
}
/* level1 page table */
...
...
@@ -150,8 +150,8 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS
nSec
=
(
vaddrEnd
>>
20
)
-
(
vaddrStart
>>
20
);
for
(
i
=
0
;
i
<=
nSec
;
i
++
)
{
*
pTT
=
attr
|
(((
paddrStart
>>
20
)
+
i
)
<<
20
);
pTT
++
;
*
pTT
=
attr
|
(((
paddrStart
>>
20
)
+
i
)
<<
20
);
pTT
++
;
}
}
...
...
@@ -161,21 +161,21 @@ RT_WEAK void mmu_setmtts(void)
mmu_setmtt
(
0x00000000
,
0xFFFFFFFF
,
0x00000000
,
RW_NCNB
);
/* None cached for 4G memory */
mmu_setmtt
(
0x80200000
,
0x80800000
-
1
,
0x80200000
,
RW_CB
);
/* 126M cached DDR memory */
mmu_setmtt
(
0x80000000
,
0x80200000
-
1
,
0x80000000
,
RW_NCNB
);
/* 2M none-cached DDR memory */
mmu_setmtt
(
0x402F0000
,
0x40300000
-
1
,
0x402F0000
,
RW_CB
);
/* 63K OnChip memory
*/
mmu_setmtt
(
0x402F0000
,
0x40300000
-
1
,
0x402F0000
,
RW_CB
);
/* 63K OnChip memory
*/
}
void
rt_hw_mmu_init
(
void
)
{
/* disable I/D cache */
mmu_disable_dcache
();
mmu_disable_icache
();
mmu_disable
();
mmu_invalidate_tlb
();
/* disable I/D cache */
mmu_disable_dcache
();
mmu_disable_icache
();
mmu_disable
();
mmu_invalidate_tlb
();
mmu_setmtts
();
/* set MMU table address */
mmu_setttbase
((
rt_uint32_t
)
_page_table
);
/* set MMU table address */
mmu_setttbase
((
rt_uint32_t
)
_page_table
);
/* enables MMU */
mmu_enable
();
...
...
libcpu/arm/am335x/mmu.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -13,27 +13,27 @@
#include <rtthread.h>
#define DESC_SEC
(0x2)
#define CB
(3<<2) //cache_on, write_back
#define CNB
(2<<2) //cache_on, write_through
#define NCB
(1<<2) //cache_off,WR_BUF on
#define NCNB
(0<<2) //cache_off,WR_BUF off
#define AP_RW
(3<<10) //supervisor=RW, user=RW
#define AP_RO
(2<<10) //supervisor=RW, user=RO
#define DOMAIN_FAULT
(0x0)
#define DOMAIN_CHK
(0x1)
#define DOMAIN_NOTCHK
(0x3)
#define DOMAIN0
(0x0<<5)
#define DOMAIN1
(0x1<<5)
#define DOMAIN0_ATTR
(DOMAIN_CHK<<0)
#define DOMAIN1_ATTR
(DOMAIN_FAULT<<2)
#define RW_CB
(AP_RW|DOMAIN0|CB|DESC_SEC)
/* Read/Write, cache, write back */
#define RW_CNB
(AP_RW|DOMAIN0|CNB|DESC_SEC)
/* Read/Write, cache, write through */
#define RW_NCNB
(AP_RW|DOMAIN0|NCNB|DESC_SEC)
/* Read/Write without cache and write buffer */
#define RW_FAULT
(AP_RW|DOMAIN1|NCNB|DESC_SEC)
/* Read/Write without cache and write buffer */
#define DESC_SEC
(0x2)
#define CB
(3<<2) //cache_on, write_back
#define CNB
(2<<2) //cache_on, write_through
#define NCB
(1<<2) //cache_off,WR_BUF on
#define NCNB
(0<<2) //cache_off,WR_BUF off
#define AP_RW
(3<<10) //supervisor=RW, user=RW
#define AP_RO
(2<<10) //supervisor=RW, user=RO
#define DOMAIN_FAULT
(0x0)
#define DOMAIN_CHK
(0x1)
#define DOMAIN_NOTCHK
(0x3)
#define DOMAIN0
(0x0<<5)
#define DOMAIN1
(0x1<<5)
#define DOMAIN0_ATTR
(DOMAIN_CHK<<0)
#define DOMAIN1_ATTR
(DOMAIN_FAULT<<2)
#define RW_CB
(AP_RW|DOMAIN0|CB|DESC_SEC)
/* Read/Write, cache, write back */
#define RW_CNB
(AP_RW|DOMAIN0|CNB|DESC_SEC)
/* Read/Write, cache, write through */
#define RW_NCNB
(AP_RW|DOMAIN0|NCNB|DESC_SEC)
/* Read/Write without cache and write buffer */
#define RW_FAULT
(AP_RW|DOMAIN1|NCNB|DESC_SEC)
/* Read/Write without cache and write buffer */
void
rt_hw_mmu_init
(
void
);
...
...
libcpu/arm/am335x/stack.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/am335x/trap.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -36,13 +36,13 @@ extern long list_thread(void);
void
rt_hw_show_register
(
struct
rt_hw_register
*
regs
)
{
rt_kprintf
(
"Execption:
\n
"
);
rt_kprintf
(
"r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x
\n
"
,
regs
->
r0
,
regs
->
r1
,
regs
->
r2
,
regs
->
r3
);
rt_kprintf
(
"r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x
\n
"
,
regs
->
r4
,
regs
->
r5
,
regs
->
r6
,
regs
->
r7
);
rt_kprintf
(
"r08:0x%08x r09:0x%08x r10:0x%08x
\n
"
,
regs
->
r8
,
regs
->
r9
,
regs
->
r10
);
rt_kprintf
(
"fp :0x%08x ip :0x%08x
\n
"
,
regs
->
fp
,
regs
->
ip
);
rt_kprintf
(
"sp :0x%08x lr :0x%08x pc :0x%08x
\n
"
,
regs
->
sp
,
regs
->
lr
,
regs
->
pc
);
rt_kprintf
(
"cpsr:0x%08x
\n
"
,
regs
->
cpsr
);
rt_kprintf
(
"Execption:
\n
"
);
rt_kprintf
(
"r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x
\n
"
,
regs
->
r0
,
regs
->
r1
,
regs
->
r2
,
regs
->
r3
);
rt_kprintf
(
"r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x
\n
"
,
regs
->
r4
,
regs
->
r5
,
regs
->
r6
,
regs
->
r7
);
rt_kprintf
(
"r08:0x%08x r09:0x%08x r10:0x%08x
\n
"
,
regs
->
r8
,
regs
->
r9
,
regs
->
r10
);
rt_kprintf
(
"fp :0x%08x ip :0x%08x
\n
"
,
regs
->
fp
,
regs
->
ip
);
rt_kprintf
(
"sp :0x%08x lr :0x%08x pc :0x%08x
\n
"
,
regs
->
sp
,
regs
->
lr
,
regs
->
pc
);
rt_kprintf
(
"cpsr:0x%08x
\n
"
,
regs
->
cpsr
);
}
/**
...
...
@@ -62,15 +62,15 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
return
;
#endif
rt_hw_show_register
(
regs
);
rt_hw_show_register
(
regs
);
rt_kprintf
(
"undefined instruction
\n
"
);
rt_kprintf
(
"thread %.*s stack:
\n
"
,
RT_NAME_MAX
,
rt_current_thread
->
name
);
rt_kprintf
(
"undefined instruction
\n
"
);
rt_kprintf
(
"thread %.*s stack:
\n
"
,
RT_NAME_MAX
,
rt_current_thread
->
name
);
#ifdef RT_USING_FINSH
list_thread
();
list_thread
();
#endif
rt_hw_cpu_shutdown
();
rt_hw_cpu_shutdown
();
}
/**
...
...
@@ -84,10 +84,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
*/
void
rt_hw_trap_swi
(
struct
rt_hw_register
*
regs
)
{
rt_hw_show_register
(
regs
);
rt_hw_show_register
(
regs
);
rt_kprintf
(
"software interrupt
\n
"
);
rt_hw_cpu_shutdown
();
rt_kprintf
(
"software interrupt
\n
"
);
rt_hw_cpu_shutdown
();
}
/**
...
...
@@ -100,15 +100,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
*/
void
rt_hw_trap_pabt
(
struct
rt_hw_register
*
regs
)
{
rt_hw_show_register
(
regs
);
rt_hw_show_register
(
regs
);
rt_kprintf
(
"prefetch abort
\n
"
);
rt_kprintf
(
"thread %.*s stack:
\n
"
,
RT_NAME_MAX
,
rt_current_thread
->
name
);
rt_kprintf
(
"prefetch abort
\n
"
);
rt_kprintf
(
"thread %.*s stack:
\n
"
,
RT_NAME_MAX
,
rt_current_thread
->
name
);
#ifdef RT_USING_FINSH
list_thread
();
list_thread
();
#endif
rt_hw_cpu_shutdown
();
rt_hw_cpu_shutdown
();
}
/**
...
...
@@ -124,29 +124,29 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
#ifdef RT_USING_GDB
if
(
gdb_mem_fault_handler
)
{
regs
->
pc
=
(
unsigned
long
)
gdb_mem_fault_handler
;
regs
->
pc
=
(
unsigned
long
)
gdb_mem_fault_handler
;
return
;
}
#endif
rt_hw_show_register
(
regs
);
rt_hw_show_register
(
regs
);
rt_kprintf
(
"data abort
\n
"
);
rt_kprintf
(
"thread %.*s stack:
\n
"
,
RT_NAME_MAX
,
rt_current_thread
->
name
);
rt_kprintf
(
"data abort
\n
"
);
rt_kprintf
(
"thread %.*s stack:
\n
"
,
RT_NAME_MAX
,
rt_current_thread
->
name
);
#ifdef RT_USING_FINSH
list_thread
();
list_thread
();
#endif
rt_hw_cpu_shutdown
();
rt_hw_cpu_shutdown
();
}
void
rt_hw_trap_irq
()
{
void
*
param
;
unsigned
long
ir
;
unsigned
long
ir
;
rt_isr_handler_t
isr_func
;
extern
struct
rt_irq_desc
isr_table
[];
ir
=
rt_hw_interrupt_get_active
(
INT_IRQ
);
ir
=
rt_hw_interrupt_get_active
(
INT_IRQ
);
if
(
ir
==
127
)
{
/* new IRQ generation */
...
...
@@ -169,18 +169,18 @@ void rt_hw_trap_irq()
if
(
isr_func
!=
RT_NULL
)
isr_func
(
ir
,
param
);
/* new IRQ generation */
/* new IRQ generation */
rt_hw_interrupt_ack
(
INT_IRQ
);
}
void
rt_hw_trap_fiq
()
{
void
*
param
;
unsigned
long
ir
;
unsigned
long
ir
;
rt_isr_handler_t
isr_func
;
extern
struct
rt_irq_desc
isr_table
[];
ir
=
rt_hw_interrupt_get_active
(
INT_FIQ
);
ir
=
rt_hw_interrupt_get_active
(
INT_FIQ
);
/* get interrupt service routine */
isr_func
=
isr_table
[
ir
].
handler
;
...
...
@@ -189,7 +189,7 @@ void rt_hw_trap_fiq()
/* turn to interrupt service routine */
isr_func
(
ir
,
param
);
/* new FIQ generation */
/* new FIQ generation */
rt_hw_interrupt_ack
(
INT_FIQ
);
}
...
...
libcpu/arm/arm926/cpuport.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/arm926/machine.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/arm926/mmu.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/arm926/mmu.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/arm926/stack.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/arm926/trap.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/armv6/armv6.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __ARMV6_H__
#define __ARMV6_H__
...
...
@@ -26,7 +26,7 @@
#ifndef __ASSEMBLY__
struct
rt_hw_register
{
rt_uint32_t
cpsr
;
rt_uint32_t
cpsr
;
rt_uint32_t
r0
;
rt_uint32_t
r1
;
rt_uint32_t
r2
;
...
...
@@ -46,24 +46,24 @@ struct rt_hw_register
};
#if(0)
struct
rt_hw_register
{
rt_uint32_t
r0
;
rt_uint32_t
r1
;
rt_uint32_t
r2
;
rt_uint32_t
r3
;
rt_uint32_t
r4
;
rt_uint32_t
r5
;
rt_uint32_t
r6
;
rt_uint32_t
r7
;
rt_uint32_t
r8
;
rt_uint32_t
r9
;
rt_uint32_t
r10
;
rt_uint32_t
fp
;
rt_uint32_t
ip
;
rt_uint32_t
sp
;
rt_uint32_t
lr
;
rt_uint32_t
pc
;
rt_uint32_t
cpsr
;
rt_uint32_t
ORIG_r0
;
rt_uint32_t
r0
;
rt_uint32_t
r1
;
rt_uint32_t
r2
;
rt_uint32_t
r3
;
rt_uint32_t
r4
;
rt_uint32_t
r5
;
rt_uint32_t
r6
;
rt_uint32_t
r7
;
rt_uint32_t
r8
;
rt_uint32_t
r9
;
rt_uint32_t
r10
;
rt_uint32_t
fp
;
rt_uint32_t
ip
;
rt_uint32_t
sp
;
rt_uint32_t
lr
;
rt_uint32_t
pc
;
rt_uint32_t
cpsr
;
rt_uint32_t
ORIG_r0
;
};
#endif
#endif
...
...
libcpu/arm/armv6/cpuport.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -11,8 +11,8 @@
#include <rthw.h>
#include <rtthread.h>
#define ICACHE_MASK
(rt_uint32_t)(1 << 12)
#define DCACHE_MASK
(rt_uint32_t)(1 << 2)
#define ICACHE_MASK
(rt_uint32_t)(1 << 12)
#define DCACHE_MASK
(rt_uint32_t)(1 << 2)
extern
void
machine_reset
(
void
);
extern
void
machine_shutdown
(
void
);
...
...
@@ -20,32 +20,32 @@ extern void machine_shutdown(void);
#ifdef __GNUC__
rt_inline
rt_uint32_t
cp15_rd
(
void
)
{
rt_uint32_t
i
;
rt_uint32_t
i
;
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
return
i
;
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
return
i
;
}
rt_inline
void
cache_enable
(
rt_uint32_t
bit
)
{
__asm__
__volatile__
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"orr r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
:
\
:
"r"
(
bit
)
\
:
"memory"
);
__asm__
__volatile__
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"orr r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
:
\
:
"r"
(
bit
)
\
:
"memory"
);
}
rt_inline
void
cache_disable
(
rt_uint32_t
bit
)
{
__asm__
__volatile__
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"bic r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
:
\
:
"r"
(
bit
)
\
:
"memory"
);
__asm__
__volatile__
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"bic r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
:
\
:
"r"
(
bit
)
\
:
"memory"
);
}
...
...
@@ -54,38 +54,38 @@ rt_inline void cache_disable(rt_uint32_t bit)
#ifdef __CC_ARM
rt_inline
rt_uint32_t
cp15_rd
(
void
)
{
rt_uint32_t
i
;
rt_uint32_t
i
;
__asm
{
mrc
p15
,
0
,
i
,
c1
,
c0
,
0
}
__asm
{
mrc
p15
,
0
,
i
,
c1
,
c0
,
0
}
return
i
;
return
i
;
}
rt_inline
void
cache_enable
(
rt_uint32_t
bit
)
{
rt_uint32_t
value
;
rt_uint32_t
value
;
__asm
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
orr
value
,
value
,
bit
mcr
p15
,
0
,
value
,
c1
,
c0
,
0
}
__asm
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
orr
value
,
value
,
bit
mcr
p15
,
0
,
value
,
c1
,
c0
,
0
}
}
rt_inline
void
cache_disable
(
rt_uint32_t
bit
)
{
rt_uint32_t
value
;
rt_uint32_t
value
;
__asm
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
bic
value
,
value
,
bit
mcr
p15
,
0
,
value
,
c1
,
c0
,
0
}
__asm
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
bic
value
,
value
,
bit
mcr
p15
,
0
,
value
,
c1
,
c0
,
0
}
}
#endif
...
...
@@ -95,7 +95,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
*/
void
rt_hw_cpu_icache_enable
()
{
cache_enable
(
ICACHE_MASK
);
cache_enable
(
ICACHE_MASK
);
}
/**
...
...
@@ -104,7 +104,7 @@ void rt_hw_cpu_icache_enable()
*/
void
rt_hw_cpu_icache_disable
()
{
cache_disable
(
ICACHE_MASK
);
cache_disable
(
ICACHE_MASK
);
}
/**
...
...
@@ -113,7 +113,7 @@ void rt_hw_cpu_icache_disable()
*/
rt_base_t
rt_hw_cpu_icache_status
()
{
return
(
cp15_rd
()
&
ICACHE_MASK
);
return
(
cp15_rd
()
&
ICACHE_MASK
);
}
/**
...
...
@@ -122,7 +122,7 @@ rt_base_t rt_hw_cpu_icache_status()
*/
void
rt_hw_cpu_dcache_enable
()
{
cache_enable
(
DCACHE_MASK
);
cache_enable
(
DCACHE_MASK
);
}
/**
...
...
@@ -131,7 +131,7 @@ void rt_hw_cpu_dcache_enable()
*/
void
rt_hw_cpu_dcache_disable
()
{
cache_disable
(
DCACHE_MASK
);
cache_disable
(
DCACHE_MASK
);
}
/**
...
...
@@ -140,7 +140,7 @@ void rt_hw_cpu_dcache_disable()
*/
rt_base_t
rt_hw_cpu_dcache_status
()
{
return
(
cp15_rd
()
&
DCACHE_MASK
);
return
(
cp15_rd
()
&
DCACHE_MASK
);
}
/**
...
...
@@ -149,13 +149,13 @@ rt_base_t rt_hw_cpu_dcache_status()
*/
RT_WEAK
void
rt_hw_cpu_reset
()
{
rt_kprintf
(
"Restarting system...
\n
"
);
machine_reset
();
while
(
1
);
/* loop forever and wait for reset to happen */
rt_kprintf
(
"Restarting system...
\n
"
);
machine_reset
();
/* NEVER REACHED */
while
(
1
);
/* loop forever and wait for reset to happen */
/* NEVER REACHED */
}
/**
...
...
@@ -164,67 +164,67 @@ RT_WEAK void rt_hw_cpu_reset()
*/
RT_WEAK
void
rt_hw_cpu_shutdown
()
{
rt_uint32_t
level
;
rt_kprintf
(
"shutdown...
\n
"
);
rt_uint32_t
level
;
rt_kprintf
(
"shutdown...
\n
"
);
level
=
rt_hw_interrupt_disable
();
machine_shutdown
();
while
(
level
)
{
RT_ASSERT
(
0
);
}
level
=
rt_hw_interrupt_disable
();
machine_shutdown
();
while
(
level
)
{
RT_ASSERT
(
0
);
}
}
#ifdef RT_USING_CPU_FFS
/**
* This function finds the first bit set (beginning with the least significant bit)
* This function finds the first bit set (beginning with the least significant bit)
* in value and return the index of that bit.
*
* Bits are numbered starting at 1 (the least significant bit). A return value of
* Bits are numbered starting at 1 (the least significant bit). A return value of
* zero from any of these functions means that the argument was zero.
*
* @return return the index of the first bit set. If value is 0, then this function
*
* @return return the index of the first bit set. If value is 0, then this function
* shall return 0.
*/
#if defined(__CC_ARM)
int
__rt_ffs
(
int
value
)
{
register
rt_uint32_t
x
;
register
rt_uint32_t
x
;
if
(
value
==
0
)
return
value
;
if
(
value
==
0
)
return
value
;
__asm
{
rsb
x
,
value
,
#
0
and
x
,
x
,
value
clz
x
,
x
rsb
x
,
x
,
#
32
}
__asm
{
rsb
x
,
value
,
#
0
and
x
,
x
,
value
clz
x
,
x
rsb
x
,
x
,
#
32
}
return
x
;
return
x
;
}
#elif defined(__IAR_SYSTEMS_ICC__)
int
__rt_ffs
(
int
value
)
{
if
(
value
==
0
)
return
value
;
if
(
value
==
0
)
return
value
;
__ASM
(
"RSB r4, r0, #0"
);
__ASM
(
"AND r4, r4, r0"
);
__ASM
(
"CLZ r4, r4"
);
__ASM
(
"RSB r0, r4, #32"
);
__ASM
(
"RSB r4, r0, #0"
);
__ASM
(
"AND r4, r4, r0"
);
__ASM
(
"CLZ r4, r4"
);
__ASM
(
"RSB r0, r4, #32"
);
}
#elif defined(__GNUC__)
int
__rt_ffs
(
int
value
)
{
if
(
value
==
0
)
return
value
;
if
(
value
==
0
)
return
value
;
value
&=
(
-
value
);
asm
(
"clz %0, %1"
:
"=r"
(
value
)
:
"r"
(
value
));
value
&=
(
-
value
);
asm
(
"clz %0, %1"
:
"=r"
(
value
)
:
"r"
(
value
));
return
(
32
-
value
);
return
(
32
-
value
);
}
#endif
...
...
libcpu/arm/armv6/mmu.c
浏览文件 @
6c907c3a
此差异已折叠。
点击以展开。
libcpu/arm/armv6/mmu.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -12,7 +12,7 @@
#include <rtthread.h>
#define CACHE_LINE_SIZE
32
#define CACHE_LINE_SIZE
32
/*
* Hardware page table definitions.
...
...
@@ -30,7 +30,7 @@
/*
* - section
*/
#define PGD_SECT_BUFFERABLE
(1 << 2)
#define PGD_SECT_BUFFERABLE
(1 << 2)
#define PGD_SECT_CACHEABLE (1 << 3)
#define PGD_SECT_XN (1 << 4)
/* ARMv6 */
#define PGD_SECT_AP0 (1 << 10)
...
...
@@ -155,35 +155,35 @@
#define PAGE_RONX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN)
/* Read Only without cache and write buffer */
#define DESC_SEC
(0x2|(1<<4))
#define CB
(3<<2) //cache_on, write_back
#define CNB
(2<<2) //cache_on, write_through
#define NCB
(1<<2) //cache_off,WR_BUF on
#define NCNB
(0<<2) //cache_off,WR_BUF off
#define AP_RW
(3<<10) //supervisor=RW, user=RW
#define AP_RO
(2<<10) //supervisor=RW, user=RO
#define DESC_SEC
(0x2|(1<<4))
#define CB
(3<<2) //cache_on, write_back
#define CNB
(2<<2) //cache_on, write_through
#define NCB
(1<<2) //cache_off,WR_BUF on
#define NCNB
(0<<2) //cache_off,WR_BUF off
#define AP_RW
(3<<10) //supervisor=RW, user=RW
#define AP_RO
(2<<10) //supervisor=RW, user=RO
#define DOMAIN_FAULT
(0x0)
#define DOMAIN_CHK
(0x1)
#define DOMAIN_NOTCHK
(0x3)
#define DOMAIN0
(0x0<<5)
#define DOMAIN1
(0x1<<5)
#define DOMAIN_FAULT
(0x0)
#define DOMAIN_CHK
(0x1)
#define DOMAIN_NOTCHK
(0x3)
#define DOMAIN0
(0x0<<5)
#define DOMAIN1
(0x1<<5)
#define DOMAIN0_ATTR
(DOMAIN_CHK<<0)
#define DOMAIN1_ATTR
(DOMAIN_FAULT<<2)
#define DOMAIN0_ATTR
(DOMAIN_CHK<<0)
#define DOMAIN1_ATTR
(DOMAIN_FAULT<<2)
#define RW_CB
(AP_RW|DOMAIN0|CB|DESC_SEC)
/* Read/Write, cache, write back */
#define RW_CNB
(AP_RW|DOMAIN0|CNB|DESC_SEC)
/* Read/Write, cache, write through */
#define RW_NCNB
(AP_RW|DOMAIN0|NCNB|DESC_SEC)
/* Read/Write without cache and write buffer */
#define RW_FAULT
(AP_RW|DOMAIN1|NCNB|DESC_SEC)
/* Read/Write without cache and write buffer */
#define RW_CB
(AP_RW|DOMAIN0|CB|DESC_SEC)
/* Read/Write, cache, write back */
#define RW_CNB
(AP_RW|DOMAIN0|CNB|DESC_SEC)
/* Read/Write, cache, write through */
#define RW_NCNB
(AP_RW|DOMAIN0|NCNB|DESC_SEC)
/* Read/Write without cache and write buffer */
#define RW_FAULT
(AP_RW|DOMAIN1|NCNB|DESC_SEC)
/* Read/Write without cache and write buffer */
struct
mem_desc
{
rt_uint32_t
vaddr_start
;
rt_uint32_t
vaddr_end
;
rt_uint32_t
paddr_start
;
rt_uint32_t
sect_attr
;
/* when page mapped */
rt_uint32_t
page_attr
;
/* only sector mapped valid */
rt_uint32_t
mapped_mode
;
rt_uint32_t
vaddr_start
;
rt_uint32_t
vaddr_end
;
rt_uint32_t
paddr_start
;
rt_uint32_t
sect_attr
;
/* when page mapped */
rt_uint32_t
page_attr
;
/* only sector mapped valid */
rt_uint32_t
mapped_mode
;
#define SECT_MAPPED 0
#define PAGE_MAPPED 1
};
...
...
libcpu/arm/armv6/stack.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/armv6/vfp.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/armv6/vfp.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -87,7 +87,7 @@
})
#define vmsr(vfp, var) \
asm("vmsr "#vfp", %0"
\
asm("vmsr "#vfp", %0"
\
: : "r" (var) : "cc")
...
...
libcpu/arm/common/backtrace.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/common/div0.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -8,5 +8,5 @@
*/
void
__div0
(
void
)
{
while
(
1
)
;
while
(
1
)
;
}
libcpu/arm/common/showmem.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -12,27 +12,27 @@
void
rt_hw_show_memory
(
rt_uint32_t
addr
,
rt_uint32_t
size
)
{
int
i
=
0
,
j
=
0
;
int
i
=
0
,
j
=
0
;
RT_ASSERT
(
addr
);
RT_ASSERT
(
addr
);
addr
=
addr
&
~
0xF
;
size
=
4
*
((
size
+
3
)
/
4
);
addr
=
addr
&
~
0xF
;
size
=
4
*
((
size
+
3
)
/
4
);
while
(
i
<
size
)
{
rt_kprintf
(
"0x%08x: "
,
addr
);
while
(
i
<
size
)
{
rt_kprintf
(
"0x%08x: "
,
addr
);
for
(
j
=
0
;
j
<
4
;
j
++
)
{
rt_kprintf
(
"0x%08x "
,
*
(
rt_uint32_t
*
)
addr
);
for
(
j
=
0
;
j
<
4
;
j
++
)
{
rt_kprintf
(
"0x%08x "
,
*
(
rt_uint32_t
*
)
addr
);
addr
+=
4
;
i
++
;
}
addr
+=
4
;
i
++
;
}
rt_kprintf
(
"
\n
"
);
}
rt_kprintf
(
"
\n
"
);
}
return
;
return
;
}
libcpu/arm/cortex-a/armv7.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -12,43 +12,43 @@
/* the exception stack without VFP registers */
struct
rt_hw_exp_stack
{
unsigned
long
r0
;
unsigned
long
r1
;
unsigned
long
r2
;
unsigned
long
r3
;
unsigned
long
r4
;
unsigned
long
r5
;
unsigned
long
r6
;
unsigned
long
r7
;
unsigned
long
r8
;
unsigned
long
r9
;
unsigned
long
r10
;
unsigned
long
fp
;
unsigned
long
ip
;
unsigned
long
sp
;
unsigned
long
lr
;
unsigned
long
pc
;
unsigned
long
cpsr
;
unsigned
long
r0
;
unsigned
long
r1
;
unsigned
long
r2
;
unsigned
long
r3
;
unsigned
long
r4
;
unsigned
long
r5
;
unsigned
long
r6
;
unsigned
long
r7
;
unsigned
long
r8
;
unsigned
long
r9
;
unsigned
long
r10
;
unsigned
long
fp
;
unsigned
long
ip
;
unsigned
long
sp
;
unsigned
long
lr
;
unsigned
long
pc
;
unsigned
long
cpsr
;
};
struct
rt_hw_stack
{
unsigned
long
cpsr
;
unsigned
long
r0
;
unsigned
long
r1
;
unsigned
long
r2
;
unsigned
long
r3
;
unsigned
long
r4
;
unsigned
long
r5
;
unsigned
long
r6
;
unsigned
long
r7
;
unsigned
long
r8
;
unsigned
long
r9
;
unsigned
long
r10
;
unsigned
long
fp
;
unsigned
long
ip
;
unsigned
long
lr
;
unsigned
long
pc
;
unsigned
long
cpsr
;
unsigned
long
r0
;
unsigned
long
r1
;
unsigned
long
r2
;
unsigned
long
r3
;
unsigned
long
r4
;
unsigned
long
r5
;
unsigned
long
r6
;
unsigned
long
r7
;
unsigned
long
r8
;
unsigned
long
r9
;
unsigned
long
r10
;
unsigned
long
fp
;
unsigned
long
ip
;
unsigned
long
lr
;
unsigned
long
pc
;
};
#define USERMODE 0x10
...
...
libcpu/arm/cortex-a/cache.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-29
quanzhao
the first version
* 2019-03-29
quanzhao
the first version
*/
#include <rthw.h>
#include <rtdef.h>
...
...
libcpu/arm/cortex-a/cp15.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/cpu.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/gic.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/gic.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/interrupt.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/interrupt.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/mmu.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/mmu.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/pmu.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/pmu.h
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/stack.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-a/trap.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-m0/cpuport.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-m23/cpuport.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
19
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-m3/cpuport.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-m33/cpuport.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -457,7 +457,7 @@ RT_WEAK void rt_hw_cpu_reset(void)
* @return return the index of the first bit set. If value is 0, then this function
* shall return 0.
*/
#if defined(__CC_ARM)
#if defined(__CC_ARM)
__asm
int
__rt_ffs
(
int
value
)
{
CMP
r0
,
#
0x00
...
...
libcpu/arm/cortex-m33/trustzone.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
19
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -31,7 +31,7 @@ extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
rt_ubase_t
rt_trustzone_current_context
;
#if defined(__CC_ARM)
#if defined(__CC_ARM)
static
__inline
rt_uint32_t
__get_IPSR
(
void
)
{
register
rt_uint32_t
result
__asm
(
"ipsr"
);
...
...
@@ -78,7 +78,7 @@ rt_err_t rt_trustzone_enter(rt_ubase_t module)
rt_trustzone_init
();
if
(
tzcall
(
TZ_ALLOC_CONTEXT_ID
,
module
,
0
,
0
))
{
return
RT_EOK
;
return
RT_EOK
;
}
return
-
RT_ERROR
;
}
...
...
libcpu/arm/cortex-m4/cpuport.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -454,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void)
* @return return the index of the first bit set. If value is 0, then this function
* shall return 0.
*/
#if defined(__CC_ARM)
#if defined(__CC_ARM)
__asm
int
__rt_ffs
(
int
value
)
{
CMP
r0
,
#
0x00
...
...
libcpu/arm/cortex-m7/cpu_cache.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -13,7 +13,7 @@
#include <rtdef.h>
#include <board.h>
/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
/* The L1-caches on all Cortex
Â
®-M7s are divided into lines of 32 bytes. */
#define L1CACHE_LINESIZE_BYTE (32)
void
rt_hw_cpu_icache_enable
(
void
)
...
...
libcpu/arm/cortex-m7/cpuport.c
浏览文件 @
6c907c3a
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-r4/armv7.h
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/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -16,23 +16,23 @@
/* the exception stack without VFP registers */
struct
rt_hw_exp_stack
{
unsigned
long
r0
;
unsigned
long
r1
;
unsigned
long
r2
;
unsigned
long
r3
;
unsigned
long
r4
;
unsigned
long
r5
;
unsigned
long
r6
;
unsigned
long
r7
;
unsigned
long
r8
;
unsigned
long
r9
;
unsigned
long
r10
;
unsigned
long
fp
;
unsigned
long
ip
;
unsigned
long
sp
;
unsigned
long
lr
;
unsigned
long
pc
;
unsigned
long
cpsr
;
unsigned
long
r0
;
unsigned
long
r1
;
unsigned
long
r2
;
unsigned
long
r3
;
unsigned
long
r4
;
unsigned
long
r5
;
unsigned
long
r6
;
unsigned
long
r7
;
unsigned
long
r8
;
unsigned
long
r9
;
unsigned
long
r10
;
unsigned
long
fp
;
unsigned
long
ip
;
unsigned
long
sp
;
unsigned
long
lr
;
unsigned
long
pc
;
unsigned
long
cpsr
;
};
#define USERMODE 0x10
...
...
libcpu/arm/cortex-r4/cpu.c
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/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -30,22 +30,22 @@ RT_WEAK void rt_hw_cpu_reset()
*/
RT_WEAK
void
rt_hw_cpu_shutdown
()
{
rt_kprintf
(
"shutdown...
\n
"
);
rt_kprintf
(
"shutdown...
\n
"
);
while
(
1
);
while
(
1
);
}
#ifdef __TI_COMPILER_VERSION__
#ifdef RT_USING_CPU_FFS
int
__rt_ffs
(
int
value
)
{
if
(
value
==
0
)
return
value
;
if
(
value
==
0
)
return
value
;
__asm
(
" rsb r1, r0, #0"
);
__asm
(
" and r1, r1, r0"
);
__asm
(
" clz r1, r1"
);
__asm
(
" rsb r0, r1, #32"
);
__asm
(
" rsb r1, r0, #0"
);
__asm
(
" and r1, r1, r0"
);
__asm
(
" clz r1, r1"
);
__asm
(
" rsb r0, r1, #32"
);
}
#endif
...
...
libcpu/arm/cortex-r4/interrupt.c
浏览文件 @
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/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -17,7 +17,7 @@
#include "armv7.h"
#define MAX_HANDLERS
96
#define MAX_HANDLERS
96
/* exception and interrupt handler table */
struct
rt_irq_desc
irq_desc
[
MAX_HANDLERS
];
...
...
@@ -36,16 +36,16 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
static
void
rt_hw_int_not_handle
(
int
vector
,
void
*
param
)
{
rt_kprintf
(
"Unhandled interrupt %d occured!!!
\n
"
,
vector
);
rt_kprintf
(
"Unhandled interrupt %d occured!!!
\n
"
,
vector
);
}
#define vimRAM (0xFFF82000U)
void
rt_hw_interrupt_init
(
void
)
{
register
int
i
;
register
int
i
;
rt_uint32_t
*
vect_addr
;
rt_uint32_t
*
vect_addr
;
/* the initialization is done in sys_startup.c */
...
...
@@ -55,15 +55,15 @@ void rt_hw_interrupt_init(void)
{
irq_desc
[
i
].
handler
=
rt_hw_int_not_handle
;
vect_addr
=
(
rt_uint32_t
*
)(
vimRAM
+
i
*
4
);
*
vect_addr
=
(
rt_uint32_t
)
&
irq_desc
[
i
];
vect_addr
=
(
rt_uint32_t
*
)(
vimRAM
+
i
*
4
);
*
vect_addr
=
(
rt_uint32_t
)
&
irq_desc
[
i
];
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest
=
0
;
rt_interrupt_from_thread
=
0
;
rt_interrupt_to_thread
=
0
;
rt_thread_switch_interrupt_flag
=
0
;
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest
=
0
;
rt_interrupt_from_thread
=
0
;
rt_interrupt_to_thread
=
0
;
rt_thread_switch_interrupt_flag
=
0
;
}
void
rt_hw_interrupt_mask
(
int
vector
)
...
...
@@ -86,21 +86,21 @@ void rt_hw_interrupt_umask(int vector)
* @return the old handler
*/
rt_isr_handler_t
rt_hw_interrupt_install
(
int
vector
,
rt_isr_handler_t
handler
,
void
*
param
,
const
char
*
name
)
void
*
param
,
const
char
*
name
)
{
rt_isr_handler_t
old_handler
=
RT_NULL
;
if
(
vector
>=
0
&&
vector
<
MAX_HANDLERS
)
{
old_handler
=
irq_desc
[
vector
].
handler
;
if
(
handler
!=
RT_NULL
)
{
irq_desc
[
vector
].
handler
=
handler
;
irq_desc
[
vector
].
param
=
param
;
}
}
return
old_handler
;
rt_isr_handler_t
old_handler
=
RT_NULL
;
if
(
vector
>=
0
&&
vector
<
MAX_HANDLERS
)
{
old_handler
=
irq_desc
[
vector
].
handler
;
if
(
handler
!=
RT_NULL
)
{
irq_desc
[
vector
].
handler
=
handler
;
irq_desc
[
vector
].
param
=
param
;
}
}
return
old_handler
;
}
/*@}*/
libcpu/arm/cortex-r4/stack.c
浏览文件 @
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/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
libcpu/arm/cortex-r4/trap.c
浏览文件 @
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/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
...
...
@@ -28,13 +28,13 @@
*/
void
rt_hw_show_register
(
struct
rt_hw_exp_stack
*
regs
)
{
rt_kprintf
(
"Execption:
\n
"
);
rt_kprintf
(
"r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x
\n
"
,
regs
->
r0
,
regs
->
r1
,
regs
->
r2
,
regs
->
r3
);
rt_kprintf
(
"r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x
\n
"
,
regs
->
r4
,
regs
->
r5
,
regs
->
r6
,
regs
->
r7
);
rt_kprintf
(
"r08:0x%08x r09:0x%08x r10:0x%08x
\n
"
,
regs
->
r8
,
regs
->
r9
,
regs
->
r10
);
rt_kprintf
(
"fp :0x%08x ip :0x%08x
\n
"
,
regs
->
fp
,
regs
->
ip
);
rt_kprintf
(
"sp :0x%08x lr :0x%08x pc :0x%08x
\n
"
,
regs
->
sp
,
regs
->
lr
,
regs
->
pc
);
rt_kprintf
(
"cpsr:0x%08x
\n
"
,
regs
->
cpsr
);
rt_kprintf
(
"Execption:
\n
"
);
rt_kprintf
(
"r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x
\n
"
,
regs
->
r0
,
regs
->
r1
,
regs
->
r2
,
regs
->
r3
);
rt_kprintf
(
"r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x
\n
"
,
regs
->
r4
,
regs
->
r5
,
regs
->
r6
,
regs
->
r7
);
rt_kprintf
(
"r08:0x%08x r09:0x%08x r10:0x%08x
\n
"
,
regs
->
r8
,
regs
->
r9
,
regs
->
r10
);
rt_kprintf
(
"fp :0x%08x ip :0x%08x
\n
"
,
regs
->
fp
,
regs
->
ip
);
rt_kprintf
(
"sp :0x%08x lr :0x%08x pc :0x%08x
\n
"
,
regs
->
sp
,
regs
->
lr
,
regs
->
pc
);
rt_kprintf
(
"cpsr:0x%08x
\n
"
,
regs
->
cpsr
);
}
/**
...
...
@@ -49,8 +49,8 @@ void rt_hw_trap_udef(struct rt_hw_exp_stack *regs)
{
rt_kprintf
(
"undefined instruction
\n
"
);
rt_hw_show_register
(
regs
);
if
(
rt_thread_self
()
!=
RT_NULL
)
rt_kprintf
(
"Current Thread: %s
\n
"
,
rt_thread_self
()
->
name
);
if
(
rt_thread_self
()
!=
RT_NULL
)
rt_kprintf
(
"Current Thread: %s
\n
"
,
rt_thread_self
()
->
name
);
rt_hw_cpu_shutdown
();
}
...
...
@@ -68,7 +68,7 @@ void rt_hw_trap_svc(struct rt_hw_exp_stack *regs)
rt_kprintf
(
"software interrupt
\n
"
);
rt_hw_show_register
(
regs
);
#ifdef RT_USING_FINSH
list_thread
();
list_thread
();
#endif
rt_hw_cpu_shutdown
();
}
...
...
@@ -86,7 +86,7 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
rt_kprintf
(
"prefetch abort
\n
"
);
rt_hw_show_register
(
regs
);
#ifdef RT_USING_FINSH
list_thread
();
list_thread
();
#endif
rt_hw_cpu_shutdown
();
}
...
...
@@ -104,7 +104,7 @@ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
rt_kprintf
(
"Data Abort "
);
rt_hw_show_register
(
regs
);
#ifdef RT_USING_FINSH
list_thread
();
list_thread
();
#endif
rt_hw_cpu_shutdown
();
}
...
...
@@ -121,7 +121,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
rt_kprintf
(
"Reserved trap
\n
"
);
rt_hw_show_register
(
regs
);
#ifdef RT_USING_FINSH
list_thread
();
list_thread
();
#endif
rt_hw_cpu_shutdown
();
}
...
...
@@ -129,15 +129,15 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
extern
rt_isr_handler_t
isr_table
[];
void
rt_hw_trap_irq
(
void
)
{
int
irqno
;
struct
rt_irq_desc
*
irq
;
extern
struct
rt_irq_desc
irq_desc
[];
int
irqno
;
struct
rt_irq_desc
*
irq
;
extern
struct
rt_irq_desc
irq_desc
[];
irq
=
(
struct
rt_irq_desc
*
)
vimREG
->
IRQVECREG
;
irqno
=
((
rt_uint32_t
)
irq
-
(
rt_uint32_t
)
&
irq_desc
[
0
])
/
sizeof
(
struct
rt_irq_desc
);
irq
=
(
struct
rt_irq_desc
*
)
vimREG
->
IRQVECREG
;
irqno
=
((
rt_uint32_t
)
irq
-
(
rt_uint32_t
)
&
irq_desc
[
0
])
/
sizeof
(
struct
rt_irq_desc
);
/* invoke isr */
irq
->
handler
(
irqno
,
irq
->
param
);
/* invoke isr */
irq
->
handler
(
irqno
,
irq
->
param
);
}
void
rt_hw_trap_fiq
(
void
)
...
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