Merge pull request #5094 from aisino2200/master

ACM32F4XX-nucleo bsp add

bsp/acm32f4xx-nucleo/.ignore_format.yml

+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- libraries

bsp/acm32f4xx-nucleo/Kconfig

+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+source "$BSP_DIR/drivers/Kconfig"
+

bsp/acm32f4xx-nucleo/README.md

+# acm32f0x0板级支持包
+
+## 1. 简介
+
+ACM32F4xx芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性：
+
+|--------------------------|--------------------|
+|         硬件             |         描述       |
+| -------------------------|--------------------|
+|芯片型号                  | ACM32F4XX系列      |
+|CPU                       | ARM Cortex-M33     |
+|主频                      | 180MHz             |
+|片内SRAM                  | 192K               |
+|片内Flash                 | 512K               |
+|--------------------------|--------------------|
+
+具体型号及资源请参考上海航芯官方网站[ACM32F4](www.aisinochip.com/index.php/product/child1/id/219.html)。
+
+## 2. 编译说明
+
+推荐使用[env工具][1]，可以在console下进入到`bsp/acm32f4xx-nucleo`目录中，运行以下命令：
+
+`scons`
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
+
+也可以通过`scons --target=mdk5`生成keil工程，再使用keil进行编译。
+
+## 3. 烧写及执行
+
+开发板的使用请参考上海航芯官方网站相应型号的[开发工具](www.aisinochip.com/index.php/product/detail/id/25.html)。
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+## 4. 驱动支持情况及计划
+
+| **片上外设**  | **支持情况** |               **备注**                |
+| ------------- | ------------ | ------------------------------------- |
+| GPIO          |     支持     | PA0, PA1... PF4 ---> PIN: 0, 1...83  |
+| UART          |     支持     |              UART1/UART2              |
+| LED           |     支持     |              LED1                     |
+
+## 5. 联系人信息
+
+维护人：AisinoChip < xiangfeng.liu@aisinochip.com >
+
+## 6. 参考
+
+* 板子[数据手册][2]
+* 芯片[数据手册][3]
+
+  [1]: https://www.rt-thread.org/page/download.html
+  [2]: www.aisinochip.com/index.php/product/detail/id/50.html
+  [3]: www.aisinochip.com/index.php/product/detail/id/50.html

bsp/acm32f4xx-nucleo/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/acm32f4xx-nucleo/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread_acm32f4xx.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/acm32f4xx-nucleo/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/acm32f4xx-nucleo/applications/main.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-17     AisinoChip   the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include <drivers/pin.h>
+
+#define LED_PIN_NUM    83     /* PF3 */
+
+int main(void)
+{
+    rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN_NUM, PIN_LOW);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
+        rt_pin_write(LED_PIN_NUM, PIN_HIGH);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
+    }
+}

bsp/acm32f4xx-nucleo/drivers/Kconfig

+menu "Hardware Drivers Config"
+
+choice
+    prompt "select chip type"
+    default SOC_ACM32F403RET7
+
+    config SOC_ACM32F403KCU7
+    bool "SOC_ACM32F403KCU7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403KEU7
+    bool "SOC_ACM32F403KEU7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403CCT7
+    bool "SOC_ACM32F403CCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403CET7
+    bool "SOC_ACM32F403CET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403RCT7
+    bool "SOC_ACM32F403RCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403RET7
+    bool "SOC_ACM32F403RET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403VCT7
+    bool "SOC_ACM32F403VCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403VET7
+    bool "SOC_ACM32F403VET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+endchoice
+
+menu "ACM32F403RET7"
+    depends on SOC_ACM32F403RET7
+
+    config SOC_SRAM_START_ADDR
+        hex "sram start address"
+        default 0x20000000
+
+    config SOC_SRAM_SIZE
+        hex "sram size(KBytes)"
+        default 0xC0
+
+    config SOC_FLASH_START_ADDR
+        hex "EFlash Start Address"
+        default 0x00000000
+
+    config SOC_FLASH_SIZE
+        hex "EFlash Size(KBytes)"
+        default 0x8000
+endmenu
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    menu "Hardware GPIO"
+        config BSP_USING_GPIO1
+            bool "Enable GPIOAB"
+            default y
+            select RT_USING_PIN
+        config BSP_USING_GPIO2
+            bool "Enable GPIOCD"
+            default y
+            select RT_USING_PIN
+        config BSP_USING_GPIO3
+            bool "Enable GPIOEF"
+            default y
+            select RT_USING_PIN
+    endmenu
+
+    config BSP_USING_ADC
+        bool "Enable ADC"
+        select RT_USING_ADC
+        default n
+
+    config BSP_USING_DAC
+        bool "Enable DAC"
+        select RT_USING_DAC
+        default n
+
+    menu "Hardware UART"
+        config BSP_USING_UART1
+            bool "Enable UART1 (PA9/PA10)"
+            default y
+            select RT_USING_SERIAL
+
+        config BSP_USING_UART2
+            bool "Enable UART2 (PA2/PA3)"
+            default y
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART2
+            config BSP_UART2_RX_USING_DMA
+                bool "Enable UART2 RX DMA"
+                depends on BSP_USING_UART2
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART2_TX_USING_DMA
+                bool "Enable UART2 TX DMA"
+                depends on BSP_USING_UART2
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+
+        config BSP_USING_UART3
+            bool "Enable UART3 (PC4/PC5)"
+            default n
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART3
+            config BSP_UART3_RX_USING_DMA
+                bool "Enable UART3 RX DMA"
+                depends on BSP_USING_UART3
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART3_TX_USING_DMA
+                bool "Enable UART3 TX DMA"
+                depends on BSP_USING_UART3
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+
+        config BSP_USING_UART4
+            bool "Enable UART4 (PC11/PC10)"
+            default n
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART4
+            config BSP_UART4_RX_USING_DMA
+                bool "Enable UART4 RX DMA"
+                depends on BSP_USING_UART4
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART4_TX_USING_DMA
+                bool "Enable UART4 TX DMA"
+                depends on BSP_USING_UART4
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+    endmenu
+
+    config BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+
+    config BSP_USING_LPUART
+        bool "Enable LPUART"
+        select RT_USING_UART
+        default n
+
+    menu "Hardware I2C"
+        config BSP_USING_I2C1
+            bool "Enable I2C1"
+            default n
+            select RT_USING_I2C
+        config BSP_USING_I2C2
+            bool "Enable I2C2"
+            default n
+            select RT_USING_I2C
+    endmenu
+
+    menu "Hardware I2S"
+        config BSP_USING_I2S1
+            bool "Enable I2S1"
+            default n
+            select RT_USING_I2S
+    endmenu
+
+    menu "Hardware CAN"
+        config BSP_USING_CAN1
+            bool "Enable CAN1"
+            default n
+            select RT_USING_CAN
+        config BSP_USING_CAN2
+            bool "Enable CAN2"
+            default n
+            select RT_USING_CAN
+    endmenu
+
+    menu "Hardware TIMER"
+        config BSP_USING_TIM1
+            bool "Enable Timer1"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM2
+            bool "Enable Timer2"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM3
+            bool "Enable Timer3"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM4
+            bool "Enable Timer4"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM6
+            bool "Enable Timer6"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM7
+            bool "Enable Timer7"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM14
+            bool "Enable Timer14"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM15
+            bool "Enable Timer15"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM16
+            bool "Enable Timer16"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM17
+            bool "Enable Timer17"
+            default n
+            select RT_USING_HWTIMER
+    endmenu
+
+    menu "Hardware WDT"
+        config BSP_USING_WDT
+            bool "Enable Watch Dog Timer"
+            default n
+            select RT_USING_WDT
+        config BSP_USING_IWDT
+            bool "Enable Independent Watch Dog Timer"
+            default n
+            select RT_USING_WDT
+    endmenu
+
+    config BSP_USING_LCD
+        bool "Enable LCD"
+        default n
+
+    menu "Hardware SPI"
+        config BSP_USING_SPI1
+            bool "Enable SPI1"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI1
+            config BSP_SPI1_RX_USING_DMA
+                bool "Enable SPI1 RX DMA"
+                default n
+
+            config BSP_SPI1_TX_USING_DMA
+                bool "Enable SPI1 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI2
+            bool "Enable SPI2"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI2
+            config BSP_SPI2_RX_USING_DMA
+                bool "Enable SPI2 RX DMA"
+                default n
+
+            config BSP_SPI2_TX_USING_DMA
+                bool "Enable SPI2 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI3
+            bool "Enable SPI3"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI3
+            config BSP_SPI3_RX_USING_DMA
+                bool "Enable SPI3 RX DMA"
+                default n
+
+            config BSP_SPI3_TX_USING_DMA
+                bool "Enable SPI3 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI4
+            bool "Enable SPI4"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI4
+            config BSP_SPI4_RX_USING_DMA
+                bool "Enable SPI4 RX DMA"
+                default n
+
+            config BSP_SPI4_TX_USING_DMA
+                bool "Enable SPI4 TX DMA"
+                default n
+        endif
+    endmenu
+
+    menu "Hardware CRYPTO"
+        config BSP_USING_CRC
+            select RT_HWCRYPTO_USING_CRC
+            bool "Enable CRC"
+            default n
+            select RT_USING_HWCRYPTO
+        config BSP_USING_AES
+            select RT_HWCRYPTO_USING_AES
+            bool "Enable AES"
+            default n
+            select RT_USING_HWCRYPTO
+
+        config BSP_USING_HRNG
+            select RT_HWCRYPTO_USING_RNG
+            bool "Enable HRNG"
+            default n
+            select RT_USING_HWCRYPTO
+    endmenu
+
+    config BSP_USING_CMP
+        bool "Enable Analog Voltage Comparer"
+        default n
+
+    config BSP_USING_OPA
+        bool "Enable Operational Amplifier"
+        default n
+
+    config BSP_USING_TKEY
+        bool "Enable Touch Key"
+        select RT_USING_TOUCH
+        default n
+
+    config BSP_USING_RPMU
+        bool "Enable RTC PMU"
+        select RT_USING_PM
+        default n
+
+    config BSP_USING_USBD
+        bool "Enable USB Device"
+        select RT_USING_USB
+        default n
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
+

bsp/acm32f4xx-nucleo/drivers/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
+

bsp/acm32f4xx-nucleo/drivers/board.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-25     AisinoChip   first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include <rtdevice.h>
+
+#define SOC_SRAM_END_ADDR   (SOC_SRAM_START_ADDR+SOC_SRAM_SIZE*1024)
+
+extern int  rt_application_init(void);
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+    #pragma section="HEAP"
+#else
+    extern int __bss_end;
+#endif
+
+extern void rt_hw_uart_init(void);
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial EVB board.
+ */
+void rt_hw_board_init(void)
+{
+    /* system init, clock, NVIC */
+    System_Init();
+
+    /* Configure the SysTick */
+    SysTick_Config(System_Get_SystemClock() / RT_TICK_PER_SECOND);
+
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#ifdef RT_USING_HEAP
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SOC_SRAM_END_ADDR);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void *)SOC_SRAM_END_ADDR);
+#else
+    /* init memory system */
+    rt_system_heap_init((void *)&__bss_end, (void *)SOC_SRAM_END_ADDR);
+#endif
+#endif /* RT_USING_HEAP */
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+

bsp/acm32f4xx-nucleo/drivers/board.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-22     AisinoCip    add board.h to this bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtconfig.h>
+#include "ACM32Fxx_HAL.h"
+
+/*-------------------------- UART CONFIG BEGIN --------------------------*/
+
+/** After configuring corresponding UART or UART DMA, you can use it.
+  *
+  * STEP 1, define macro define related to the serial port opening based on the serial port number
+  *                 such as     #define BSP_USING_UATR1
+  *
+  * STEP 2, according to the corresponding pin of serial port, modify the related serial port information
+  *                 such as     #define UART1_TX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_RX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_TX_PIN        GPIO_PIN_X   ->   GPIO_PIN_9
+  *                             #define UART1_RX_PIN        GPIO_PIN_X   ->   GPIO_PIN_10
+  *
+  * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
+  *                 RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
+  *
+  * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
+  *                 such as     #define BSP_UART1_RX_USING_DMA
+  *
+  */
+
+#if defined(BSP_USING_UART1)
+    #define UART1_TX_PORT           GPIOA
+    #define UART1_RX_PORT           GPIOA
+    #define UART1_TX_PIN            GPIO_PIN_9
+    #define UART1_RX_PIN            GPIO_PIN_10
+
+    #if defined(BSP_UART1_RX_USING_DMA)
+        #define UART1_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART1_RX_DMA_RCC        BIT12
+        #define UART1_RX_DMA_IRQ        DMA_IRQn
+        #define UART1_RX_DMA_CHANNEL    0
+        #define UART1_RX_DMA_REQUEST    REQ6_UART1_RECV
+    #endif /* BSP_UART1_RX_USING_DMA */
+
+    #if defined(BSP_UART1_TX_USING_DMA)
+        #define UART1_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART1_TX_DMA_RCC        BIT12
+        #define UART1_TX_DMA_IRQ        DMA_IRQn
+        #define UART1_TX_DMA_CHANNEL    1
+        #define UART1_TX_DMA_REQUEST    REQ5_UART1_SEND
+    #endif /* BSP_UART1_TX_USING_DMA */
+
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+    #define UART2_TX_PORT           GPIOA
+    #define UART2_RX_PORT           GPIOA
+    #define UART2_TX_PIN            GPIO_PIN_2
+    #define UART2_RX_PIN            GPIO_PIN_3
+
+    #if defined(BSP_UART2_RX_USING_DMA)
+        #define UART2_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART2_RX_DMA_RCC        BIT12
+        #define UART2_RX_DMA_IRQ        DMA_IRQn
+        #define UART2_RX_DMA_CHANNEL    0
+        #define UART2_RX_DMA_REQUEST    REQ8_UART2_RECV
+    #endif /* BSP_UART2_RX_USING_DMA */
+
+    #if defined(BSP_UART2_TX_USING_DMA)
+        #define UART2_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART2_TX_DMA_RCC        BIT12
+        #define UART2_TX_DMA_IRQ        DMA_IRQn
+        #define UART2_TX_DMA_CHANNEL    1
+        #define UART2_TX_DMA_REQUEST    REQ7_UART2_SEND
+    #endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+    #define UART3_TX_PORT           GPIOB
+    #define UART3_RX_PORT           GPIOB
+    #define UART3_TX_PIN            GPIO_PIN_10
+    #define UART3_RX_PIN            GPIO_PIN_11
+
+    #if defined(BSP_UART3_RX_USING_DMA)
+        #define UART3_RX_DMA_INSTANCE   DMA_Channel2
+        #define UART3_RX_DMA_RCC        BIT12
+        #define UART3_RX_DMA_IRQ        DMA_IRQn
+        #define UART3_RX_DMA_CHANNEL    2
+        #define UART3_RX_DMA_REQUEST    REQ29_UART3_RECV
+    #endif /* BSP_UART3_RX_USING_DMA */
+
+    #if defined(BSP_UART3_TX_USING_DMA)
+        #define UART3_TX_DMA_INSTANCE   DMA_Channel3
+        #define UART3_TX_DMA_RCC        BIT12
+        #define UART3_TX_DMA_IRQ        DMA_IRQn
+        #define UART3_TX_DMA_CHANNEL    3
+        #define UART3_TX_DMA_REQUEST    REQ27_UART3_SEND
+    #endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+    #define UART4_TX_PORT           GPIOC
+    #define UART4_RX_PORT           GPIOC
+    #define UART4_TX_PIN            GPIO_PIN_10
+    #define UART4_RX_PIN            GPIO_PIN_11
+
+    #if defined(BSP_UART4_RX_USING_DMA)
+        #define UART4_RX_DMA_INSTANCE   DMA_Channel4
+        #define UART4_RX_DMA_RCC        BIT12
+        #define UART4_RX_DMA_IRQ        DMA_IRQn
+        #define UART4_RX_DMA_CHANNEL    4
+        #define UART4_RX_DMA_REQUEST    REQ46_UART4_RECV
+    #endif /* BSP_UART4_RX_USING_DMA */
+
+    #if defined(BSP_UART4_TX_USING_DMA)
+        #define UART4_TX_DMA_INSTANCE   DMA_Channel5
+        #define UART4_TX_DMA_RCC        BIT12
+        #define UART4_TX_DMA_IRQ        DMA_IRQn
+        #define UART4_TX_DMA_CHANNEL    5
+        #define UART4_TX_DMA_REQUEST    REQ45_UART4_SEND
+    #endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+/*-------------------------- UART CONFIG END --------------------------*/
+
+/* board configuration */
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
+

bsp/acm32f4xx-nucleo/drivers/drv_gpio.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-09-18     AisinoChip        first version
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include "board.h"
+
+#ifdef RT_USING_PIN
+
+#define __ACM32_PIN(index, gpio, gpio_index)                                \
+    {                                                                       \
+        index, GPIO##gpio, GPIO_PIN_##gpio_index                            \
+    }
+
+#define __ACM32_PIN_RESERVE                                                 \
+    {                                                                       \
+        -1, 0, 0                                                            \
+    }
+
+/* ACM32 GPIO driver */
+struct pin_index
+{
+    int             index;
+    enum_GPIOx_t    gpio;
+    uint32_t        pin;
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t         line;
+    EXTI_HandleTypeDef  handle;
+};
+
+static const struct pin_index pins[] =
+{
+#if defined(BSP_USING_GPIO1)
+    __ACM32_PIN(0,   A, 0),
+    __ACM32_PIN(1,   A, 1),
+    __ACM32_PIN(2,   A, 2),
+    __ACM32_PIN(3,   A, 3),
+    __ACM32_PIN(4,   A, 4),
+    __ACM32_PIN(5,   A, 5),
+    __ACM32_PIN(6,   A, 6),
+    __ACM32_PIN(7,   A, 7),
+    __ACM32_PIN(8,   A, 8),
+    __ACM32_PIN(9,   A, 9),
+    __ACM32_PIN(10,  A, 10),
+    __ACM32_PIN(11,  A, 11),
+    __ACM32_PIN(12,  A, 12),
+    __ACM32_PIN(13,  A, 13),
+    __ACM32_PIN(14,  A, 14),
+    __ACM32_PIN(15,  A, 15),
+    __ACM32_PIN(16,  B, 0),
+    __ACM32_PIN(17,  B, 1),
+    __ACM32_PIN(18,  B, 2),
+    __ACM32_PIN(19,  B, 3),
+    __ACM32_PIN(20,  B, 4),
+    __ACM32_PIN(21,  B, 5),
+    __ACM32_PIN(22,  B, 6),
+    __ACM32_PIN(23,  B, 7),
+    __ACM32_PIN(24,  B, 8),
+    __ACM32_PIN(25,  B, 9),
+    __ACM32_PIN(26,  B, 10),
+    __ACM32_PIN(27,  B, 11),
+    __ACM32_PIN(28,  B, 12),
+    __ACM32_PIN(29,  B, 13),
+    __ACM32_PIN(30,  B, 14),
+    __ACM32_PIN(31,  B, 15),
+#if defined(BSP_USING_GPIO2)
+    __ACM32_PIN(32,  C, 0),
+    __ACM32_PIN(33,  C, 1),
+    __ACM32_PIN(34,  C, 2),
+    __ACM32_PIN(35,  C, 3),
+    __ACM32_PIN(36,  C, 4),
+    __ACM32_PIN(37,  C, 5),
+    __ACM32_PIN(38,  C, 6),
+    __ACM32_PIN(39,  C, 7),
+    __ACM32_PIN(40,  C, 8),
+    __ACM32_PIN(41,  C, 9),
+    __ACM32_PIN(42,  C, 10),
+    __ACM32_PIN(43,  C, 11),
+    __ACM32_PIN(44,  C, 12),
+    __ACM32_PIN(45,  C, 13),
+    __ACM32_PIN(46,  C, 14),
+    __ACM32_PIN(47,  C, 15),
+    __ACM32_PIN(48,  D, 0),
+    __ACM32_PIN(49,  D, 1),
+    __ACM32_PIN(50,  D, 2),
+    __ACM32_PIN(51,  D, 3),
+    __ACM32_PIN(52,  D, 4),
+    __ACM32_PIN(53,  D, 5),
+    __ACM32_PIN(54,  D, 6),
+    __ACM32_PIN(55,  D, 7),
+    __ACM32_PIN(56,  D, 8),
+    __ACM32_PIN(57,  D, 9),
+    __ACM32_PIN(58,  D, 10),
+    __ACM32_PIN(59,  D, 11),
+    __ACM32_PIN(60,  D, 12),
+    __ACM32_PIN(61,  D, 13),
+    __ACM32_PIN(62,  D, 14),
+    __ACM32_PIN(63,  D, 15),
+#if defined(BSP_USING_GPIO3)
+    __ACM32_PIN(64,  E, 0),
+    __ACM32_PIN(65,  E, 1),
+    __ACM32_PIN(66,  E, 2),
+    __ACM32_PIN(67,  E, 3),
+    __ACM32_PIN(68,  E, 4),
+    __ACM32_PIN(69,  E, 5),
+    __ACM32_PIN(70,  E, 6),
+    __ACM32_PIN(71,  E, 7),
+    __ACM32_PIN(72,  E, 8),
+    __ACM32_PIN(73,  E, 9),
+    __ACM32_PIN(74,  E, 10),
+    __ACM32_PIN(75,  E, 11),
+    __ACM32_PIN(76,  E, 12),
+    __ACM32_PIN(77,  E, 13),
+    __ACM32_PIN(78,  E, 14),
+    __ACM32_PIN(79,  E, 15),
+    __ACM32_PIN(80,  F, 0),
+    __ACM32_PIN(81,  F, 1),
+    __ACM32_PIN(82,  F, 2),
+    __ACM32_PIN(83,  F, 3),
+    __ACM32_PIN(84,  F, 4),
+#endif /* defined(BSP_USING_GPIO3) */
+#endif /* defined(BSP_USING_GPIO2) */
+#endif /* defined(BSP_USING_GPIO1) */
+};
+
+static struct pin_irq_map pin_irq_map[] =
+{
+    {EXTI_LINE_0,  {0}},
+    {EXTI_LINE_1,  {0}},
+    {EXTI_LINE_2,  {0}},
+    {EXTI_LINE_3,  {0}},
+    {EXTI_LINE_4,  {0}},
+    {EXTI_LINE_5,  {0}},
+    {EXTI_LINE_6,  {0}},
+    {EXTI_LINE_7,  {0}},
+    {EXTI_LINE_8,  {0}},
+    {EXTI_LINE_9,  {0}},
+    {EXTI_LINE_10, {0}},
+    {EXTI_LINE_11, {0}},
+    {EXTI_LINE_12, {0}},
+    {EXTI_LINE_13, {0}},
+    {EXTI_LINE_14, {0}},
+    {EXTI_LINE_15, {0}},
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+static const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+
+    return index;
+};
+
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value);
+}
+
+static int _pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+
+    value = PIN_LOW;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+
+    value = HAL_GPIO_ReadPin(index->gpio, index->pin);
+
+    return value;
+}
+
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    GPIO_InitTypeDef GPIO_InitStruct;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    /* Configure GPIO_InitStructure */
+    GPIO_InitStruct.Pin = index->pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
+
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_PULLUP;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        /* output setting: od. */
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+
+    /* special PIN process */
+    __HAL_RTC_PC13_DIGIT();
+
+    HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
+}
+
+#define     PIN2INDEX(pin)      ((pin) % 16)
+
+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t _pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                     rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    GPIO_InitTypeDef GPIO_InitStruct;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+    irqmap = &pin_irq_map[irqindex];
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+
+        /* Configure GPIO_InitStructure */
+        GPIO_InitStruct.Pin = index->pin;
+        GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+
+        irqmap->handle.u32_Line = irqmap->line;
+        irqmap->handle.u32_Mode = EXTI_MODE_INTERRUPT;
+
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            GPIO_InitStruct.Pull = GPIO_PULLUP;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_FALLING;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            GPIO_InitStruct.Pull = GPIO_NOPULL;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING_FALLING;
+            break;
+        }
+        HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
+
+        irqmap->handle.u32_GPIOSel = pin / 16;
+
+        HAL_EXTI_SetConfigLine(&irqmap->handle);
+
+        pin_irq_enable_mask |= 1 << irqindex;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        if ((pin_irq_enable_mask & (1 << irqindex)) == 0)
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        EXTI->IENR &= ~irqmap->line;
+        EXTI->EENR &= ~irqmap->line;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops _acm32_pin_ops =
+{
+    _pin_mode,
+    _pin_write,
+    _pin_read,
+    _pin_attach_irq,
+    _pin_dettach_irq,
+    _pin_irq_enable,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+int rt_hw_pin_init(void)
+{
+    return rt_device_pin_register("pin", &_acm32_pin_ops, RT_NULL);
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+void EXTI_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    for (int i = 0; i < 16; i++)
+    {
+        if (EXTI->PDR & pin_irq_map[i].line)
+        {
+            EXTI->PDR = pin_irq_map[i].line;
+            pin_irq_hdr(i);
+            break;
+        }
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#endif /* RT_USING_PIN */
+

bsp/acm32f4xx-nucleo/drivers/drv_uart.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "uart_config.h"
+
+#ifdef RT_USING_SERIAL
+
+#ifdef RT_SERIAL_USING_DMA
+struct dma_config
+{
+    DMA_Channel_TypeDef *Instance;
+    rt_uint32_t         dma_rcc;
+    IRQn_Type           dma_irq;
+
+    rt_uint32_t         channel;
+    rt_uint32_t         request;
+};
+#endif
+
+#ifdef RT_SERIAL_USING_DMA
+    static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag);
+#endif /* RT_SERIAL_USING_DMA */
+
+struct acm32_uart_config
+{
+    const char          *name;
+    UART_TypeDef        *Instance;
+    IRQn_Type           irq_type;
+    enum_Enable_ID_t    enable_id;
+
+#ifdef RT_SERIAL_USING_DMA
+    struct dma_config   *dma_rx;
+    struct dma_config   *dma_tx;
+#endif
+
+    enum_GPIOx_t        tx_port;
+    enum_GPIOx_t        rx_port;
+    rt_uint32_t         tx_pin;
+    rt_uint32_t         rx_pin;
+};
+
+struct acm32_uart
+{
+    UART_HandleTypeDef          handle;
+    struct acm32_uart_config    *config;
+#ifdef RT_SERIAL_USING_DMA
+    struct
+    {
+        DMA_HandleTypeDef       handle;
+        rt_size_t               last_index;
+    } dma_rx;
+
+    struct
+    {
+        DMA_HandleTypeDef       handle;
+    } dma_tx;
+#endif
+
+    rt_uint16_t                 uart_dma_flag;
+    struct rt_serial_device     serial;
+};
+
+static rt_err_t uart_rx_indicate_cb(rt_device_t dev, rt_size_t size)
+{
+    return RT_EOK;
+}
+
+static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    uart->handle.Instance = uart->config->Instance;
+
+    uart->handle.Init.BaudRate = cfg->baud_rate;
+    if (cfg->data_bits == DATA_BITS_8)
+    {
+        uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
+    }
+    else     /* not support */
+    {
+        return -RT_EINVAL;
+    }
+
+    if (cfg->stop_bits == STOP_BITS_1)
+    {
+        uart->handle.Init.StopBits = UART_STOPBITS_1;
+    }
+    else if (cfg->stop_bits == STOP_BITS_2)
+    {
+        uart->handle.Init.StopBits = UART_STOPBITS_2;
+    }
+    else     /* not support */
+    {
+        return -RT_EINVAL;
+    }
+
+    if (cfg->parity == PARITY_NONE)
+    {
+        uart->handle.Init.Parity = UART_PARITY_NONE;
+    }
+    else if (cfg->parity == PARITY_ODD)
+    {
+        uart->handle.Init.Parity = UART_PARITY_ODD;
+    }
+    else if (cfg->parity == PARITY_EVEN)
+    {
+        uart->handle.Init.Parity = UART_PARITY_EVEN;
+    }
+    else     /* not support */
+    {
+        return -RT_EINVAL;
+    }
+
+    uart->handle.Init.Mode       = UART_MODE_TX_RX;
+    uart->handle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
+
+    HAL_UART_Init(&uart->handle);
+
+    uart->handle.Instance->LCRH &= ~UART_LCRH_FEN;
+    return RT_EOK;
+}
+
+static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct acm32_uart *uart;
+#ifdef RT_SERIAL_USING_DMA
+    rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+#endif
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    switch (cmd)
+    {
+    /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        NVIC_DisableIRQ(uart->config->irq_type);
+        /* Disable RX interrupt */
+        uart->handle.Instance->IE &= ~UART_IE_RXI;
+        break;
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        NVIC_EnableIRQ(uart->config->irq_type);
+        /* Enable RX interrupt */
+        uart->handle.Instance->IE |= UART_IE_RXI;
+        break;
+#ifdef RT_SERIAL_USING_DMA
+    /* UART config */
+    case RT_DEVICE_CTRL_CONFIG :
+        DMA_Configuration(serial, (rt_uint32_t)ctrl_arg);
+        rt_device_set_rx_indicate((rt_device_t)serial, uart_rx_indicate_cb);
+        break;
+#endif /* RT_SERIAL_USING_DMA */
+    }
+    return RT_EOK;
+}
+
+static int _uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    while (uart->handle.Instance->FR & UART_FR_TXFF);    /* wait Tx FIFO not full */
+    uart->handle.Instance->DR = c;
+    while ((uart->handle.Instance->FR & UART_FR_BUSY)); /* wait TX Complete */
+
+    return 1;
+}
+
+static int _uart_getc(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart;
+
+    int ch;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    ch = -1;
+    if (!(uart->handle.Instance->FR & UART_FR_RXFE))   /* Rx FIFO not empty */
+    {
+        ch = uart->handle.Instance->DR & 0xff;
+    }
+
+    return ch;
+}
+
+#ifdef RT_SERIAL_USING_DMA
+/**
+ * Serial port receive idle process. This need add to uart idle ISR.
+ *
+ * @param serial serial device
+ */
+static void dma_uart_rx_idle_isr(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    rt_size_t recv_total_index, recv_len;
+    rt_base_t level;
+
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
+
+    recv_total_index = uart->handle.lu32_RxSize - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
+    recv_len = recv_total_index - uart->handle.lu32_RxCount;
+    uart->handle.lu32_RxCount = recv_total_index;
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
+
+    if (recv_len)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+    }
+}
+
+/*
+ DMA receive done process. This need add to DMA receive done ISR.
+
+ @param serial serial device
+*/
+static void dma_rx_done_isr(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart;
+    struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    rt_size_t recv_len;
+    rt_base_t level;
+
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
+
+    recv_len = serial->config.bufsz - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
+    uart->dma_rx.last_index = 0;
+
+    DMA->INT_TC_CLR |= 1 << (uart->config->dma_rx->channel);      /* clear channel0 TC flag */
+
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
+
+    if (recv_len)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+    }
+
+    HAL_UART_Receive_DMA(&(uart->handle), &rx_fifo->buffer[rx_fifo->put_index], serial->config.bufsz);
+}
+
+static rt_size_t _uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+{
+    struct acm32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    if (size == 0)
+    {
+        return 0;
+    }
+
+    if (RT_SERIAL_DMA_TX == direction)
+    {
+        if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
+            return size;
+        }
+        else
+        {
+            return 0;
+        }
+    }
+    return 0;
+}
+
+#endif /* RT_SERIAL_USING_DMA */
+
+static const struct rt_uart_ops acm32_uart_ops =
+{
+    _uart_configure,
+    _uart_control,
+    _uart_putc,
+    _uart_getc,
+#ifdef RT_SERIAL_USING_DMA
+    _uart_dma_transmit,
+#endif
+};
+
+#ifdef RT_SERIAL_USING_DMA
+static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag)
+{
+    struct rt_serial_rx_fifo *rx_fifo;
+    DMA_HandleTypeDef *DMA_Handle;
+    struct dma_config *dma_config;
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        DMA_Handle = &uart->dma_rx.handle;
+        dma_config = uart->config->dma_rx;
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+        DMA_Handle = &uart->dma_tx.handle;
+        dma_config = uart->config->dma_tx;
+    }
+    else
+    {
+        return;
+    }
+
+    DMA_Handle->Instance                 = dma_config->Instance;
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        DMA_Handle->Init.Data_Flow          = DMA_DATA_FLOW_P2M;
+        DMA_Handle->Init.Mode               = DMA_NORMAL;
+        DMA_Handle->Init.Source_Inc         = DMA_SOURCE_ADDR_INCREASE_DISABLE;
+        DMA_Handle->Init.Desination_Inc     = DMA_DST_ADDR_INCREASE_ENABLE;
+
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+        DMA_Handle->Init.Data_Flow          = DMA_DATA_FLOW_M2P;
+        DMA_Handle->Init.Mode               = DMA_NORMAL;
+        DMA_Handle->Init.Source_Inc         = DMA_SOURCE_ADDR_INCREASE_ENABLE;
+        DMA_Handle->Init.Desination_Inc     = DMA_DST_ADDR_INCREASE_DISABLE;
+    }
+
+    DMA_Handle->Init.Request_ID             = dma_config->request;
+    DMA_Handle->Init.Source_Width           = DMA_SRC_WIDTH_BYTE;
+    DMA_Handle->Init.Desination_Width       = DMA_DST_WIDTH_BYTE;
+
+    if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
+    {
+        RT_ASSERT(0);
+    }
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        __HAL_LINK_DMA(uart->handle, HDMA_Rx, uart->dma_rx.handle);
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+        __HAL_LINK_DMA(uart->handle, HDMA_Tx, uart->dma_tx.handle);
+    }
+    /* enable interrupt */
+    if (flag == RT_DEVICE_FLAG_DMA_RX)
+    {
+        rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+        /* Start DMA transfer */
+        if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
+        {
+            /* Transfer error in reception process */
+            RT_ASSERT(0);
+        }
+
+    }
+}
+#endif /* RT_SERIAL_USING_DMA */
+
+enum
+{
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_INDEX,
+#endif
+#ifdef BSP_USING_UART4
+    UART4_INDEX,
+#endif
+    UART_MAX_INDEX,
+};
+
+static struct acm32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART1
+    UART1_CONFIG,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_CONFIG,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_CONFIG,
+#endif
+#ifdef BSP_USING_UART4
+    UART4_CONFIG,
+#endif
+};
+
+static struct acm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+#ifdef RT_SERIAL_USING_DMA
+static void uart_get_dma_config(void)
+{
+#if defined(BSP_USING_UART1)
+#if defined(BSP_UART1_RX_USING_DMA)
+    static struct dma_config uart1_rx_dma_conf = UART1_DMA_RX_CONFIG;
+    uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART1_INDEX].dma_rx = &uart1_rx_dma_conf;
+#endif /* BSP_UART1_RX_USING_DMA */
+#if defined(BSP_UART1_TX_USING_DMA)
+    static struct dma_config uart1_tx_dma_conf = UART1_DMA_TX_CONFIG;
+    uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART1_INDEX].dma_tx = &uart1_tx_dma_conf;
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#if defined(BSP_UART2_RX_USING_DMA)
+    static struct dma_config uart2_rx_dma_conf = UART2_DMA_RX_CONFIG;
+    uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART2_INDEX].dma_rx = &uart2_rx_dma_conf;
+#endif /* BSP_UART2_RX_USING_DMA */
+#if defined(BSP_UART2_TX_USING_DMA)
+    static struct dma_config uart2_tx_dma_conf = UART2_DMA_TX_CONFIG;
+    uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART2_INDEX].dma_tx = &uart2_tx_dma_conf;
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#if defined(BSP_UART3_RX_USING_DMA)
+    static struct dma_config uart3_rx_dma_conf = UART3_DMA_RX_CONFIG;
+    uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART3_INDEX].dma_rx = &uart3_rx_dma_conf;
+#endif /* BSP_UART3_RX_USING_DMA */
+#if defined(BSP_UART3_TX_USING_DMA)
+    static struct dma_config uart3_tx_dma_conf = UART3_DMA_TX_CONFIG;
+    uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART3_INDEX].dma_tx = &uart3_tx_dma_conf;
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#if defined(BSP_UART4_RX_USING_DMA)
+    static struct dma_config uart4_rx_dma_conf = UART4_DMA_RX_CONFIG;
+    uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART4_INDEX].dma_rx = &uart4_rx_dma_conf;
+#endif /* BSP_UART4_RX_USING_DMA */
+#if defined(BSP_UART3_TX_USING_DMA)
+    static struct dma_config uart4_tx_dma_conf = UART4_DMA_TX_CONFIG;
+    uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART4_INDEX].dma_tx = &uart4_tx_dma_conf;
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+}
+#endif
+
+rt_err_t rt_hw_uart_init(void)
+{
+    rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct acm32_uart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t rc = RT_EOK;
+
+#ifdef RT_SERIAL_USING_DMA
+    uart_get_dma_config();
+#endif
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        uart_obj[i].config          = &uart_config[i];
+
+        uart_obj[i].serial.ops      = &acm32_uart_ops;
+        uart_obj[i].serial.config   = config;
+
+        /* register UART device */
+        rc = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
+                                   RT_DEVICE_FLAG_RDWR
+                                   | RT_DEVICE_FLAG_INT_RX
+                                   | RT_DEVICE_FLAG_INT_TX
+                                   | uart_obj[i].uart_dma_flag
+                                   , NULL);
+        RT_ASSERT(rc == RT_EOK);
+    }
+
+    return rc;
+}
+
+static void uart_isr(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    RT_ASSERT(serial != RT_NULL);
+
+    /* receive interrupt enabled */
+    if (uart->handle.Instance->IE & UART_IE_RXI)
+    {
+        if (uart->handle.Instance->RIS & UART_RIS_RXI)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        }
+    }
+
+#ifdef RT_SERIAL_USING_DMA
+    if (uart->handle.Instance->IE & UART_IE_RTI)   /* Receive TimeOut Interrupt */
+    {
+        dma_uart_rx_idle_isr(serial);
+        /* Clear RTI Status */
+        uart->handle.Instance->ICR = UART_ICR_RTI;
+    }
+#endif /* RT_SERIAL_USING_DMA */
+
+    if (uart->handle.Instance->IE & UART_IE_TXI && \
+            uart->handle.Instance->RIS & UART_RIS_TXI)
+    {
+        /* Clear TXI Status */
+        uart->handle.Instance->ICR = UART_ICR_TXI;
+        if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
+        }
+        /* Disable TX interrupt */
+        uart->handle.Instance->IE &= ~UART_IE_TXI;
+    }
+}
+
+#if defined(BSP_USING_UART1)
+void UART1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART1_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+void UART2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART2_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+void UART3_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART3_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+void UART4_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART4_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART4 */
+
+#ifdef RT_SERIAL_USING_DMA
+void DMA_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    for (int i = 0; i < UART_MAX_INDEX; i++)
+    {
+        if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_rx->channel))
+        {
+            dma_rx_done_isr(&uart_obj[i].serial);
+            break;
+        }
+
+        if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_tx->channel))
+        {
+            DMA->INT_TC_CLR |= 1 << (uart_obj[i].config->dma_tx->channel);      /* clear channel0 TC flag */
+            break;
+        }
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_SERIAL_USING_DMA */
+
+void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+    struct acm32_uart *uart;
+    GPIO_InitTypeDef  GPIO_Uart;
+
+    RT_ASSERT(huart != RT_NULL);
+
+    /* get uart object */
+    uart = rt_container_of(huart, struct acm32_uart, handle);
+
+    /* Enable Clock */
+    System_Module_Enable(uart->config->enable_id);
+
+    /* Initialization GPIO */
+    GPIO_Uart.Pin       = uart->config->tx_pin;
+    GPIO_Uart.Mode      = GPIO_MODE_AF_PP;
+    GPIO_Uart.Pull      = GPIO_PULLUP;
+    GPIO_Uart.Alternate = GPIO_FUNCTION_2;
+    HAL_GPIO_Init(uart->config->tx_port, &GPIO_Uart);
+
+    GPIO_Uart.Pin       = uart->config->rx_pin;
+    GPIO_Uart.Mode      = GPIO_MODE_AF_PP;
+    GPIO_Uart.Pull      = GPIO_PULLUP;
+    GPIO_Uart.Alternate = GPIO_FUNCTION_2;
+    HAL_GPIO_Init(uart->config->rx_port, &GPIO_Uart);
+
+    /* NVIC Config */
+    NVIC_ClearPendingIRQ(uart->config->irq_type);
+    NVIC_SetPriority(uart->config->irq_type, 5);
+    NVIC_EnableIRQ(uart->config->irq_type);
+}
+
+#endif /* RT_USING_SEARIAL */
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0007FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0800;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.lds

+/*
+ * linker script for ACM32F4xx with GNU ld
+ */
+
+/* describes the location and size of blocks of memory in the target. */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 512KB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */
+}
+/* Program Entry, set to mark it as "used" and avoid gc */
+ENTRY(Reset_Handler)
+_system_stack_size = 0x800;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(8);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00030000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/acm32f4xx-nucleo/drivers/uart_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "board.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(RT_USING_SERIAL)
+
+#if defined(BSP_USING_UART1)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = UART1,                                          \
+        .irq_type = UART1_IRQn,                                     \
+        .enable_id = EN_UART1,                                      \
+        .tx_port  = UART1_TX_PORT,                                  \
+        .rx_port  = UART1_RX_PORT,                                  \
+        .tx_pin   = UART1_TX_PIN,                                   \
+        .rx_pin   = UART1_RX_PIN,                                   \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+        .channel  = UART2_RX_DMA_CHANNEL,                           \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+        .channel  = UART2_TX_DMA_CHANNEL,                           \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = UART2,                                          \
+        .irq_type = UART2_IRQn,                                     \
+        .enable_id = EN_UART2,                                      \
+        .tx_port  = UART2_TX_PORT,                                  \
+        .rx_port  = UART2_RX_PORT,                                  \
+        .tx_pin   = UART2_TX_PIN,                                   \
+        .rx_pin   = UART2_RX_PIN,                                   \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+        .channel  = UART3_RX_DMA_CHANNEL,                           \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+        .channel  = UART3_TX_DMA_CHANNEL,                           \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = UART3,                                          \
+        .irq_type = UART3_IRQn,                                     \
+        .enable_id = EN_UART3,                                      \
+        .tx_port  = UART3_TX_PORT,                                  \
+        .rx_port  = UART3_RX_PORT,                                  \
+        .tx_pin   = UART3_TX_PIN,                                   \
+        .rx_pin   = UART3_RX_PIN,                                   \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+        .channel  = UART4_RX_DMA_CHANNEL,                           \
+        .request  = UART4_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_TX_DMA_RCC,                               \
+        .dma_irq  = UART4_TX_DMA_IRQ,                               \
+        .channel  = UART4_TX_DMA_CHANNEL,                           \
+        .request  = UART4_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+        .enable_id = EN_UART4,                                      \
+        .tx_port  = UART4_TX_PORT,                                  \
+        .rx_port  = UART4_RX_PORT,                                  \
+        .tx_pin   = UART4_TX_PIN,                                   \
+        .rx_pin   = UART4_RX_PIN,                                   \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RT_USING_SERIAL */
+
+#endif /* __UART_CONFIG_H__ */
+

bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_compiler.h

+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_version.h

+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.3
+ * @date     24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/acm32f4xx-nucleo/libraries/CMSIS/mpu_armv8.h

+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4.s

+;* File Name          : Startup_ACM32F4.s
+;* Version            : V1.0.0
+;* Date               : 2020
+;* Description        : ACM32F4 Devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* All rights reserved.
+;*******************************************************************************
+
+Stack_Size      EQU     0x00000800
+Heap_Size       EQU     0x00000000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT __Vectors
+
+__Vectors       
+                DCD     __initial_sp                    ; Top of Stack
+                DCD     Reset_Handler                   ; Reset Handler
+                DCD     NMI_Handler                     ; NMI Handler
+                DCD     HardFault_Handler               ; Hard Fault Handler
+                DCD     MemManage_Handler               ; MPU Fault Handler
+                DCD     BusFault_Handler                ; Bus Fault Handler
+                DCD     UsageFault_Handler              ; Usage Fault Handler
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     SVC_Handler                     ; SVCall Handler
+                DCD     DebugMon_Handler                ; Debug Monitor Handler
+                DCD     0                               ; Reserved
+                DCD     PendSV_Handler                  ; PendSV Handler
+                DCD     SysTick_Handler                 ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler                  ; 0:  WDT_IRQHandler
+                DCD     RTC_IRQHandler                  ; 1:  RTC_IRQHandler
+                DCD     EFC_IRQHandler                  ; 2:  EFC_IRQHandler
+                DCD     GPIOAB_IRQHandler               ; 3:  GPIOAB_IRQHandler
+                DCD     GPIOCD_IRQHandler               ; 4:  GPIOCD_IRQHandler
+                DCD     EXTI_IRQHandler                 ; 5:  EXTI_IRQHandler 
+                DCD     SRAM_PARITY_IRQHandler          ; 6:  SRAM_PARITY_IRQHandler
+                DCD     CLKRDY_IRQHandler               ; 7:  CLKRDY_IRQHandler
+                DCD     UART4_IRQHandler                ; 8:  UART4_IRQHandler
+                DCD     DMA_IRQHandler                  ; 9:  DMA_IRQHandler
+                DCD     UART3_IRQHandler                ; 10: UART3_IRQHandler
+                DCD     RSV_IRQHandler                  ; 11: RSV
+                DCD     ADC_IRQHandler                  ; 12: ADC_IRQHandler
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler  ; 13: TIM1_BRK_UP_TRG_COM_IRQHandler
+                DCD     TIM1_CC_IRQHandler              ; 14: TIM1_CC_IRQHandler
+                DCD     TIM2_IRQHandler                 ; 15: TIM2_IRQHandler
+                DCD     TIM3_IRQHandler                 ; 16: TIM3_IRQHandler 
+                DCD     TIM6_IRQHandler                 ; 17: TIM6_IRQHandler
+                DCD     TIM7_IRQHandler                 ; 18: TIM7_IRQHandler
+                DCD     TIM14_IRQHandler                ; 19: TIM14_IRQHandler
+                DCD     TIM15_IRQHandler                ; 20: TIM15_IRQHandler
+                DCD     TIM16_IRQHandler                ; 21: TIM16_IRQHandler
+                DCD     TIM17_IRQHandler                ; 22: TIM17_IRQHandler
+                DCD     I2C1_IRQHandler                 ; 23: I2C1_IRQHandler
+                DCD     I2C2_IRQHandler                 ; 24: I2C2_IRQHandler
+                DCD     SPI1_IRQHandler                 ; 25: SPI1_IRQHandler
+                DCD     SPI2_IRQHandler                 ; 26: SPI2_IRQHandler
+                DCD     UART1_IRQHandler                ; 27: UART1_IRQHandler
+                DCD     UART2_IRQHandler                ; 28: UART2_IRQHandler
+                DCD     LPUART_IRQHandler               ; 29: LPUART_IRQHandler
+                DCD     SPI3_IRQHandler                 ; 30: SPI3_IRQHandler
+                DCD     AES_IRQHandler                  ; 31: AES_IRQHandler
+                DCD     USB_IRQHandler                  ; 32: USB_IRQHandler
+                DCD     DAC_IRQHandler                  ; 33: DAC_IRQHandler
+                DCD     I2S_IRQHandler                  ; 34: I2S_IRQHandler
+                DCD     GPIOEF_IRQHandler               ; 35: GPIOEF_IRQHandler
+                DCD     CAN1_IRQHandler                 ; 36: CAN1_IRQHandler
+                DCD     CAN2_IRQHandler                 ; 37: CAN2_IRQHandler
+                DCD     FPU_IRQHandler                  ; 38: FPU_IRQHandler
+                DCD     TIM4_IRQHandler                 ; 39: TIM4_IRQHandler 
+                DCD     SPI4_IRQHandler                 ; 40: SPI4_IRQHandler
+                AREA    |.text|, CODE, READONLY
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  System_Core_Config
+                IMPORT  __main
+                LDR     R0, =System_Core_Config
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT   WDT_IRQHandler                 [WEAK]
+                EXPORT   RTC_IRQHandler                 [WEAK]
+                EXPORT   EFC_IRQHandler                 [WEAK]
+                EXPORT   GPIOAB_IRQHandler              [WEAK]
+                EXPORT   GPIOCD_IRQHandler              [WEAK]
+                EXPORT   EXTI_IRQHandler                [WEAK]
+                EXPORT   SRAM_PARITY_IRQHandler         [WEAK]
+                EXPORT   CLKRDY_IRQHandler              [WEAK]
+                EXPORT   UART4_IRQHandler               [WEAK]
+                EXPORT   DMA_IRQHandler                 [WEAK]
+                EXPORT   UART3_IRQHandler               [WEAK]
+                EXPORT   RSV_IRQHandler                 [WEAK]
+                EXPORT   ADC_IRQHandler                 [WEAK]
+                EXPORT   TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+                EXPORT   TIM1_CC_IRQHandler             [WEAK]
+                EXPORT   TIM2_IRQHandler                [WEAK]
+                EXPORT   TIM3_IRQHandler                [WEAK]
+                EXPORT   TIM6_IRQHandler                [WEAK]
+                EXPORT   TIM7_IRQHandler                [WEAK]
+                EXPORT   TIM14_IRQHandler               [WEAK]
+                EXPORT   TIM15_IRQHandler               [WEAK]
+                EXPORT   TIM16_IRQHandler               [WEAK]
+                EXPORT   TIM17_IRQHandler               [WEAK]
+                EXPORT   I2C1_IRQHandler                [WEAK]
+                EXPORT   I2C2_IRQHandler                [WEAK]
+                EXPORT   SPI1_IRQHandler                [WEAK]
+                EXPORT   SPI2_IRQHandler                [WEAK]
+                EXPORT   UART1_IRQHandler               [WEAK]
+                EXPORT   UART2_IRQHandler               [WEAK]
+                EXPORT   LPUART_IRQHandler              [WEAK]
+                EXPORT   SPI3_IRQHandler                [WEAK]
+                EXPORT   AES_IRQHandler                 [WEAK]
+                EXPORT   USB_IRQHandler                 [WEAK]
+                EXPORT   RSV_IRQHandler                 [WEAK]
+                EXPORT   DAC_IRQHandler                 [WEAK]
+                EXPORT   I2S_IRQHandler                 [WEAK]
+                EXPORT   GPIOEF_IRQHandler              [WEAK]
+                EXPORT   CAN1_IRQHandler                [WEAK]
+                EXPORT   CAN2_IRQHandler                [WEAK]
+                EXPORT   FPU_IRQHandler                 [WEAK]
+                EXPORT   TIM4_IRQHandler                [WEAK]
+                EXPORT   SPI4_IRQHandler                [WEAK]
+WDT_IRQHandler
+RTC_IRQHandler
+EFC_IRQHandler
+GPIOAB_IRQHandler
+GPIOCD_IRQHandler
+EXTI_IRQHandler
+SRAM_PARITY_IRQHandler
+CLKRDY_IRQHandler
+UART4_IRQHandler
+DMA_IRQHandler
+UART3_IRQHandler
+ADC_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+LPUART_IRQHandler
+SPI3_IRQHandler
+AES_IRQHandler
+USB_IRQHandler
+RSV_IRQHandler
+DAC_IRQHandler
+I2S_IRQHandler
+GPIOEF_IRQHandler
+CAN1_IRQHandler
+CAN2_IRQHandler
+FPU_IRQHandler
+TIM4_IRQHandler
+SPI4_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 
+                IF      :DEF:__MICROLIB
+                 
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                 
+                ELSE
+                 
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+                 
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+                END

bsp/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h

+/*
+  ******************************************************************************
+  * @file    System_Accelerate.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   MCU Accelerate Peripheral Access Layer System header File.
+  ******************************************************************************
+*/
+#ifndef __SYSTEM_ACCELERATE_H__
+#define __SYSTEM_ACCELERATE_H__
+
+
+
+/* System_EnableIAccelerate */ 
+void System_EnableIAccelerate(void);
+
+/* System_DisableIAccelerate */
+void System_DisableIAccelerate(void);
+
+/* System_EnableDAccelerate */
+void System_EnableDAccelerate(void);
+
+/* System_DisableDAccelerate */
+void System_DisableDAccelerate(void);
+
+
+#endif
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h

+/*
+  ******************************************************************************
+  * @file    ACM32Fxx_HAL.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   HAL Config header file.
+  ******************************************************************************
+*/
+#ifndef __ACM32FXX_HAL_H__
+#define __ACM32FXX_HAL_H__
+
+/* 
+    Uncomment the line below according to the target device used in your application 
+*/
+/* #define ACM32F3XX */    /*!< ACM32F303xx */
+   #define ACM32F4XX       /*!< ACM32F403xx */
+/* #define ACM32FPXX */    /*!< ACM32FP400xx ACM32FP401xx */
+
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(ACM32F3XX)
+    #include "ACM32F3.h"
+#elif defined(ACM32F4XX)
+    #include "ACM32F4.h"
+#elif defined(ACM32FPXX)
+    #include "ACM32FP.h"
+#else
+    #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)"
+#endif
+/**
+  * @}
+  */
+
+
+/*
+ * @brief  HAL Status structures definition
+ */
+typedef enum
+{
+    HAL_OK       = 0x00U,
+    HAL_ERROR    = 0x01U,
+    HAL_BUSY     = 0x02U,
+    HAL_TIMEOUT  = 0x03U
+}HAL_StatusTypeDef;
+
+
+//#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __weak
+    #define __weak  __attribute__((weak))
+  #endif
+//#endif
+
+
+/* USE FULL ASSERT */
+#define USE_FULL_ASSERT    (1)
+
+
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDT_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_EFLASH_MODULE_ENABLED
+#ifdef  ACM32F4XX
+#define HAL_OPA_MODULE_ENABLED
+#endif
+#ifndef ACM32FPXX
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#endif
+#define HAL_LPUART_MODULE_ENABLED
+#define HAL_WDT_MODULE_ENABLED 
+#define HAL_FSUSB_MODULE_ENABLED
+#define HAL_SYSTICK_ENABLED
+#define HAL_CRC_ENABLED  
+#define HAL_FAU_ENABLED  
+#define HAL_AES_ENABLED  
+#define HAL_HASH_SHA1_ENABLED 
+#define HAL_HASH_SHA256_ENABLED 
+#define HAL_HRNG_ENABLED  
+
+#if defined(ACM32F3XX)
+    #include "System_ACM32F3.h"
+#elif defined(ACM32F4XX)
+    #include "System_ACM32F4.h"
+#elif defined(ACM32FPXX)
+    #include "System_ACM32FP.h"
+#else
+    #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)"
+#endif
+
+#include "System_Accelerate.h"
+
+#ifdef HAL_DMA_MODULE_ENABLED
+    #include "HAL_DMA.h"
+#endif
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+    #include "HAL_GPIO.h"
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+    #include "HAL_UART.h"
+    #include "HAL_UART_EX.h"
+#endif
+
+#ifdef HAL_ADC_MODULE_ENABLED
+    #include "HAL_ADC.h"
+#endif
+
+#ifdef HAL_DAC_MODULE_ENABLED
+    #include "HAL_DAC.h"
+#endif
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+    #include "HAL_EXTI.h"
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+    #include "HAL_I2C.h"
+#endif
+
+#ifdef HAL_I2S_MODULE_ENABLED
+    #include "HAL_I2S.h"
+#endif
+
+#ifdef HAL_RTC_MODULE_ENABLED
+    #include "HAL_RTC.h"
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+    #include "HAL_SPI.h"
+#endif
+
+#ifdef HAL_IWDT_MODULE_ENABLED
+    #include "HAL_IWDT.h"
+#endif
+
+#ifdef HAL_EFLASH_MODULE_ENABLED
+    #include "HAL_EFlash.h"
+    #include "HAL_EFlash_EX.h"
+#endif
+
+#ifdef HAL_OPA_MODULE_ENABLED
+    #include "HAL_OPA.h"
+#endif
+
+#ifdef HAL_COMP_MODULE_ENABLED
+    #include "HAL_COMP.h"
+#endif
+
+#ifdef HAL_CAN_MODULE_ENABLED
+    #include "HAL_CAN.h"
+#endif
+
+#ifdef HAL_LPUART_MODULE_ENABLED
+    #include "HAL_LPUART.h"
+#endif
+
+#ifdef HAL_WDT_MODULE_ENABLED
+    #include "HAL_WDT.h"
+#endif
+
+#ifdef HAL_TIMER_MODULE_ENABLED
+    #include "HAL_TIMER.h"  
+    #include "HAL_TIMER_EX.h"
+#endif  
+
+#ifdef HAL_FSUSB_MODULE_ENABLED
+    #include "HAL_FSUSB.h"
+#endif
+
+#ifdef HAL_CRC_ENABLED  
+#include  "HAL_CRC.h"
+#endif  
+
+#ifdef  HAL_AES_ENABLED
+#include  "HAL_AES.h"  
+#endif    
+
+#ifdef HAL_FAU_ENABLED    
+#include  "HAL_FAU.h"       
+#endif 
+
+#ifdef HAL_HASH_SHA1_ENABLED 
+#include "HAL_SHA1.h"  
+#endif 
+
+#ifdef HAL_HASH_SHA256_ENABLED 
+#include "HAL_SHA256.h"  
+#endif  
+
+#ifdef HAL_HRNG_ENABLED     
+#include "HAL_HRNG.h"    
+#endif    
+
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h

+/*
+  ******************************************************************************
+  * @file    HAL_EFlash_EX.h
+  * @version V1.0.0
+  * @date    2021
+  * @brief   Header file of EFlash extention module   
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_EX_H__
+#define __HAL_EFlash_EX_H__
+
+#include "stdint.h"
+
+/* HAL_EFlash_Return_To_Boot */
+void HAL_EFlash_Return_to_Boot(void);
+
+/* HAL_EFlash_Init_Para */ 
+void HAL_EFlash_Init_Para(uint32_t fu32_freq);   
+
+/* HAL_EFlash_ErasePage_EX */   
+void HAL_EFlash_ErasePage_EX(uint32_t fu32_Addr);  
+
+/* HAL_EFlash_Program_Word_EX */     
+void HAL_EFlash_Program_Word_EX(uint32_t fu32_Addr, uint32_t fu32_Data);  
+
+#endif