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提交 314bcbd3 编写于 作者: O onelife.real
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*** EFM32 branch *** 

 - New branch for Energy Micro's MCUs (http://energymicro.com/).
 - Target board: FM32 Gecko Starter Kit (http://www.energymicro.com/tools)

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1274 bbd45198-f89e-11dd-88c7-29a3b14d5316
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bsp/efm32/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c 0 → 100644
浏览文件 @ 314bcbd3
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
register uint32_t result __ASM ("r0") = 0;
__ASM volatile ("MRS %0, psp\n"
"BX lr \n" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack);
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n"
"BX lr \n" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
register uint32_t result __ASM ("r0") = 0;
__ASM volatile ("MRS %0, msp\n"
"BX lr \n" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack);
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n"
"BX lr \n" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
bsp/efm32/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h 0 → 100644
浏览文件 @ 314bcbd3
此差异已折叠。
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32.h 0 → 100644
浏览文件 @ 314bcbd3
/**************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 Gxxx Device series
*
* This is a convenience header file for defining the EFM32 part number on the
* build command line, instead of specifying the part specific header file.
* @verbatim
* Example: Add "-DEFM32G890F128" to your build options, to define part
* Add "#include "efm32.h" to your source files
* @endverbatim
* @author Energy Micro AS
* @version 1.3.0
******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#ifndef __EFM32_H
#define __EFM32_H
/* Gecko Parts */
#if defined(EFM32G200F16)
#include "efm32g200f16.h"
#elif defined(EFM32G200F32)
#include "efm32g200f32.h"
#elif defined(EFM32G200F64)
#include "efm32g200f64.h"
#elif defined(EFM32G210F128)
#include "efm32g210f128.h"
#elif defined(EFM32G230F128)
#include "efm32g230f128.h"
#elif defined(EFM32G230F32)
#include "efm32g230f32.h"
#elif defined(EFM32G230F64)
#include "efm32g230f64.h"
#elif defined(EFM32G280F128)
#include "efm32g280f128.h"
#elif defined(EFM32G280F32)
#include "efm32g280f32.h"
#elif defined(EFM32G280F64)
#include "efm32g280f64.h"
#elif defined(EFM32G290F128)
#include "efm32g290f128.h"
#elif defined(EFM32G290F32)
#include "efm32g290f32.h"
#elif defined(EFM32G290F64)
#include "efm32g290f64.h"
#elif defined(EFM32G840F128)
#include "efm32g840f128.h"
#elif defined(EFM32G840F32)
#include "efm32g840f32.h"
#elif defined(EFM32G840F64)
#include "efm32g840f64.h"
#elif defined(EFM32G880F128)
#include "efm32g880f128.h"
#elif defined(EFM32G880F32)
#include "efm32g880f32.h"
#elif defined(EFM32G880F64)
#include "efm32g880f64.h"
#elif defined(EFM32G890F128)
#include "efm32g890f128.h"
#elif defined(EFM32G890F32)
#include "efm32g890f32.h"
#elif defined(EFM32G890F64)
#include "efm32g890f64.h"
#else
#error "efm32.h: PART NUMBER undefined"
#endif
#endif
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/arm/startup_efm32.s 0 → 100644
浏览文件 @ 314bcbd3
;/*****************************************************************************
; * @file: startup_efm32.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the Energy Micro EFM32 device series
; * @version 1.3.0
; * @date: 7. September 2010
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2008 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA_IRQHandler ; 0: DMA Interrupt
DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt
DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt
DCD ACMP0_IRQHandler ; 5: ACMP0 Interrupt
DCD ADC0_IRQHandler ; 6: ADC0 Interrupt
DCD DAC0_IRQHandler ; 7: DAC0 Interrupt
DCD I2C0_IRQHandler ; 8: I2C0 Interrupt
DCD GPIO_ODD_IRQHandler ; 9: GPIO_ODD Interrupt
DCD TIMER1_IRQHandler ; 10: TIMER1 Interrupt
DCD TIMER2_IRQHandler ; 11: TIMER2 Interrupt
DCD USART1_RX_IRQHandler ; 12: USART1_RX Interrupt
DCD USART1_TX_IRQHandler ; 13: USART1_TX Interrupt
DCD USART2_RX_IRQHandler ; 14: USART2_RX Interrupt
DCD USART2_TX_IRQHandler ; 15: USART2_TX Interrupt
DCD UART0_RX_IRQHandler ; 16: UART0_RX Interrupt
DCD UART0_TX_IRQHandler ; 17: UART0_TX Interrupt
DCD LEUART0_IRQHandler ; 18: LEUART0 Interrupt
DCD LEUART1_IRQHandler ; 19: LEUART1 Interrupt
DCD LETIMER0_IRQHandler ; 20: LETIMER0 Interrupt
DCD PCNT0_IRQHandler ; 21: PCNT0 Interrupt
DCD PCNT1_IRQHandler ; 22: PCNT1 Interrupt
DCD PCNT2_IRQHandler ; 23: PCNT2 Interrupt
DCD RTC_IRQHandler ; 24: RTC Interrupt
DCD CMU_IRQHandler ; 25: CMU Interrupt
DCD VCMP_IRQHandler ; 26: VCMP Interrupt
DCD LCD_IRQHandler ; 27: LCD Interrupt
DCD MSC_IRQHandler ; 28: MSC Interrupt
DCD AES_IRQHandler ; 29: AES Interrupt
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA_IRQHandler [WEAK]
EXPORT GPIO_EVEN_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT USART0_RX_IRQHandler [WEAK]
EXPORT USART0_TX_IRQHandler [WEAK]
EXPORT ACMP0_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT GPIO_ODD_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT USART1_RX_IRQHandler [WEAK]
EXPORT USART1_TX_IRQHandler [WEAK]
EXPORT USART2_RX_IRQHandler [WEAK]
EXPORT USART2_TX_IRQHandler [WEAK]
EXPORT UART0_RX_IRQHandler [WEAK]
EXPORT UART0_TX_IRQHandler [WEAK]
EXPORT LEUART0_IRQHandler [WEAK]
EXPORT LEUART1_IRQHandler [WEAK]
EXPORT LETIMER0_IRQHandler [WEAK]
EXPORT PCNT0_IRQHandler [WEAK]
EXPORT PCNT1_IRQHandler [WEAK]
EXPORT PCNT2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT CMU_IRQHandler [WEAK]
EXPORT VCMP_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT MSC_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
DMA_IRQHandler
GPIO_EVEN_IRQHandler
TIMER0_IRQHandler
USART0_RX_IRQHandler
USART0_TX_IRQHandler
ACMP0_IRQHandler
ADC0_IRQHandler
DAC0_IRQHandler
I2C0_IRQHandler
GPIO_ODD_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
USART1_RX_IRQHandler
USART1_TX_IRQHandler
USART2_RX_IRQHandler
USART2_TX_IRQHandler
UART0_RX_IRQHandler
UART0_TX_IRQHandler
LEUART0_IRQHandler
LEUART1_IRQHandler
LETIMER0_IRQHandler
PCNT0_IRQHandler
PCNT1_IRQHandler
PCNT2_IRQHandler
RTC_IRQHandler
CMU_IRQHandler
VCMP_IRQHandler
LCD_IRQHandler
MSC_IRQHandler
AES_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/cs3/efm32g.ld 0 → 100644
浏览文件 @ 314bcbd3
/* Linker script for Energy Micro EFM32G
*
* Version: Sourcery G++ 4.4-139 - Preview
* Support: https://support.codesourcery.com/GNUToolchain/
*
* Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
ENTRY(__cs3_reset)
SEARCH_DIR(.)
GROUP(-lgcc -lc -lcs3 -lcs3unhosted)
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 128K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
}
/* These force the linker to search for particular symbols from
* the start of the link process and thus ensure the user's
* overrides are picked up
*/
EXTERN(__cs3_reset __cs3_reset_efm32)
EXTERN(__cs3_start_asm _start)
EXTERN(__cs3_stack)
EXTERN(__cs3_reset)
EXTERN(NMI_Handler)
EXTERN(HardFault_Handler)
EXTERN(MemManage_Handler)
EXTERN(BusFault_Handler)
EXTERN(UsageFault_Handler)
EXTERN(Reserved7_Handler)
EXTERN(Reserved8_Handler)
EXTERN(Reserved9_Handler)
EXTERN(Reserved10_Handler)
EXTERN(SVC_Handler)
EXTERN(DebugMon_Handler)
EXTERN(Reserved13_Handler)
EXTERN(PendSV_Handler)
EXTERN(SysTick_Handler)
EXTERN(DMA_IRQHandler)
EXTERN(GPIO_EVEN_IRQHandler)
EXTERN(TIMER0_IRQHandler)
EXTERN(USART0_RX_IRQHandler)
EXTERN(USART0_TX_IRQHandler)
EXTERN(ACMP0_IRQHandler)
EXTERN(ADC0_IRQHandler)
EXTERN(DAC0_IRQHandler)
EXTERN(I2C0_IRQHandler)
EXTERN(GPIO_ODD_IRQHandler)
EXTERN(TIMER1_IRQHandler)
EXTERN(TIMER2_IRQHandler)
EXTERN(USART1_RX_IRQHandler)
EXTERN(USART1_TX_IRQHandler)
EXTERN(USART2_RX_IRQHandler)
EXTERN(USART2_TX_IRQHandler)
EXTERN(UART0_RX_IRQHandler)
EXTERN(UART0_TX_IRQHandler)
EXTERN(LEUART0_IRQHandler)
EXTERN(LEUART1_IRQHandler)
EXTERN(LETIMER0_IRQHandler)
EXTERN(PCNT0_IRQHandler)
EXTERN(PCNT1_IRQHandler)
EXTERN(PCNT2_IRQHandler)
EXTERN(RTC_IRQHandler)
EXTERN(CMU_IRQHandler)
EXTERN(VCMP_IRQHandler)
EXTERN(LCD_IRQHandler)
EXTERN(MSC_IRQHandler)
EXTERN(AES_IRQHandler)
EXTERN(__cs3_interrupt_vector_efm32g)
EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
/* Provide fall-back values */
PROVIDE(__cs3_heap_start = _end);
PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);
PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
SECTIONS
{
.text :
{
CREATE_OBJECT_SYMBOLS
__cs3_region_start_rom = .;
*(.cs3.region-head.rom)
ASSERT (. == __cs3_region_start_rom, ".cs3.region-head.rom not permitted");
__cs3_interrupt_vector = __cs3_interrupt_vector_efm32g;
*(.cs3.interrupt_vector)
/* Make sure we pulled in an interrupt vector. */
ASSERT (. != __cs3_interrupt_vector_efm32g, "No interrupt vector");
PROVIDE(__cs3_reset = __cs3_reset_efm32);
*(.cs3.reset)
PROVIDE(__cs3_start_asm = _start);
*(.text.cs3.init)
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
} >rom
.eh_frame_hdr : ALIGN (4)
{
KEEP (*(.eh_frame_hdr))
} >rom
.eh_frame : ALIGN (4)
{
KEEP (*(.eh_frame))
} >rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >rom
PROVIDE_HIDDEN (__exidx_end = .);
.rodata : ALIGN (4)
{
*(.rodata .rodata.* .gnu.linkonce.r.*)
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
__cs3_regions = .;
LONG (0)
LONG (__cs3_region_init_ram)
LONG (__cs3_region_start_ram)
LONG (__cs3_region_init_size_ram)
LONG (__cs3_region_zero_size_ram)
__cs3_regions_end = .;
. = ALIGN (8);
*(.rom)
*(.rom.b .bss.rom)
_etext = .;
} >rom
/* __cs3_region_end_rom is deprecated */
__cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);
__cs3_region_size_rom = LENGTH(rom);
.data : ALIGN (8)
{
__cs3_region_start_ram = .;
*(.cs3.region-head.ram)
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN (8);
*(.ram)
_edata = .;
} >ram AT>rom
.bss :
{
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
*(.ram.b .bss.ram)
_end = .;
__end = .;
} >ram AT>rom
/* __cs3_region_end_ram is deprecated */
__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
__cs3_region_size_ram = LENGTH(ram);
__cs3_region_init_ram = LOADADDR (.data);
__cs3_region_init_size_ram = _edata - ADDR (.data);
__cs3_region_zero_size_ram = _end - _edata;
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to
* the beginning of the section so we begin them at 0.
*/
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* DWARF 2.1 */
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
}
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/cs3/startup_efm32.s 0 → 100644
浏览文件 @ 314bcbd3
/* Vector table for efm32g
*
* Version: Sourcery G++ 4.4-180
* Support: https://support.codesourcery.com/GNUToolchain/
*
* Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
* Energy Micro release version
* @version 1.3.0
*/
.section ".cs3.interrupt_vector", "ax"
.globl __cs3_interrupt_vector_efm32g
.type __cs3_interrupt_vector_efm32g, %object
__cs3_interrupt_vector_efm32g:
.long __cs3_stack
.long __cs3_reset
.long NMI_Handler
.long HardFault_Handler
.long MemManage_Handler
.long BusFault_Handler
.long UsageFault_Handler
.long Reserved7_Handler
.long Reserved8_Handler
.long Reserved9_Handler
.long Reserved10_Handler
.long SVC_Handler
.long DebugMon_Handler
.long Reserved13_Handler
.long PendSV_Handler
.long SysTick_Handler
.long DMA_IRQHandler
.long GPIO_EVEN_IRQHandler
.long TIMER0_IRQHandler
.long USART0_RX_IRQHandler
.long USART0_TX_IRQHandler
.long ACMP0_IRQHandler
.long ADC0_IRQHandler
.long DAC0_IRQHandler
.long I2C0_IRQHandler
.long GPIO_ODD_IRQHandler
.long TIMER1_IRQHandler
.long TIMER2_IRQHandler
.long USART1_RX_IRQHandler
.long USART1_TX_IRQHandler
.long USART2_RX_IRQHandler
.long USART2_TX_IRQHandler
.long UART0_RX_IRQHandler
.long UART0_TX_IRQHandler
.long LEUART0_IRQHandler
.long LEUART1_IRQHandler
.long LETIMER0_IRQHandler
.long PCNT0_IRQHandler
.long PCNT1_IRQHandler
.long PCNT2_IRQHandler
.long RTC_IRQHandler
.long CMU_IRQHandler
.long VCMP_IRQHandler
.long LCD_IRQHandler
.long MSC_IRQHandler
.long AES_IRQHandler
.size __cs3_interrupt_vector_efm32g, . - __cs3_interrupt_vector_efm32g
.thumb
.thumb_func
.section .cs3.reset,"ax",%progbits
.globl __cs3_reset_efm32
.type __cs3_reset_efm32, %function
__cs3_reset_efm32:
/* jump to common start code */
ldr r0,=__cs3_start_asm
bx r0
.pool
.size __cs3_reset_efm32,.-__cs3_reset_efm32
.thumb
.globl _IRQHandlerinterrupt
.type _IRQHandlerinterrupt, %function
_IRQHandlerinterrupt:
b .
.size _IRQHandlerinterrupt, . - _IRQHandlerinterrupt
.weak NMI_Handler
.globl NMI_Handler
.set NMI_Handler, _IRQHandlerinterrupt
.weak HardFault_Handler
.globl HardFault_Handler
.set HardFault_Handler, _IRQHandlerinterrupt
.weak MemManage_Handler
.globl MemManage_Handler
.set MemManage_Handler, _IRQHandlerinterrupt
.weak BusFault_Handler
.globl BusFault_Handler
.set BusFault_Handler, _IRQHandlerinterrupt
.weak UsageFault_Handler
.globl UsageFault_Handler
.set UsageFault_Handler, _IRQHandlerinterrupt
.weak Reserved7_Handler
.globl Reserved7_Handler
.set Reserved7_Handler, _IRQHandlerinterrupt
.weak Reserved8_Handler
.globl Reserved8_Handler
.set Reserved8_Handler, _IRQHandlerinterrupt
.weak Reserved9_Handler
.globl Reserved9_Handler
.set Reserved9_Handler, _IRQHandlerinterrupt
.weak Reserved10_Handler
.globl Reserved10_Handler
.set Reserved10_Handler, _IRQHandlerinterrupt
.weak SVC_Handler
.globl SVC_Handler
.set SVC_Handler, _IRQHandlerinterrupt
.weak DebugMon_Handler
.globl DebugMon_Handler
.set DebugMon_Handler, _IRQHandlerinterrupt
.weak Reserved13_Handler
.globl Reserved13_Handler
.set Reserved13_Handler, _IRQHandlerinterrupt
.weak PendSV_Handler
.globl PendSV_Handler
.set PendSV_Handler, _IRQHandlerinterrupt
.weak SysTick_Handler
.globl SysTick_Handler
.set SysTick_Handler, _IRQHandlerinterrupt
.weak DMA_IRQHandler
.globl DMA_IRQHandler
.set DMA_IRQHandler, _IRQHandlerinterrupt
.weak GPIO_EVEN_IRQHandler
.globl GPIO_EVEN_IRQHandler
.set GPIO_EVEN_IRQHandler, _IRQHandlerinterrupt
.weak TIMER0_IRQHandler
.globl TIMER0_IRQHandler
.set TIMER0_IRQHandler, _IRQHandlerinterrupt
.weak USART0_RX_IRQHandler
.globl USART0_RX_IRQHandler
.set USART0_RX_IRQHandler, _IRQHandlerinterrupt
.weak USART0_TX_IRQHandler
.globl USART0_TX_IRQHandler
.set USART0_TX_IRQHandler, _IRQHandlerinterrupt
.weak ACMP0_IRQHandler
.globl ACMP0_IRQHandler
.set ACMP0_IRQHandler, _IRQHandlerinterrupt
.weak ADC0_IRQHandler
.globl ADC0_IRQHandler
.set ADC0_IRQHandler, _IRQHandlerinterrupt
.weak DAC0_IRQHandler
.globl DAC0_IRQHandler
.set DAC0_IRQHandler, _IRQHandlerinterrupt
.weak I2C0_IRQHandler
.globl I2C0_IRQHandler
.set I2C0_IRQHandler, _IRQHandlerinterrupt
.weak GPIO_ODD_IRQHandler
.globl GPIO_ODD_IRQHandler
.set GPIO_ODD_IRQHandler, _IRQHandlerinterrupt
.weak TIMER1_IRQHandler
.globl TIMER1_IRQHandler
.set TIMER1_IRQHandler, _IRQHandlerinterrupt
.weak TIMER2_IRQHandler
.globl TIMER2_IRQHandler
.set TIMER2_IRQHandler, _IRQHandlerinterrupt
.weak USART1_RX_IRQHandler
.globl USART1_RX_IRQHandler
.set USART1_RX_IRQHandler, _IRQHandlerinterrupt
.weak USART1_TX_IRQHandler
.globl USART1_TX_IRQHandler
.set USART1_TX_IRQHandler, _IRQHandlerinterrupt
.weak USART2_RX_IRQHandler
.globl USART2_RX_IRQHandler
.set USART2_RX_IRQHandler, _IRQHandlerinterrupt
.weak USART2_TX_IRQHandler
.globl USART2_TX_IRQHandler
.set USART2_TX_IRQHandler, _IRQHandlerinterrupt
.weak UART0_RX_IRQHandler
.globl UART0_RX_IRQHandler
.set UART0_RX_IRQHandler, _IRQHandlerinterrupt
.weak UART0_TX_IRQHandler
.globl UART0_TX_IRQHandler
.set UART0_TX_IRQHandler, _IRQHandlerinterrupt
.weak LEUART0_IRQHandler
.globl LEUART0_IRQHandler
.set LEUART0_IRQHandler, _IRQHandlerinterrupt
.weak LEUART1_IRQHandler
.globl LEUART1_IRQHandler
.set LEUART1_IRQHandler, _IRQHandlerinterrupt
.weak LETIMER0_IRQHandler
.globl LETIMER0_IRQHandler
.set LETIMER0_IRQHandler, _IRQHandlerinterrupt
.weak PCNT0_IRQHandler
.globl PCNT0_IRQHandler
.set PCNT0_IRQHandler, _IRQHandlerinterrupt
.weak PCNT1_IRQHandler
.globl PCNT1_IRQHandler
.set PCNT1_IRQHandler, _IRQHandlerinterrupt
.weak PCNT2_IRQHandler
.globl PCNT2_IRQHandler
.set PCNT2_IRQHandler, _IRQHandlerinterrupt
.weak RTC_IRQHandler
.globl RTC_IRQHandler
.set RTC_IRQHandler, _IRQHandlerinterrupt
.weak CMU_IRQHandler
.globl CMU_IRQHandler
.set CMU_IRQHandler, _IRQHandlerinterrupt
.weak VCMP_IRQHandler
.globl VCMP_IRQHandler
.set VCMP_IRQHandler, _IRQHandlerinterrupt
.weak LCD_IRQHandler
.globl LCD_IRQHandler
.set LCD_IRQHandler, _IRQHandlerinterrupt
.weak MSC_IRQHandler
.globl MSC_IRQHandler
.set MSC_IRQHandler, _IRQHandlerinterrupt
.weak AES_IRQHandler
.globl AES_IRQHandler
.set AES_IRQHandler, _IRQHandlerinterrupt
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/iar/startup_efm32.c 0 → 100644
浏览文件 @ 314bcbd3
/**************************************************************************//**
* @file
* @brief CMSIS Compatible EFM32 startup file in Cfor IAR EWARM
* @author Energy Micro AS
* @version 1.3.0
******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#pragma language=extended
#pragma segment="CSTACK"
/* IAR start function */
extern void __iar_program_start(void);
/* CMSIS init function */
extern void SystemInit(void);
/* Auto defined by linker */
extern unsigned char CSTACK$$Limit;
__weak void Reset_Handler(void)
{
SystemInit();
__iar_program_start();
}
__weak void NMI_Handler(void)
{
while(1);
}
__weak void HardFault_Handler(void)
{
while(1);
}
__weak void MemManage_Handler(void)
{
while(1);
}
__weak void BusFault_Handler(void)
{
while(1);
}
__weak void UsageFault_Handler(void)
{
while(1);
}
__weak void SVC_Handler(void)
{
while(1);
}
__weak void DebugMon_Handler(void)
{
while(1);
}
__weak void PendSV_Handler(void)
{
while(1);
}
__weak void SysTick_Handler(void)
{
while(1);
}
__weak void DMA_IRQHandler(void)
{
while(1);
}
__weak void GPIO_EVEN_IRQHandler(void)
{
while(1);
}
__weak void TIMER0_IRQHandler(void)
{
while(1);
}
__weak void USART0_RX_IRQHandler(void)
{
while(1);
}
__weak void USART0_TX_IRQHandler(void)
{
while(1);
}
__weak void ACMP0_IRQHandler(void)
{
while(1);
}
__weak void ADC0_IRQHandler(void)
{
while(1);
}
__weak void DAC0_IRQHandler(void)
{
while(1);
}
__weak void I2C0_IRQHandler(void)
{
while(1);
}
__weak void GPIO_ODD_IRQHandler(void)
{
while(1);
}
__weak void TIMER1_IRQHandler(void)
{
while(1);
}
__weak void TIMER2_IRQHandler(void)
{
while(1);
}
__weak void USART1_RX_IRQHandler(void)
{
while(1);
}
__weak void USART1_TX_IRQHandler(void)
{
while(1);
}
__weak void USART2_RX_IRQHandler(void)
{
while(1);
}
__weak void USART2_TX_IRQHandler(void)
{
while(1);
}
__weak void UART0_RX_IRQHandler(void)
{
while(1);
}
__weak void UART0_TX_IRQHandler(void)
{
while(1);
}
__weak void LEUART0_IRQHandler(void)
{
while(1);
}
__weak void LEUART1_IRQHandler(void)
{
while(1);
}
__weak void LETIMER0_IRQHandler(void)
{
while(1);
}
__weak void PCNT0_IRQHandler(void)
{
while(1);
}
__weak void PCNT1_IRQHandler(void)
{
while(1);
}
__weak void PCNT2_IRQHandler(void)
{
while(1);
}
__weak void RTC_IRQHandler(void)
{
while(1);
}
__weak void CMU_IRQHandler(void)
{
while(1);
}
__weak void VCMP_IRQHandler(void)
{
while(1);
}
__weak void LCD_IRQHandler(void)
{
while(1);
}
__weak void MSC_IRQHandler(void)
{
while(1);
}
__weak void AES_IRQHandler(void)
{
while(1);
}
/* With IAR, the CSTACK is defined via project options settings */
#pragma location = ".intvec"
const void * const __vector_table[]= {
&CSTACK$$Limit,
(void *) Reset_Handler, /* 1 - Reset (start instruction) */
(void *) NMI_Handler, /* 2 - NMI */
(void *) HardFault_Handler, /* 3 - HardFault */
(void *) MemManage_Handler,
(void *) BusFault_Handler,
(void *) UsageFault_Handler,
(void *) 0,
(void *) 0,
(void *) 0,
(void *) 0,
(void *) SVC_Handler,
(void *) DebugMon_Handler,
(void *) 0,
(void *) PendSV_Handler,
(void *) SysTick_Handler,
(void *) DMA_IRQHandler, /* 0 - DMA */
(void *) GPIO_EVEN_IRQHandler, /* 1 - GPIO_EVEN */
(void *) TIMER0_IRQHandler, /* 2 - TIMER0 */
(void *) USART0_RX_IRQHandler, /* 3 - USART0_RX */
(void *) USART0_TX_IRQHandler, /* 4 - USART0_TX */
(void *) ACMP0_IRQHandler, /* 5 - ACMP0 */
(void *) ADC0_IRQHandler, /* 6 - ADC0 */
(void *) DAC0_IRQHandler, /* 7 - DAC0 */
(void *) I2C0_IRQHandler, /* 8 - I2C0 */
(void *) GPIO_ODD_IRQHandler, /* 9 - GPIO_ODD */
(void *) TIMER1_IRQHandler, /* 10 - TIMER1 */
(void *) TIMER2_IRQHandler, /* 11 - TIMER2 */
(void *) USART1_RX_IRQHandler, /* 12 - USART1_RX */
(void *) USART1_TX_IRQHandler, /* 13 - USART1_TX */
(void *) USART2_RX_IRQHandler, /* 14 - USART2_RX */
(void *) USART2_TX_IRQHandler, /* 15 - USART2_TX */
(void *) UART0_RX_IRQHandler, /* 16 - UART0_RX */
(void *) UART0_TX_IRQHandler, /* 17 - UART0_TX */
(void *) LEUART0_IRQHandler, /* 18 - LEUART0 */
(void *) LEUART1_IRQHandler, /* 19 - LEUART1 */
(void *) LETIMER0_IRQHandler, /* 20 - LETIMER0 */
(void *) PCNT0_IRQHandler, /* 21 - PCNT0 */
(void *) PCNT1_IRQHandler, /* 22 - PCNT1 */
(void *) PCNT2_IRQHandler, /* 23 - PCNT2 */
(void *) RTC_IRQHandler, /* 24 - RTC */
(void *) CMU_IRQHandler, /* 25 - CMU */
(void *) VCMP_IRQHandler, /* 26 - VCMP */
(void *) LCD_IRQHandler, /* 27 - LCD */
(void *) MSC_IRQHandler, /* 28 - MSC */
(void *) AES_IRQHandler, /* 29 - AES */
};
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/startup/iar/startup_efm32.s 0 → 100644
浏览文件 @ 314bcbd3
;/*************************************************************************//**
; * @file: startup_efm32.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the Energy Micro 'EFM32G' Device Series
; * @version 1.3.0
; * @date: 7. September 2010
; *----------------------------------------------------------------------------
; *
; * Copyright (C) 2009 ARM Limited. All rights reserved.
; *
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM wtih at least a 128 byte
; alignment, 256 byte alignment is requied if all interrupt vectors are in use.
;
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD DMA_IRQHandler ; 0: DMA Interrupt
DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt
DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt
DCD ACMP0_IRQHandler ; 5: ACMP0 Interrupt
DCD ADC0_IRQHandler ; 6: ADC0 Interrupt
DCD DAC0_IRQHandler ; 7: DAC0 Interrupt
DCD I2C0_IRQHandler ; 8: I2C0 Interrupt
DCD GPIO_ODD_IRQHandler ; 9: GPIO_ODD Interrupt
DCD TIMER1_IRQHandler ; 10: TIMER1 Interrupt
DCD TIMER2_IRQHandler ; 11: TIMER2 Interrupt
DCD USART1_RX_IRQHandler ; 12: USART1_RX Interrupt
DCD USART1_TX_IRQHandler ; 13: USART1_TX Interrupt
DCD USART2_RX_IRQHandler ; 14: USART2_RX Interrupt
DCD USART2_TX_IRQHandler ; 15: USART2_TX Interrupt
DCD UART0_RX_IRQHandler ; 16: UART0_RX Interrupt
DCD UART0_TX_IRQHandler ; 17: UART0_TX Interrupt
DCD LEUART0_IRQHandler ; 18: LEUART0 Interrupt
DCD LEUART1_IRQHandler ; 19: LEUART1 Interrupt
DCD LETIMER0_IRQHandler ; 20: LETIMER0 Interrupt
DCD PCNT0_IRQHandler ; 21: PCNT0 Interrupt
DCD PCNT1_IRQHandler ; 22: PCNT1 Interrupt
DCD PCNT2_IRQHandler ; 23: PCNT2 Interrupt
DCD RTC_IRQHandler ; 24: RTC Interrupt
DCD CMU_IRQHandler ; 25: CMU Interrupt
DCD VCMP_IRQHandler ; 26: VCMP Interrupt
DCD LCD_IRQHandler ; 27: LCD Interrupt
DCD MSC_IRQHandler ; 28: MSC Interrupt
DCD AES_IRQHandler ; 29: AES Interrupt
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
; EFM32G specific interrupt handlers
PUBWEAK DMA_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA_IRQHandler
B DMA_IRQHandler
PUBWEAK GPIO_EVEN_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO_EVEN_IRQHandler
B GPIO_EVEN_IRQHandler
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER0_IRQHandler
B TIMER0_IRQHandler
PUBWEAK USART0_RX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART0_RX_IRQHandler
B USART0_RX_IRQHandler
PUBWEAK USART0_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART0_TX_IRQHandler
B USART0_TX_IRQHandler
PUBWEAK ACMP0_IRQHandler
SECTION .text:CODE:REORDER(1)
ACMP0_IRQHandler
B ACMP0_IRQHandler
PUBWEAK ADC0_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC0_IRQHandler
B ADC0_IRQHandler
PUBWEAK DAC0_IRQHandler
SECTION .text:CODE:REORDER(1)
DAC0_IRQHandler
B DAC0_IRQHandler
PUBWEAK I2C0_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C0_IRQHandler
B I2C0_IRQHandler
PUBWEAK GPIO_ODD_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO_ODD_IRQHandler
B GPIO_ODD_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK USART1_RX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_RX_IRQHandler
B USART1_RX_IRQHandler
PUBWEAK USART1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_TX_IRQHandler
B USART1_TX_IRQHandler
PUBWEAK USART2_RX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_RX_IRQHandler
B USART2_RX_IRQHandler
PUBWEAK USART2_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_TX_IRQHandler
B USART2_TX_IRQHandler
PUBWEAK UART0_RX_IRQHandler
SECTION .text:CODE:REORDER(1)
UART0_RX_IRQHandler
B UART0_RX_IRQHandler
PUBWEAK UART0_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
UART0_TX_IRQHandler
B UART0_TX_IRQHandler
PUBWEAK LEUART0_IRQHandler
SECTION .text:CODE:REORDER(1)
LEUART0_IRQHandler
B LEUART0_IRQHandler
PUBWEAK LEUART1_IRQHandler
SECTION .text:CODE:REORDER(1)
LEUART1_IRQHandler
B LEUART1_IRQHandler
PUBWEAK LETIMER0_IRQHandler
SECTION .text:CODE:REORDER(1)
LETIMER0_IRQHandler
B LETIMER0_IRQHandler
PUBWEAK PCNT0_IRQHandler
SECTION .text:CODE:REORDER(1)
PCNT0_IRQHandler
B PCNT0_IRQHandler
PUBWEAK PCNT1_IRQHandler
SECTION .text:CODE:REORDER(1)
PCNT1_IRQHandler
B PCNT1_IRQHandler
PUBWEAK PCNT2_IRQHandler
SECTION .text:CODE:REORDER(1)
PCNT2_IRQHandler
B PCNT2_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK CMU_IRQHandler
SECTION .text:CODE:REORDER(1)
CMU_IRQHandler
B CMU_IRQHandler
PUBWEAK VCMP_IRQHandler
SECTION .text:CODE:REORDER(1)
VCMP_IRQHandler
B VCMP_IRQHandler
PUBWEAK LCD_IRQHandler
SECTION .text:CODE:REORDER(1)
LCD_IRQHandler
B LCD_IRQHandler
PUBWEAK MSC_IRQHandler
SECTION .text:CODE:REORDER(1)
MSC_IRQHandler
B MSC_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
END
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c 0 → 100644
浏览文件 @ 314bcbd3
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 devices.
* @author Energy Micro AS
* @version 1.3.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
*******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#include <stdint.h>
#include "efm32.h"
/*******************************************************************************
****************************** DEFINES ************************************
******************************************************************************/
/** LFRCO frequency, tuned to below frequency during manufacturing. */
#define EFM32_LFRCO_FREQ (32768)
/*******************************************************************************
************************** LOCAL VARIABLES ********************************
******************************************************************************/
/* System oscillator frequencies. These frequencies are normally constant */
/* for a target, but they are made configurable in order to allow run-time */
/* handling of different boards. The crystal oscillator clocks can be set */
/* compile time to a non-default value by defining respective EFM32_nFXO_FREQ */
/* values according to board design. By defining the EFM32_nFXO_FREQ to 0, */
/* one indicates that the oscillator is not present, in order to save some */
/* SW footprint. */
#ifndef EFM32_HFXO_FREQ
#define EFM32_HFXO_FREQ (32000000)
#endif
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
#if (EFM32_LFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = 32768;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
/**
* @brief
* System System Clock Frequency (Core Clock).
*
* @details
* Required CMSIS global variable that must be kept up-to-date.
*/
uint32_t SystemCoreClock;
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Get the current core clock frequency.
*
* @details
* Calculate and get the current core clock frequency based on the current
* configuration. Assuming that the SystemCoreClock global variable is
* maintained, the core clock frequency is stored in that variable as well.
* This function will however calculate the core clock based on actual HW
* configuration. It will also update the SystemCoreClock global variable.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* The current core clock frequency in Hz.
******************************************************************************/
uint32_t SystemCoreClockGet(void)
{
uint32_t ret;
ret = SystemHFClockGet();
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
/* Keep CMSIS variable up-to-date just in case */
SystemCoreClock = ret;
return ret;
}
/***************************************************************************//**
* @brief
* Get the current HFCLK frequency.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* The current HFCLK frequency in Hz.
******************************************************************************/
uint32_t SystemHFClockGet(void)
{
uint32_t ret;
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
{
case CMU_STATUS_LFXOSEL:
#if (EFM32_LFXO_FREQ > 0)
ret = SystemLFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
ret = 0;
#endif
break;
case CMU_STATUS_LFRCOSEL:
ret = EFM32_LFRCO_FREQ;
break;
case CMU_STATUS_HFXOSEL:
#if (EFM32_HFXO_FREQ > 0)
ret = SystemHFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
ret = 0;
#endif
break;
default: /* CMU_STATUS_HFRCOSEL */
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
{
case CMU_HFRCOCTRL_BAND_28MHZ:
ret = 28000000;
break;
case CMU_HFRCOCTRL_BAND_21MHZ:
ret = 21000000;
break;
case CMU_HFRCOCTRL_BAND_14MHZ:
ret = 14000000;
break;
case CMU_HFRCOCTRL_BAND_11MHZ:
ret = 11000000;
break;
case CMU_HFRCOCTRL_BAND_7MHZ:
ret = 7000000;
break;
case CMU_HFRCOCTRL_BAND_1MHZ:
ret = 1000000;
break;
default:
ret = 0;
break;
}
break;
}
return ret;
}
/**************************************************************************//**
* @brief
* Get high frequency crystal oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* HFXO frequency in Hz.
*****************************************************************************/
uint32_t SystemHFXOClockGet(void)
{
/* External crystal oscillator present? */
#if (EFM32_HFXO_FREQ > 0)
return SystemHFXOClock;
#else
return 0;
#endif
}
/**************************************************************************//**
* @brief
* Set high frequency crystal oscillator clock frequency for target system.
*
* @note
* This function is mainly provided for being able to handle target systems
* with different HF crystal oscillator frequencies run-time. If used, it
* should probably only be used once during system startup.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @param[in] freq
* HFXO frequency in Hz used for target.
*****************************************************************************/
void SystemHFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
#if (EFM32_HFXO_FREQ > 0)
SystemHFXOClock = freq;
/* Update core clock frequency if HFXO is used to clock core */
if (CMU->STATUS & CMU_STATUS_HFXOSEL)
{
/* The function will update the global variable */
SystemCoreClockGet();
}
#else
(void)freq; /* Unused parameter */
#endif
}
/**************************************************************************//**
* @brief
* Initialize the system.
*
* @details
* Do required generic HW system init.
*
* @note
* This function is invoked during system init, before the main() routine
* and any data has been initialized. For this reason, it cannot do any
* initialization of variables etc.
*****************************************************************************/
void SystemInit(void)
{
}
/**************************************************************************//**
* @brief
* Get low frequency RC oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* LFRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemLFRCOClockGet(void)
{
/* Currently we assume that this frequency is properly tuned during */
/* manufacturing and is not changed after reset. If future requirements */
/* for re-tuning by user, we can add support for that. */
return EFM32_LFRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get low frequency crystal oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* LFXO frequency in Hz.
*****************************************************************************/
uint32_t SystemLFXOClockGet(void)
{
/* External crystal oscillator present? */
#if (EFM32_LFXO_FREQ > 0)
return SystemLFXOClock;
#else
return 0;
#endif
}
/**************************************************************************//**
* @brief
* Set low frequency crystal oscillator clock frequency for target system.
*
* @note
* This function is mainly provided for being able to handle target systems
* with different HF crystal oscillator frequencies run-time. If used, it
* should probably only be used once during system startup.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @param[in] freq
* LFXO frequency in Hz used for target.
*****************************************************************************/
void SystemLFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
#if (EFM32_LFXO_FREQ > 0)
SystemLFXOClock = freq;
/* Update core clock frequency if LFXO is used to clock core */
if (CMU->STATUS & CMU_STATUS_LFXOSEL)
{
/* The function will update the global variable */
SystemCoreClockGet();
}
#else
(void)freq; /* Unused parameter */
#endif
}
bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.h 0 → 100644
浏览文件 @ 314bcbd3
/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 devices.
* @author Energy Micro AS
* @version 1.3.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
*******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef __SYSTEM_EFM32_H
#define __SYSTEM_EFM32_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
uint32_t SystemCoreClockGet(void);
/**************************************************************************//**
* @brief
* Update CMSIS SystemCoreClock variable.
*
* @details
* CMSIS defines a global variable SystemCoreClock that shall hold the
* core frequency in Hz. If the core frequency is dynamically changed, the
* variable must be kept updated in order to be CMSIS compliant.
*
* Notice that if only changing core clock frequency through the EFM32 CMU
* API, this variable will be kept updated. This function is only provided
* for CMSIS compliance and if a user modifies the the core clock outside
* the CMU API.
*****************************************************************************/
static __INLINE void SystemCoreClockUpdate(void)
{
SystemCoreClockGet();
}
uint32_t SystemHFClockGet(void);
uint32_t SystemHFXOClockGet(void);
void SystemHFXOClockSet(uint32_t freq);
void SystemInit(void);
uint32_t SystemLFRCOClockGet(void);
uint32_t SystemLFXOClockGet(void);
void SystemLFXOClockSet(uint32_t freq);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_EFM32_H */
bsp/efm32/Libraries/SConscript 0 → 100644
浏览文件 @ 314bcbd3
import rtconfig
Import('RTT_ROOT')
from building import *
# The set of source files associated with this SConscript file.
src = Split("""
CMSIS/CM3/CoreSupport/core_cm3.c
CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c
efm32lib/src/efm32_acmp.c
efm32lib/src/efm32_adc.c
efm32lib/src/efm32_aes.c
efm32lib/src/efm32_assert.c
efm32lib/src/efm32_cmu.c
efm32lib/src/efm32_dac.c
efm32lib/src/efm32_dbg.c
efm32lib/src/efm32_dma.c
efm32lib/src/efm32_ebi.c
efm32lib/src/efm32_emu.c
efm32lib/src/efm32_gpio.c
efm32lib/src/efm32_i2c.c
efm32lib/src/efm32_lcd.c
efm32lib/src/efm32_letimer.c
efm32lib/src/efm32_leuart.c
efm32lib/src/efm32_mpu.c
efm32lib/src/efm32_msc.c
efm32lib/src/efm32_pcnt.c
efm32lib/src/efm32_prs.c
efm32lib/src/efm32_rmu.c
efm32lib/src/efm32_rtc.c
efm32lib/src/efm32_system.c
efm32lib/src/efm32_timer.c
efm32lib/src/efm32_usart.c
efm32lib/src/efm32_vcmp.c
efm32lib/src/efm32_wdog.c
""")
path = [RTT_ROOT + '/bsp/efm32/Libraries/efm32lib/inc',
RTT_ROOT + '/bsp/efm32/Libraries/CMSIS/CM3/CoreSupport',
RTT_ROOT + '/bsp/efm32/Libraries/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32']
CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.EFM32_TYPE]
group = DefineGroup('EFM32_StdPeriph', src, depend = [''], CPPPATH = path)
Return('group')
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/***************************************************************************//**
* @file
* @brief Analog Comparator (ACMP) peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
*******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef __EFM32_ACMP_H
#define __EFM32_ACMP_H
#include <stdint.h>
#include <stdbool.h>
#include "efm32.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup EFM32_Library
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup ACMP
* @{
******************************************************************************/
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** Resistor values used for capacative sense. See the datasheet for your
* device for details on each resistor value. */
typedef enum
{
/** resistor value 0 */
acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0,
/** resistor value 1 */
acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1,
/** resistor value 2 */
acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2,
/** resistor value 3 */
acmpResistor3 = _ACMP_INPUTSEL_CSRESSEL_RES3
} ACMP_CapsenseResistor_TypeDef;
/** Hysteresis level. See datasheet for your device for details on each
* level. */
typedef enum
{
acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0, /**< Hysteresis level 0 */
acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1, /**< Hysteresis level 1 */
acmpHysteresisLevel2 = _ACMP_CTRL_HYSTSEL_HYST2, /**< Hysteresis level 2 */
acmpHysteresisLevel3 = _ACMP_CTRL_HYSTSEL_HYST3, /**< Hysteresis level 3 */
acmpHysteresisLevel4 = _ACMP_CTRL_HYSTSEL_HYST4, /**< Hysteresis level 4 */
acmpHysteresisLevel5 = _ACMP_CTRL_HYSTSEL_HYST5, /**< Hysteresis level 5 */
acmpHysteresisLevel6 = _ACMP_CTRL_HYSTSEL_HYST6, /**< Hysteresis level 6 */
acmpHysteresisLevel7 = _ACMP_CTRL_HYSTSEL_HYST7 /**< Hysteresis level 7 */
} ACMP_HysteresisLevel_TypeDef;
/** ACMP warmup time. The delay is measured in HFPERCLK cycles and should
* be at least 10 us. */
typedef enum
{
/** 4 HFPERCLK cycles warmup */
acmpWarmTime4 = _ACMP_CTRL_WARMTIME_4CYCLES,
/** 8 HFPERCLK cycles warmup */
acmpWarmTime8 = _ACMP_CTRL_WARMTIME_8CYCLES,
/** 16 HFPERCLK cycles warmup */
acmpWarmTime16 = _ACMP_CTRL_WARMTIME_16CYCLES,
/** 32 HFPERCLK cycles warmup */
acmpWarmTime32 = _ACMP_CTRL_WARMTIME_32CYCLES,
/** 64 HFPERCLK cycles warmup */
acmpWarmTime64 = _ACMP_CTRL_WARMTIME_64CYCLES,
/** 128 HFPERCLK cycles warmup */
acmpWarmTime128 = _ACMP_CTRL_WARMTIME_128CYCLES,
/** 256 HFPERCLK cycles warmup */
acmpWarmTime256 = _ACMP_CTRL_WARMTIME_256CYCLES,
/** 512 HFPERCLK cycles warmup */
acmpWarmTime512 = _ACMP_CTRL_WARMTIME_512CYCLES
} ACMP_WarmTime_TypeDef;
/** ACMP inputs. Note that scaled VDD and bandgap references can only be used
* as negative inputs. */
typedef enum
{
/** Channel 0 */
acmpChannel0 = _ACMP_INPUTSEL_NEGSEL_CH0,
/** Channel 1 */
acmpChannel1 = _ACMP_INPUTSEL_NEGSEL_CH1,
/** Channel 2 */
acmpChannel2 = _ACMP_INPUTSEL_NEGSEL_CH2,
/** Channel 3 */
acmpChannel3 = _ACMP_INPUTSEL_NEGSEL_CH3,
/** Channel 4 */
acmpChannel4 = _ACMP_INPUTSEL_NEGSEL_CH4,
/** Channel 5 */
acmpChannel5 = _ACMP_INPUTSEL_NEGSEL_CH5,
/** Channel 6 */
acmpChannel6 = _ACMP_INPUTSEL_NEGSEL_CH6,
/** Channel 7 */
acmpChannel7 = _ACMP_INPUTSEL_NEGSEL_CH7,
/** 1.25V internal reference */
acmpChannel1V25 = _ACMP_INPUTSEL_NEGSEL_1V25,
/** 2.5V internal reference */
acmpChannel2V5 = _ACMP_INPUTSEL_NEGSEL_2V5,
/** Scaled VDD reference */
acmpChannelVDD = _ACMP_INPUTSEL_NEGSEL_VDD
} ACMP_Channel_TypeDef;
/*******************************************************************************
****************************** STRUCTS ************************************
******************************************************************************/
/** Capsense initialization structure. */
typedef struct
{
/** Full bias current. See section 23.3.2 in the reference manual
* for details. */
bool fullBias;
/** Half bias current. See section 23.3.2 in the reference manual
* for details. */
bool halfBias;
/** Bias current. See section 23.3.2 in the reference manual for
* details. Valid values are in the range 0-7. */
uint32_t biasProg;
/** Warmup time. This is measured in HFPERCLK cycles and should be
* about 10us in wall clock time. */
ACMP_WarmTime_TypeDef warmTime;
/** Hysteresis level */
ACMP_HysteresisLevel_TypeDef hysteresisLevel;
/** Resistor used in the capacative sensing circuit. For values see
* your device datasheet. */
ACMP_CapsenseResistor_TypeDef resistor;
/** Low power reference enabled. This setting, if enabled, reduces the
* power used by the VDD and bandgap references. */
bool lowPowerReferenceEnabled;
/** Vdd reference value. VDD_SCALED = VDD VDDLEVEL 50mV/3.8V.
* Valid values are in the range 0-63. */
uint32_t vddLevel;
} ACMP_CapsenseInit_TypeDef;
/** Default config for capacitive sense on the STK */
#define ACMP_CAPSENSE_STK_DEFAULT \
{ false, /* fullBias */ \
false, /* halfBias */ \
0xF, /* biasProg */ \
acmpWarmTime512, /* 512 cycle warmup to be safe */ \
acmpHysteresisLevel5, \
acmpResistor3, \
false, /* low power reference */ \
0x3D /* VDD level */ \
}
/** ACMP initialization structure. */
typedef struct
{
/** Full bias current. See section 23.3.2 in the reference manual
* for details. */
bool fullBias;
/** Half bias current. See section 23.3.2 in the reference manual
* for details. */
bool halfBias;
/** Bias current. See section 23.3.2 in the reference manual for
* details. Valid values are in the range 0-7. */
uint32_t biasProg;
/** Enable setting the interrupt flag on falling edge */
bool interruptOnFallingEdge;
/** Enable setting the interrupt flag on rising edge */
bool interruptOnRisingEdge;
/** Warmup time. This is measured in HFPERCLK cycles and should be
* about 10us in wall clock time. */
ACMP_WarmTime_TypeDef warmTime;
/** Hysteresis level */
ACMP_HysteresisLevel_TypeDef hysteresisLevel;
/** Inactive value emitted by the ACMP during warmup */
bool inactiveValue;
/** Low power reference enabled. This setting, if enabled, reduces the
* power used by the VDD and bandgap references. */
bool lowPowerReferenceEnabled;
/** Vdd reference value. VDD_SCALED = VDD VDDLEVEL 50mV/3.8V.
* Valid values are in the range 0-63. */
uint32_t vddLevel;
} ACMP_Init_TypeDef;
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init);
void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel);
void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, ACMP_Channel_TypeDef posSel);
void ACMP_Disable(ACMP_TypeDef *acmp);
void ACMP_DisableNoReset(ACMP_TypeDef *acmp);
void ACMP_Enable(ACMP_TypeDef *acmp);
void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert);
void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init);
void ACMP_Reset(ACMP_TypeDef *acmp);
/***************************************************************************//**
* @brief
* Clear one or more pending ACMP interrupts.
*
* @param[in] acmp
* Pointer to ACMP peripheral register block.
*
* @param[in] flags
* Pending ACMP interrupt source to clear. Use a logical OR combination
* of valid interrupt flags for the ACMP module (ACMP_IF_nnn).
******************************************************************************/
static __INLINE void ACMP_IntClear(ACMP_TypeDef *acmp, uint32_t flags)
{
acmp->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more ACMP interrupts.
*
* @param[in] acmp
* Pointer to ACMP peripheral register block.
*
* @param[in] flags
* ACMP interrupt sources to disable. Use a logical OR combination of
* valid interrupt flags for the ACMP module (ACMP_IF_nnn).
******************************************************************************/
static __INLINE void ACMP_IntDisable(ACMP_TypeDef *acmp, uint32_t flags)
{
acmp->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more ACMP interrupts.
*
* @note
* Depending on the use, a pending interrupt may already be set prior to
* enabling the interrupt. Consider using ACMP_IntClear() prior to enabling
* if such a pending interrupt should be ignored.
*
* @param[in] acmp
* Pointer to ACMP peripheral register block.
*
* @param[in] flags
* ACMP interrupt sources to enable. Use a logical OR combination of
* valid interrupt flags for the ACMP module (ACMP_IF_nnn).
******************************************************************************/
static __INLINE void ACMP_IntEnable(ACMP_TypeDef *acmp, uint32_t flags)
{
acmp->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending ACMP interrupt flags.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @param[in] acmp
* Pointer to ACMP peripheral register block.
*
* @return
* ACMP interrupt sources pending. A logical OR combination of valid
* interrupt flags for the ACMP module (ACMP_IF_nnn).
******************************************************************************/
static __INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp)
{
return(acmp->IF);
}
/***************************************************************************//**
* @brief
* Set one or more pending ACMP interrupts from SW.
*
* @param[in] acmp
* Pointer to ACMP peripheral register block.
*
* @param[in] flags
* ACMP interrupt sources to set to pending. Use a logical OR combination
* of valid interrupt flags for the ACMP module (ACMP_IF_nnn).
******************************************************************************/
static __INLINE void ACMP_IntSet(ACMP_TypeDef *acmp, uint32_t flags)
{
acmp->IFS = flags;
}
/** @} (end addtogroup ACMP) */
/** @} (end addtogroup EFM32_Library) */
#ifdef __cplusplus
}
#endif
#endif /* __EFM32_ACMP_H */
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/***************************************************************************//**
* @file
* @brief EFM32 peripheral API "assert" implementation.
* @author Energy Micro AS
* @version 1.3.0
*
* @details
* By default, EFM32 library assert usage is not included in order to reduce
* footprint and processing overhead. Further, EFM32 assert usage is decoupled
* from ISO C assert handling (NDEBUG usage), to allow a user to use ISO C
* assert without including EFM32 assert statements.
*
* Below are available defines for controlling EFM32 assert inclusion. The defines
* are typically defined for a project to be used by the preprocessor.
*
* @li If DEBUG_EFM is defined, the internal EFM32 library assert handling will
* be used, which may be a quite rudimentary implementation.
*
* @li If DEBUG_EFM_USER is defined instead, the user must provide its own EFM32
* assert handling routine (assertEFM()).
*
* As indicated above, if none of the above defines are used, EFM32 assert
* statements are not compiled.
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
*******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef __EFM32_ASSERT_H
#define __EFM32_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER)
/* Due to footprint considerations, we only pass file name and line number, */
/* not the assert expression (nor function name (C99)) */
void assertEFM(const char *file, int line);
#define EFM_ASSERT(expr) ((expr) ? ((void) 0) : assertEFM(__FILE__, __LINE__))
#else
#define EFM_ASSERT(expr) ((void) 0)
#endif /* defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) */
/** @endcond */
#ifdef __cplusplus
}
#endif
#endif /* __EFM32_ASSERT_H */
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/***************************************************************************//**
* @file
* @brief Reset Management Unit (RMU) peripheral API for EFM32.
* @author Energy Micro AS
* @version 1.3.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
*******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef __EFM32_RMU_H
#define __EFM32_RMU_H
#include <stdbool.h>
#include "efm32.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup EFM32_Library
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup RMU
* @{
******************************************************************************/
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void RMU_LockupResetDisable(bool disable);
void RMU_ResetCauseClear(void);
uint32_t RMU_ResetCauseGet(void);
/** @} (end addtogroup RMU) */
/** @} (end addtogroup EFM32_Library) */
#ifdef __cplusplus
}
#endif
#endif /* __EFM32_RMU_H */
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bsp/efm32/SConscript 0 → 100644
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bsp/efm32/SConstruct 0 → 100644
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bsp/efm32/application.c 0 → 100644
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bsp/efm32/board.c 0 → 100644
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bsp/efm32/board.h 0 → 100644
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bsp/efm32/dev_led.c 0 → 100644
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bsp/efm32/dev_led.h 0 → 100644
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bsp/efm32/drv_dma.c 0 → 100644
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bsp/efm32/drv_dma.h 0 → 100644
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bsp/efm32/drv_iic.c 0 → 100644
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bsp/efm32/drv_iic.h 0 → 100644
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bsp/efm32/drv_rtc.c 0 → 100644
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bsp/efm32/drv_rtc.h 0 → 100644
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bsp/efm32/drv_timer.c 0 → 100644
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bsp/efm32/drv_timer.h 0 → 100644
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bsp/efm32/drv_usart.c 0 → 100644
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bsp/efm32/drv_usart.h 0 → 100644
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bsp/efm32/efm32_rom.ld 0 → 100644
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bsp/efm32/hdl_interrupt.c 0 → 100644
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bsp/efm32/hdl_interrupt.h 0 → 100644
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bsp/efm32/rtconfig.h 0 → 100644
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bsp/efm32/rtconfig.py 0 → 100644
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bsp/efm32/startup.c 0 → 100644
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libcpu/arm/cortex-m3/context_gcc.S 0 → 100644
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libcpu/arm/cortex-m3/fault.c 0 → 100644
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libcpu/arm/cortex-m3/fault_gcc.S 0 → 100644
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libcpu/arm/cortex-m3/stack.c 0 → 100644
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libcpu/arm/cortex-m3/start_gcc.S 0 → 100644
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