* refactor register mechanism, current so size: 1.20MB. test=develop

* fix KernelRegistry::Global().Create. test=develop

* fix cpplint errors. test=develop

* fix test_subgraph_pass bug. test=develop

* register kernel with target,precision,datalayout combination. test=develop

* fix test_paddle_api no op found bug. test=develop

* enhance comment

* fix lite/kernels/arm/elementwise_compute_test.cc. test=develop

* fix code style

* revert format of unchanged files. test=develop

* fix code format according to cpplint 1.5.1. test=develop

* remove redundant include header. test=develop

* add op affine_grid. test=develop

* fix concatt axis < 0 errorr,ttest=develop

* fix format. test=develop

* fix: winograd support unsame pad
test=develop

* feat: add winograd int8 kernel
test=develop

* fix: style fix
test=develo

* fix winograd_int8 ut sgement default. test=develop

* close basic_test, test=develop
Co-authored-by: NMyPandaShaoxiang <txg4794@163.com>

* add grouup_norm

* fix format. test=develop

* fix xiaodu crash. test=develop

* add deformable Conv op 

* fix ut, test=develop

* fix format. test=develop

* test=develop

* delete unuseful message. test=develop

int8 direct_conv, dw_conv add relu6 and leaky relu fusion

* improve 3x3s1 direct profile

* add gemv+relu6/lleakyRelu

* fix relu6 problem, test=develop

* fix format, test=develop

* add six / scale , test=develop

* reduce .so size. test=develop

* compile all targets when LITE_ON_TINY_PUBLISH=OFF

* unordered_map is more convenient when key is customized class

* test=develop

* [LITE][DOC] Add kernel profiler doc for add operation. test=develop

* add argmax profiler info. test=develop

* fix pooling bug and speed

* add 2x2s2p1 pooling. test=develop

* fix conflict, test=develop

* [LITE][PROFILE] Enhance ARM CPU profiler with real backend kernel. test=develop

movs unsqueeze frm arm to host.

[OPs] [ARM Kernel]move assign_value op into basic ops, while moving fake ops about quantization into extra to balance lib size (#3518)

* fix:modify quant_op to extra and add one basic op&kernel

* fix: move fake op to extra

* add scale+relu/relu6/leakyrelu test=develop
* fix format， test=develop

* improve 3x3s1 direct profile

* fix format, test=develop

* Optimize matmul for size(x_dims)=2  size(y_dims)>2

* [NPU] add shape bridge

move shape arm kernel to host

* enhance compare arm kernel

* [NPU] add gather op bridge

* enable reshape arm ut

* [NPU] add lookup_table bridge

* Add hard_swish, ctc_align and reciprocal op, test=develop
* Move some activation ops to extra, test=develop

 fix sequence_pool bug

* rename elementwise_sub_grad, test=develop

* rename Grad to GRAD, test=develop

* deal with case that Y@GRAD is empty, test=develop