- 14 2月, 2020 1 次提交
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由 xiaogang 提交于
fix fpga lite_tensor compile bug add fake quantize_abs_max op test=develop
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- 13 12月, 2019 1 次提交
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由 hong19860320 提交于
[LITE][NPU][XPU] Refine subgraph pass, and support NPU/XPU model generation at execution time (#2576)
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- 21 10月, 2019 1 次提交
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由 myq406450149 提交于
* add gpu kernel mul pool relu scale softmax dropout bilinear_interp and can run in tx2 * rm GREATER_EQUAL
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- 16 8月, 2019 1 次提交
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由 Yan Chunwei 提交于
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