* update proposal and psroipool kernel file in FPGA V2 track

* update, test=develop

* update FPGA v2 pe cpp file and ew kernel files, test=develop

* fix a bug of sigmoid kernel in FPGA v2 track, test=develop

* fix bugs of concat, reshape and slice op and add usleep in fpga regpoll, test=develop

* add interupt clear operation before op compute in FPGA V2 track, test=develop

* fix a bug in ewadd in FPGA v2, test=mobile

For multiple-use parameters, only copy once

修改了选kernel的逻辑，默认从模型文件中读取出lod_tensor的data type，在static_kernel_pick pass中如果kernel输入输出的类型与读取的data type完全一致，则选择该Kernel的概率增大。

- 增加 从模型文件__model__读取lod_tensor的data type到cpp::vardesc

- program中增加unordered_map<string, type>字段，并在 Program::PrepareWorkspace中对该字段赋值

- 修改了node.h文件，将const Type* 更改为Type*，并在SSAGraph::Build过程中为符合条件的type*赋值

- static_kernel_pick_pass中添加新规则，如果kernel的输入类型输出类型与__model__中存储的类型的一致，则score*=2。

- 支持模型中用到sequence_reverse_float kernel（输入输出均为float）和sequence_reverse_int64 kernel（输入输出均为int64），能够根据输入输出type选kernel

test=develop

test=develop

* add static library in tiny_publish
* move flto and ffunction-sections cmake option into the tiny publish so result of java,cxx,python 

test=develop

* add arm split lod tensor, test=develop

* add arm merge lod tensor, test=develop

* update split merge lod tensor, test=develop

* add reduce_prob op, test=develop

* support mask_rcnn succeed, test=develop

- fix fill_constant bug.
- cast op support int64_t->int32_t

update cuda kernels to run content-dnn model

* init resnet cuda int8 support
test=develop

* refine cuda unit test
test=develop

* add the forgeted file.
test=develop

* [Demo] add cxx mobilenetv1-ssd detection demo, test=develop

* add makefile to mobile detection demo, test=develop

* [Demo] add cxx mobilenetv1-ssd detection demo, test=develop

* [demo] fix mobile_detection code style, test=develop

* [Demo] fix demo code style, test=develop

* [Demo] fix detection demo makefile dependency, test=develop

test=develop

* feat: add sgemm4x4 for armv8

* fix: fix armv7 gemm choose condition

* set the bias of int8 conv as float, test=develop

test=develop

test=develop

[LITE][PASS] Fix static kernel pick pass, if op is not int8, but kernel is int8. test=develop (#2526)

test=develop

* [NPU] add reduce_mean op bridge and unit test

test=develop

* refine xpu_pass place order; add bridges use

test=develop

remove opencl place in benchmark

test=develop

* add winograd c4 implement (#2494)
test=develop
fix: fix conv_block prepack_input_nxwc4 bug
* fix: optimize sgemm_c4 in armv7
     change condition of choose winograd kernel
* fix: change conv choose kernel condition
test=develop

add elementwise_sub, mul, div op bridge

test=develop

fix bugs of concat, reshape and slice op and add usleep in fpga regpoll, test=develop，  close #2501 (#2502)

* update proposal and psroipool kernel file in FPGA V2 track

* update, test=develop

* update FPGA v2 pe cpp file and ew kernel files, test=develop

* fix a bug of sigmoid kernel in FPGA v2 track, test=develop

* fix bugs of concat, reshape and slice op and add usleep in fpga regpoll, test=develop

* add interupt clear operation before op compute in FPGA V2 track, test=develop

* fill_constant can support shape is tensor or tensorlist

fix: fix conv_block prepack_input_nxwc4 bug
* fix: optimize sgemm_c4 in armv7
     change condition of choose winograd kernel
* fix: change conv choose kernel condition