提交 dd9b1822 编写于 作者: Z zhangyang

remove extra namespaces

上级 40ee1a31
...@@ -14,36 +14,35 @@ limitations under the License. */ ...@@ -14,36 +14,35 @@ limitations under the License. */
#pragma once #pragma once
#include <stdint.h>
#include <cstddef> #include <cstddef>
#include <iostream> #include <iostream>
#include <limits> #include <limits>
// memory management; // memory management;
namespace paddle { namespace paddle_mobile {
namespace mobile {
namespace fpga { namespace fpga {
namespace api {
int open_device(); int open_device();
int close_device(); int close_device();
void *fpga_malloc(size_t size); void* fpga_malloc(size_t size);
void fpga_free(void *ptr); void fpga_free(void* ptr);
void fpga_copy(void *dst, const void *src, size_t num); void fpga_copy(void* dst, const void* src, size_t num);
struct FpgaVersionArgs { struct FpgaVersionArgs {
void *buf; void* buf;
}; };
struct MemoryToPhysicalArgs { struct MemoryToPhysicalArgs {
const void *src; const void* src;
uint64_t physical; uint64_t physical;
}; };
struct MemoryCopyArgs { struct MemoryCopyArgs {
void *src; void* src;
void *dst; void* dst;
size_t size; size_t size;
}; };
...@@ -51,38 +50,71 @@ struct FpgaQuantArgs { ...@@ -51,38 +50,71 @@ struct FpgaQuantArgs {
float scale; float scale;
}; };
struct FpgaBNArgs {}; struct FpgaBNArgs {
bool enabled = false;
void* bias_addr;
void* scale_addr;
};
struct FpgaKernelArgs {
uint32_t width;
uint32_t height;
uint32_t stride_h;
uint32_t stride_w;
};
struct FpgaImageArgs {
uint32_t width;
uint32_t height;
uint32_t channels;
uint32_t pad_h;
uint32_t pad_w;
};
struct FpgaConvArgs { struct FpgaConvArgs {
bool enable_BN = false; bool relu_enabled;
bool enable_Relu = false; struct FpgaBNArgs BNargs;
struct FpgaBNParam bn_parm; void* image_addr;
void* filter_addr;
void* bias_addr;
void* output_addr;
float quant_scale;
struct FpgaImageArgs image;
uint32_t filter_num;
uint32_t group_num;
struct FpgaKernelArgs kernel;
}; };
struct FpgaPoolArgs { struct FpgaPoolArgs {
bool enable_BN = false; void* image_addr;
struct FpgaBNParam bn_parm; void* output_addr;
struct FpgaImageArgs image;
struct FpgaKernelArgs kernel;
}; };
struct FpgaEWAddArgs { // only support X + Y struct FpgaEWAddArgs {
bool enable_Relu = false; bool relu_enabled;
void* image0_addr;
void* image1_addr;
void* result_addr;
uint32_t const0;
uint32_t const1;
uint32_t data_len; // aligned element count
}; };
int ComputeFpgaConv(struct FpgaConvArgs); int ComputeFpgaConv(struct FpgaConvArgs args);
int ComputeFpgaPool(struct FpgaPoolArgs); int ComputeFpgaPool(struct FpgaPoolArgs args);
int ComputeFpgaEWAdd(struct FpgaEWAddArgs); int ComputeFpgaEWAdd(struct FpgaEWAddArgs args);
#define IOCTL_FPGA_MAGIC 'FPGA' #define IOCTL_FPGA_MAGIC 'CNN'
#define IOCTL_VERSION _IOW(IOCTL_FPGA_MAGIC, 1, struct FpgaVersionArgs) #define IOCTL_VERSION _IOW(IOCTL_FPGA_MAGIC, 1, struct FpgaVersionArgs)
#define IOCTL_GET_QUANT _IOW(IOCTL_FPGA_MAGIC, 2, struct FpgaQuantArgs) #define IOCTL_GET_QUANT _IOW(IOCTL_FPGA_MAGIC, 2, struct FpgaQuantArgs)
#define IOCTL_SET_QUANT _IOW(IOCTL_FPGA_MAGIC, 3, struct FpgaArgs) #define IOCTL_SET_QUANT _IOW(IOCTL_FPGA_MAGIC, 3, struct FpgaQuantArgs)
#define IOCTL_MEM_COPY _IOW(IOCTL_FPGA_MAGIC, 11, struct MemoryCopyArgs) #define IOCTL_MEM_COPY _IOW(IOCTL_FPGA_MAGIC, 11, struct MemoryCopyArgs)
#define IOCTL_MEM_TOPHY _IOW(IOCTL_FPGA_MAGIC, 12, struct MemoryToPhysicalArgs)
#define IOCTL_CONFIG_CONV _IOW(IOCTL_FPGA_MAGIC, 21, struct FpgaConvArgs) #define IOCTL_CONFIG_CONV _IOW(IOCTL_FPGA_MAGIC, 21, struct FpgaConvArgs)
#define IOCTL_CONFIG_POOLING _IOW(IOCTL_FPGA_MAGIC, 22, struct FpgaPoolArgs) #define IOCTL_CONFIG_POOLING _IOW(IOCTL_FPGA_MAGIC, 22, struct FpgaPoolArgs)
#define IOCTL_CONFIG_EW _IOW(IOCTL_FPGA_MAGIC, 23, struct FpgaEWAddArgs) #define IOCTL_CONFIG_EW _IOW(IOCTL_FPGA_MAGIC, 23, struct FpgaEWAddArgs)
} // namespace api
} // namespace fpga } // namespace fpga
} // namespace mobile } // namespace paddle_mobile
} // namespace paddle
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