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提交 7034b8ae 编写于 作者: xiebaiyuan's avatar xiebaiyuan
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Merge remote-tracking branch 'upstream/develop' into develop

上级 068d5aae 9a0edc6f
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Showing with 348 addition and 482 deletion
src/fpga/api.cpp
浏览文件 @ 7034b8ae
...@@ -249,5 +249,79 @@ void format_concat_output(framework::Tensor *out, int height, int width, ...@@ -249,5 +249,79 @@ void format_concat_output(framework::Tensor *out, int height, int width,
out->reset_data_ptr(data_ptr); out->reset_data_ptr(data_ptr);
} }
void fill_conv_arg(struct WrapperConvArgs *arg, framework::Tensor *input,
framework::Tensor *out, framework::Tensor *filter,
bool relu_enabled, int group_num, int stride_h, int stride_w,
int padding_h, int padding_w, float *bs_ptr) {
auto input_ptr = input->data<float>();
auto filter_ptr = filter->data<float>();
auto out_ptr = out->mutable_data<float>();
arg->group_num = (uint32_t)group_num;
arg->split_num = (uint32_t)fpga::get_plit_num(filter);
arg->filter_num = (uint32_t)filter->dims()[0];
arg->output.address = out_ptr;
arg->output.scale_address = out->scale;
arg->conv_args = (fpga::ConvArgs *)fpga::fpga_malloc(arg->split_num *
sizeof(fpga::ConvArgs));
arg->concat_arg.image_num = arg->split_num;
arg->concat_arg.image_out = out_ptr;
arg->concat_arg.scale_out = out->scale;
arg->concat_arg.height = (uint32_t)filter->dims()[2];
arg->concat_arg.width = (uint32_t)filter->dims()[3];
int n = arg->split_num;
arg->concat_arg.images_in = (half **)fpga::fpga_malloc(n * sizeof(int *));
arg->concat_arg.scales_in = (float **)fpga::fpga_malloc(n * sizeof(float *));
arg->concat_arg.channel_num =
(uint32_t *)fpga::fpga_malloc(n * sizeof(uint32_t));
arg->concat_arg.image_out = out_ptr;
const int channel = (int)out->dims()[1];
int element_num_per_div = fpga::get_element_num_per_div(filter, group_num);
int element_num = fpga::get_aligned_filter_element_num(
filter->dims()[1] * filter->dims()[2] * filter->dims()[3]);
for (int i = 0; i < n; i++) {
arg->conv_args[i].relu_enabled = relu_enabled;
arg->conv_args[i].group_num = (uint32_t)group_num;
arg->conv_args[i].kernel.stride_h = (uint32_t)stride_h;
arg->conv_args[i].kernel.stride_w = (uint32_t)stride_w;
arg->conv_args[i].kernel.height = (uint32_t)filter->dims()[2];
arg->conv_args[i].kernel.width = (uint32_t)filter->dims()[3];
arg->conv_args[i].image.address = input_ptr;
arg->conv_args[i].image.channels = (uint32_t)input->dims()[1];
arg->conv_args[i].image.height = (uint32_t)input->dims()[2];
arg->conv_args[i].image.width = (uint32_t)input->dims()[3];
arg->conv_args[i].image.scale_address = input->scale;
arg->conv_args[i].image.pad_height = (uint32_t)padding_h;
arg->conv_args[i].image.pad_width = (uint32_t)padding_w;
arg->conv_args[i].filter_address = &((int8_t *)filter_ptr)[i * element_num];
arg->conv_args[i].sb_address = &((int8_t *)bs_ptr)[i * element_num];
arg->conv_args[i].filter_num =
(uint32_t)(i == n - 1 ? fpga::get_aligned_filter_num(
channel - (n - 1) * element_num_per_div)
: element_num_per_div);
if (n > 1) {
arg->conv_args[i].output.scale_address =
(float *)fpga::fpga_malloc(2 * sizeof(float));
arg->conv_args[i].output.address =
fpga::fpga_malloc(input->dims()[2] * input->dims()[3] *
arg->conv_args[i].filter_num * sizeof(half));
}
else {
arg->conv_args[i].output.scale_address = out->scale;
arg->conv_args[i].output.address = out_ptr;
}
arg->concat_arg.images_in[i] = (half *)arg->conv_args[i].output.address;
arg->concat_arg.scales_in[i] = (float *)arg->conv_args[i].sb_address;
arg->concat_arg.channel_num[i] = arg->conv_args[i].filter_num;
}
}
} // namespace fpga } // namespace fpga
} // namespace paddle_mobile } // namespace paddle_mobile
src/fpga/api.h
浏览文件 @ 7034b8ae
...@@ -191,14 +191,15 @@ int ComputeFpgaEWAdd(const struct EWAddArgs& args); ...@@ -191,14 +191,15 @@ int ComputeFpgaEWAdd(const struct EWAddArgs& args);
int ComputeFPGAConcat(const struct ConcatArgs& args); int ComputeFPGAConcat(const struct ConcatArgs& args);
static inline int align_to_x(int num, int x) { return (num + x - 1) / x * x; } static inline int align_to_x(int num, int x) { return (num + x - 1) / x * x; }
void format_image(framework::Tensor* image_tensor); void format_image(framework::Tensor* image_tensor);
void format_ofm(framework::Tensor* ofm_tensor); // only allocate memory void format_ofm(framework::Tensor* ofm_tensor); // only allocate memory
float filter_find_max(framework::Tensor* filter_tensor); float filter_find_max(framework::Tensor* filter_tensor);
int get_element_num_per_div(framework::Tensor* filter_tensor, int group_num); int get_element_num_per_div(framework::Tensor* filter_tensor, int group_num);
int get_plit_num(framework::Tensor* filter_tensor); int get_plit_num(framework::Tensor* filter_tensor);
int get_aligned_filter_element_num(int chw); int get_aligned_filter_element_num(int chw);
int get_aligned_filter_num(int num); int get_aligned_filter_num(int num);
void format_filter(framework::Tensor* filter_tensor, float max_value, void format_filter(framework::Tensor* filter_tensor, float max_value,
int group_num); int group_num);
void format_bias_scale_array(float** bias_scale_array, void format_bias_scale_array(float** bias_scale_array,
...@@ -206,5 +207,10 @@ void format_bias_scale_array(float** bias_scale_array, ...@@ -206,5 +207,10 @@ void format_bias_scale_array(float** bias_scale_array,
void format_concat_output(framework::Tensor* out, int height, int width, void format_concat_output(framework::Tensor* out, int height, int width,
int image_num, uint32_t* channel_num); int image_num, uint32_t* channel_num);
void fill_conv_arg(struct WrapperConvArgs* arg, framework::Tensor* input,
framework::Tensor* out, framework::Tensor* filter,
bool relu_enabled, int group_num, int stride_h, int stride_w,
int padding_h, int padding_w, float* bs_ptr);
} // namespace fpga } // namespace fpga
} // namespace paddle_mobile } // namespace paddle_mobile
src/fpga/image.cpp
浏览文件 @ 7034b8ae
...@@ -64,7 +64,40 @@ void format_image(float **data_in, int channel, int height, int width) { ...@@ -64,7 +64,40 @@ void format_image(float **data_in, int channel, int height, int width) {
void concat_images(int16_t **images_in, float **scales_in, void *image_out, void concat_images(int16_t **images_in, float **scales_in, void *image_out,
float *scale_out, int image_num, uint32_t *channel_num, float *scale_out, int image_num, uint32_t *channel_num,
int height, int width) {} int height, int width) {
int i = 0;
int j = 0;
int k = 0;
int each_out_line_channel = 0;
int align_each_out_area_cw = 0;
int align_each_in_area_cw = 0;
int align_each_out_area_cw_differ = 0;
int tmp_channel = 0;
*scale_out = 0;
for (i = 0; i < image_num; i++) {
each_out_line_channel += channel_num[i];
*scale_out = std::max(*scale_out, scales_in[i][0]);
}
align_each_out_area_cw =
align_to_x(each_out_line_channel * width, IMAGE_ALIGNMENT);
align_each_out_area_cw_differ =
align_each_out_area_cw - each_out_line_channel * width;
for (k = 0; k < height; k++) {
for (j = 0; j < width; j++) {
for (i = 0; i < image_num; i++) {
align_each_in_area_cw =
align_to_x(channel_num[i] * width, IMAGE_ALIGNMENT);
memcpy((int16_t *)image_out + tmp_channel +
k * align_each_out_area_cw_differ,
images_in[i] + j * channel_num[i] + k * align_each_in_area_cw,
channel_num[i] * sizeof(int16_t));
tmp_channel += channel_num[i];
}
}
}
}
} // namespace image } // namespace image
} // namespace fpga } // namespace fpga
......
src/operators/kernel/fpga/conv_add_bn_kernel.cpp
浏览文件 @ 7034b8ae
...@@ -60,84 +60,18 @@ bool ConvAddBNKernel<FPGA, float>::Init(FusionConvAddBNParam<FPGA> *param) { ...@@ -60,84 +60,18 @@ bool ConvAddBNKernel<FPGA, float>::Init(FusionConvAddBNParam<FPGA> *param) {
float max_value = fpga::filter_find_max(filter); float max_value = fpga::filter_find_max(filter);
fpga::format_filter(filter, max_value, param->Groups()); fpga::format_filter(filter, max_value, param->Groups());
auto filter_ptr = filter->data<float>();
int element_num_per_div = int element_num_per_div =
fpga::get_element_num_per_div(filter, param->Groups()); fpga::get_element_num_per_div(filter, param->Groups());
fpga::format_bias_scale_array(&bs_ptr, element_num_per_div, channel); fpga::format_bias_scale_array(&bs_ptr, element_num_per_div, channel);
fpga::format_ofm(out); fpga::format_ofm(out);
auto out_ptr = out->mutable_data<float>();
fpga::WrapperConvArgs conv_arg;
fpga::WrapperConvArgs convArgs; fpga::fill_conv_arg(&conv_arg, input, out, filter, relu_enabled,
convArgs.group_num = (uint32_t)param->Groups(); param->Groups(), param->Strides()[0], param->Strides()[1],
convArgs.split_num = (uint32_t)fpga::get_plit_num(filter); param->Paddings()[0], param->Paddings()[1], bs_ptr);
convArgs.filter_num = (uint32_t)filter->dims()[0]; param->SetFpgaArgs(conv_arg);
convArgs.output.address = out_ptr;
convArgs.output.scale_address = out->scale;
convArgs.conv_args = (fpga::ConvArgs *)fpga::fpga_malloc(
convArgs.split_num * sizeof(fpga::ConvArgs));
convArgs.concat_arg.image_num = convArgs.split_num;
convArgs.concat_arg.image_out = out_ptr;
convArgs.concat_arg.scale_out = out->scale;
convArgs.concat_arg.height = (uint32_t)filter->dims()[2];
convArgs.concat_arg.width = (uint32_t)filter->dims()[3];
int n = convArgs.split_num;
convArgs.concat_arg.images_in = (half **)fpga::fpga_malloc(n * sizeof(int *));
convArgs.concat_arg.scales_in =
(float **)fpga::fpga_malloc(n * sizeof(float *));
convArgs.concat_arg.channel_num =
(uint32_t *)fpga::fpga_malloc(n * sizeof(uint32_t));
convArgs.concat_arg.image_out = out_ptr;
param->SetFpgaArgs(convArgs);
int element_num = fpga::get_aligned_filter_element_num(
filter->dims()[1] * filter->dims()[2] * filter->dims()[3]);
for (int i = 0; i < n; i++) {
convArgs.conv_args[i].relu_enabled = relu_enabled;
convArgs.conv_args[i].group_num = (uint32_t)param->Groups();
convArgs.conv_args[i].kernel.stride_h = (uint32_t)param->Strides()[0];
convArgs.conv_args[i].kernel.stride_w = (uint32_t)param->Strides()[1];
convArgs.conv_args[i].kernel.height = (uint32_t)filter->dims()[2];
convArgs.conv_args[i].kernel.width = (uint32_t)filter->dims()[3];
convArgs.conv_args[i].image.address = input_ptr;
convArgs.conv_args[i].image.channels = (uint32_t)input->dims()[1];
convArgs.conv_args[i].image.height = (uint32_t)input->dims()[2];
convArgs.conv_args[i].image.width = (uint32_t)input->dims()[3];
convArgs.conv_args[i].image.scale_address = input->scale;
convArgs.conv_args[i].image.pad_height = (uint32_t)param->Paddings()[0];
convArgs.conv_args[i].image.pad_width = (uint32_t)param->Paddings()[1];
convArgs.conv_args[i].filter_address =
&((int8_t *)filter_ptr)[i * element_num];
convArgs.conv_args[i].sb_address = &((int8_t *)bs_ptr)[i * element_num];
convArgs.conv_args[i].filter_num =
(uint32_t)(i == n - 1 ? fpga::get_aligned_filter_num(
channel - (n - 1) * element_num_per_div)
: element_num_per_div);
if (n > 1) {
convArgs.conv_args[i].output.scale_address =
(float *)fpga::fpga_malloc(2 * sizeof(float));
convArgs.conv_args[i].output.address =
fpga::fpga_malloc(input->dims()[2] * input->dims()[3] *
convArgs.conv_args[i].filter_num * sizeof(half));
}
else {
convArgs.conv_args[i].output.scale_address = out->scale;
convArgs.conv_args[i].output.address = out_ptr;
}
convArgs.concat_arg.images_in[i] =
(half *)convArgs.conv_args[i].output.address;
convArgs.concat_arg.scales_in[i] =
(float *)convArgs.conv_args[i].sb_address;
convArgs.concat_arg.channel_num[i] = convArgs.conv_args[i].filter_num;
}
return true; return true;
} }
......
src/operators/kernel/fpga/conv_add_bn_relu_kernel.cpp
浏览文件 @ 7034b8ae
...@@ -67,45 +67,11 @@ bool ConvAddBNReluKernel<FPGA, float>::Init( ...@@ -67,45 +67,11 @@ bool ConvAddBNReluKernel<FPGA, float>::Init(
fpga::format_ofm(out); fpga::format_ofm(out);
auto out_ptr = out->mutable_data<float>(); auto out_ptr = out->mutable_data<float>();
fpga::WrapperConvArgs convArgs; fpga::WrapperConvArgs conv_arg;
convArgs.group_num = (uint32_t)param->Groups(); fpga::fill_conv_arg(&conv_arg, input, out, filter, relu_enabled,
convArgs.split_num = (uint32_t)fpga::get_plit_num(filter); param->Groups(), param->Strides()[0], param->Strides()[1],
convArgs.filter_num = (uint32_t)filter->dims()[0]; param->Paddings()[0], param->Paddings()[1], bs_ptr);
convArgs.output.address = out_ptr; param->SetFpgaArgs(conv_arg);
convArgs.output.scale_address = out->scale;
convArgs.conv_args = (fpga::ConvArgs *)fpga::fpga_malloc(
convArgs.split_num * sizeof(fpga::ConvArgs));
param->SetFpgaArgs(convArgs);
int element_num = fpga::get_aligned_filter_element_num(
filter->dims()[1] * filter->dims()[2] * filter->dims()[3]);
int n = convArgs.split_num;
for (int i = 0; i < n; i++) {
convArgs.conv_args[i].relu_enabled = relu_enabled;
convArgs.conv_args[i].group_num = (uint32_t)param->Groups();
convArgs.conv_args[i].kernel.stride_h = (uint32_t)param->Strides()[0];
convArgs.conv_args[i].kernel.stride_w = (uint32_t)param->Strides()[1];
convArgs.conv_args[i].kernel.height = (uint32_t)filter->dims()[2];
convArgs.conv_args[i].kernel.width = (uint32_t)filter->dims()[3];
convArgs.conv_args[i].image.address = input_ptr;
convArgs.conv_args[i].image.channels = (uint32_t)input->dims()[1];
convArgs.conv_args[i].image.height = (uint32_t)input->dims()[2];
convArgs.conv_args[i].image.width = (uint32_t)input->dims()[3];
convArgs.conv_args[i].image.pad_height = (uint32_t)param->Paddings()[0];
convArgs.conv_args[i].image.pad_width = (uint32_t)param->Paddings()[1];
convArgs.conv_args[i].filter_address =
&((int8_t *)filter_ptr)[i * element_num];
convArgs.conv_args[i].sb_address = &((int8_t *)bs_ptr)[i * element_num];
convArgs.conv_args[i].filter_num =
(uint32_t)(i == n - 1 ? fpga::get_aligned_filter_num(
channel - (n - 1) * element_num_per_div)
: element_num_per_div);
convArgs.conv_args[i].output.scale_address =
(float *)fpga::fpga_malloc(2 * sizeof(float));
convArgs.conv_args[i].image.scale_address = input->scale;
}
return true;
return true; return true;
} }
......
src/operators/kernel/fpga/conv_add_relu_kernel.cpp
浏览文件 @ 7034b8ae
...@@ -49,44 +49,11 @@ bool ConvAddReluKernel<FPGA, float>::Init(FusionConvAddReluParam<FPGA> *param) { ...@@ -49,44 +49,11 @@ bool ConvAddReluKernel<FPGA, float>::Init(FusionConvAddReluParam<FPGA> *param) {
fpga::format_ofm(out); fpga::format_ofm(out);
auto out_ptr = out->mutable_data<float>(); auto out_ptr = out->mutable_data<float>();
fpga::WrapperConvArgs convArgs; fpga::WrapperConvArgs conv_arg;
convArgs.group_num = (uint32_t)param->Groups(); fpga::fill_conv_arg(&conv_arg, input, out, filter, relu_enabled,
convArgs.split_num = (uint32_t)fpga::get_plit_num(filter); param->Groups(), param->Strides()[0], param->Strides()[1],
convArgs.filter_num = (uint32_t)filter->dims()[0]; param->Paddings()[0], param->Paddings()[1], bs_ptr);
convArgs.output.address = out_ptr; param->SetFpgaArgs(conv_arg);
convArgs.output.scale_address = out->scale;
convArgs.conv_args = (fpga::ConvArgs *)fpga::fpga_malloc(
convArgs.split_num * sizeof(fpga::ConvArgs));
param->SetFpgaArgs(convArgs);
int element_num = fpga::get_aligned_filter_element_num(
filter->dims()[1] * filter->dims()[2] * filter->dims()[3]);
int n = convArgs.split_num;
for (int i = 0; i < n; i++) {
convArgs.conv_args[i].relu_enabled = relu_enabled;
convArgs.conv_args[i].group_num = (uint32_t)param->Groups();
convArgs.conv_args[i].kernel.stride_h = (uint32_t)param->Strides()[0];
convArgs.conv_args[i].kernel.stride_w = (uint32_t)param->Strides()[1];
convArgs.conv_args[i].kernel.height = (uint32_t)filter->dims()[2];
convArgs.conv_args[i].kernel.width = (uint32_t)filter->dims()[3];
convArgs.conv_args[i].image.address = input_ptr;
convArgs.conv_args[i].image.channels = (uint32_t)input->dims()[1];
convArgs.conv_args[i].image.height = (uint32_t)input->dims()[2];
convArgs.conv_args[i].image.width = (uint32_t)input->dims()[3];
convArgs.conv_args[i].image.pad_height = (uint32_t)param->Paddings()[0];
convArgs.conv_args[i].image.pad_width = (uint32_t)param->Paddings()[1];
convArgs.conv_args[i].filter_address =
&((int8_t *)filter_ptr)[i * element_num];
convArgs.conv_args[i].sb_address = &((int8_t *)bs_ptr)[i * element_num];
convArgs.conv_args[i].filter_num =
(uint32_t)(i == n - 1 ? fpga::get_aligned_filter_num(
channel - (n - 1) * element_num_per_div)
: element_num_per_div);
convArgs.conv_args[i].output.scale_address =
(float *)fpga::fpga_malloc(2 * sizeof(float));
convArgs.conv_args[i].image.scale_address = input->scale;
}
return true; return true;
} }
......
src/operators/kernel/fpga/conv_bn_kernel.cpp
浏览文件 @ 7034b8ae
...@@ -64,44 +64,11 @@ bool ConvBNKernel<FPGA, float>::Init(FusionConvBNParam<FPGA> *param) { ...@@ -64,44 +64,11 @@ bool ConvBNKernel<FPGA, float>::Init(FusionConvBNParam<FPGA> *param) {
fpga::format_ofm(out); fpga::format_ofm(out);
auto out_ptr = out->mutable_data<float>(); auto out_ptr = out->mutable_data<float>();
fpga::WrapperConvArgs convArgs; fpga::WrapperConvArgs conv_arg;
convArgs.group_num = (uint32_t)param->Groups(); fpga::fill_conv_arg(&conv_arg, input, out, filter, relu_enabled,
convArgs.split_num = (uint32_t)fpga::get_plit_num(filter); param->Groups(), param->Strides()[0], param->Strides()[1],
convArgs.filter_num = (uint32_t)filter->dims()[0]; param->Paddings()[0], param->Paddings()[1], bs_ptr);
convArgs.output.address = out_ptr; param->SetFpgaArgs(conv_arg);
convArgs.output.scale_address = out->scale;
convArgs.conv_args = (fpga::ConvArgs *)fpga::fpga_malloc(
convArgs.split_num * sizeof(fpga::ConvArgs));
param->SetFpgaArgs(convArgs);
int element_num = fpga::get_aligned_filter_element_num(
filter->dims()[1] * filter->dims()[2] * filter->dims()[3]);
int n = convArgs.split_num;
for (int i = 0; i < n; i++) {
convArgs.conv_args[i].relu_enabled = relu_enabled;
convArgs.conv_args[i].group_num = (uint32_t)param->Groups();
convArgs.conv_args[i].kernel.stride_h = (uint32_t)param->Strides()[0];
convArgs.conv_args[i].kernel.stride_w = (uint32_t)param->Strides()[1];
convArgs.conv_args[i].kernel.height = (uint32_t)filter->dims()[2];
convArgs.conv_args[i].kernel.width = (uint32_t)filter->dims()[3];
convArgs.conv_args[i].image.address = input_ptr;
convArgs.conv_args[i].image.channels = (uint32_t)input->dims()[1];
convArgs.conv_args[i].image.height = (uint32_t)input->dims()[2];
convArgs.conv_args[i].image.width = (uint32_t)input->dims()[3];
convArgs.conv_args[i].image.pad_height = (uint32_t)param->Paddings()[0];
convArgs.conv_args[i].image.pad_width = (uint32_t)param->Paddings()[1];
convArgs.conv_args[i].filter_address =
&((int8_t *)filter_ptr)[i * element_num];
convArgs.conv_args[i].sb_address = &((int8_t *)bs_ptr)[i * element_num];
convArgs.conv_args[i].filter_num =
(uint32_t)(i == n - 1 ? fpga::get_aligned_filter_num(
channel - (n - 1) * element_num_per_div)
: element_num_per_div);
convArgs.conv_args[i].output.scale_address =
(float *)fpga::fpga_malloc(2 * sizeof(float));
convArgs.conv_args[i].image.scale_address = input->scale;
}
return true; return true;
} }
......
src/operators/kernel/fpga/conv_bn_relu_kernel.cpp
浏览文件 @ 7034b8ae
...@@ -74,31 +74,11 @@ bool ConvBNReluKernel<FPGA, float>::Init(FusionConvBNReluParam<FPGA> *param) { ...@@ -74,31 +74,11 @@ bool ConvBNReluKernel<FPGA, float>::Init(FusionConvBNReluParam<FPGA> *param) {
int element_num = fpga::get_aligned_filter_element_num( int element_num = fpga::get_aligned_filter_element_num(
filter->dims()[1] * filter->dims()[2] * filter->dims()[3]); filter->dims()[1] * filter->dims()[2] * filter->dims()[3]);
int n = convArgs.split_num; fpga::WrapperConvArgs conv_arg;
for (int i = 0; i < n; i++) { fpga::fill_conv_arg(&conv_arg, input, out, filter, relu_enabled,
convArgs.conv_args[i].relu_enabled = relu_enabled; param->Groups(), param->Strides()[0], param->Strides()[1],
convArgs.conv_args[i].group_num = (uint32_t)param->Groups(); param->Paddings()[0], param->Paddings()[1], bs_ptr);
convArgs.conv_args[i].kernel.stride_h = (uint32_t)param->Strides()[0]; param->SetFpgaArgs(conv_arg);
convArgs.conv_args[i].kernel.stride_w = (uint32_t)param->Strides()[1];
convArgs.conv_args[i].kernel.height = (uint32_t)filter->dims()[2];
convArgs.conv_args[i].kernel.width = (uint32_t)filter->dims()[3];
convArgs.conv_args[i].image.address = input_ptr;
convArgs.conv_args[i].image.channels = (uint32_t)input->dims()[1];
convArgs.conv_args[i].image.height = (uint32_t)input->dims()[2];
convArgs.conv_args[i].image.width = (uint32_t)input->dims()[3];
convArgs.conv_args[i].image.pad_height = (uint32_t)param->Paddings()[0];
convArgs.conv_args[i].image.pad_width = (uint32_t)param->Paddings()[1];
convArgs.conv_args[i].filter_address =
&((int8_t *)filter_ptr)[i * element_num];
convArgs.conv_args[i].sb_address = &((int8_t *)bs_ptr)[i * element_num];
convArgs.conv_args[i].filter_num =
(uint32_t)(i == n - 1 ? fpga::get_aligned_filter_num(
channel - (n - 1) * element_num_per_div)
: element_num_per_div);
convArgs.conv_args[i].output.scale_address =
(float *)fpga::fpga_malloc(2 * sizeof(float));
convArgs.conv_args[i].image.scale_address = input->scale;
}
return true; return true;
} }
......
src/operators/kernel/fpga/fc_relu_kernel.cpp
浏览文件 @ 7034b8ae
...@@ -54,44 +54,10 @@ bool FusionFcReluKernel<FPGA, float>::Init(FusionFcReluParam<FPGA> *param) { ...@@ -54,44 +54,10 @@ bool FusionFcReluKernel<FPGA, float>::Init(FusionFcReluParam<FPGA> *param) {
auto out_ptr = out->mutable_data<float>(); auto out_ptr = out->mutable_data<float>();
fpga::WrapperConvArgs convArgs; fpga::WrapperConvArgs conv_arg;
convArgs.group_num = 1; fpga::fill_conv_arg(&conv_arg, input_x, out, filter, relu_enabled, 1, 1, 1, 0,
convArgs.split_num = (uint32_t)fpga::get_plit_num(filter); 0, bs_ptr);
convArgs.filter_num = (uint32_t)filter->dims()[0]; param->SetFpgaArgs(conv_arg);
convArgs.output.address = out_ptr;
convArgs.output.scale_address = out->scale;
convArgs.conv_args = (fpga::ConvArgs *)fpga::fpga_malloc(
convArgs.split_num * sizeof(fpga::ConvArgs));
param->SetFpgaArgs(convArgs);
int element_num = fpga::get_aligned_filter_element_num(
filter->dims()[1] * filter->dims()[2] * filter->dims()[3]);
int n = convArgs.split_num;
for (int i = 0; i < n; i++) {
convArgs.conv_args[i].relu_enabled = relu_enabled;
convArgs.conv_args[i].group_num = 1;
convArgs.conv_args[i].kernel.stride_h = 1;
convArgs.conv_args[i].kernel.stride_w = 1;
convArgs.conv_args[i].kernel.height = (uint32_t)filter->dims()[2];
convArgs.conv_args[i].kernel.width = (uint32_t)filter->dims()[3];
convArgs.conv_args[i].image.address = input_x_ptr;
convArgs.conv_args[i].image.channels = (uint32_t)input_x->dims()[1];
convArgs.conv_args[i].image.height = (uint32_t)input_x->dims()[2];
convArgs.conv_args[i].image.width = (uint32_t)input_x->dims()[3];
convArgs.conv_args[i].image.pad_height = 0;
convArgs.conv_args[i].image.pad_width = 0;
convArgs.conv_args[i].filter_address =
&((int8_t *)filter_ptr)[i * element_num];
convArgs.conv_args[i].sb_address = &((int8_t *)bs_ptr)[i * element_num];
convArgs.conv_args[i].filter_num =
(uint32_t)(i == n - 1 ? fpga::get_aligned_filter_num(
channel - (n - 1) * element_num_per_div)
: element_num_per_div);
convArgs.conv_args[i].output.scale_address =
(float *)fpga::fpga_malloc(2 * sizeof(float));
convArgs.conv_args[i].image.scale_address = input_x->scale;
}
return true; return true;
} }
template <> template <>
......
src/operators/kernel/fpga/fusion_fc_kernel.cpp
浏览文件 @ 7034b8ae
...@@ -55,44 +55,10 @@ bool FusionFcKernel<FPGA, float>::Init(FusionFcParam<FPGA> *param) { ...@@ -55,44 +55,10 @@ bool FusionFcKernel<FPGA, float>::Init(FusionFcParam<FPGA> *param) {
auto out_ptr = out->mutable_data<float>(); auto out_ptr = out->mutable_data<float>();
fpga::WrapperConvArgs convArgs; fpga::WrapperConvArgs conv_arg;
convArgs.group_num = 1; fpga::fill_conv_arg(&conv_arg, input_x, out, filter, relu_enabled, 1, 1, 1, 0,
convArgs.split_num = (uint32_t)fpga::get_plit_num(filter); 0, bs_ptr);
convArgs.filter_num = (uint32_t)filter->dims()[0]; param->SetFpgaArgs(conv_arg);
convArgs.output.address = out_ptr;
convArgs.output.scale_address = out->scale;
convArgs.conv_args = (fpga::ConvArgs *)fpga::fpga_malloc(
convArgs.split_num * sizeof(fpga::ConvArgs));
param->SetFpgaArgs(convArgs);
int element_num = fpga::get_aligned_filter_element_num(
filter->dims()[1] * filter->dims()[2] * filter->dims()[3]);
int n = convArgs.split_num;
for (int i = 0; i < n; i++) {
convArgs.conv_args[i].relu_enabled = relu_enabled;
convArgs.conv_args[i].group_num = 1;
convArgs.conv_args[i].kernel.stride_h = 1;
convArgs.conv_args[i].kernel.stride_w = 1;
convArgs.conv_args[i].kernel.height = (uint32_t)filter->dims()[2];
convArgs.conv_args[i].kernel.width = (uint32_t)filter->dims()[3];
convArgs.conv_args[i].image.address = input_x_ptr;
convArgs.conv_args[i].image.channels = (uint32_t)input_x->dims()[1];
convArgs.conv_args[i].image.height = (uint32_t)input_x->dims()[2];
convArgs.conv_args[i].image.width = (uint32_t)input_x->dims()[3];
convArgs.conv_args[i].image.pad_height = 0;
convArgs.conv_args[i].image.pad_width = 0;
convArgs.conv_args[i].filter_address =
&((int8_t *)filter_ptr)[i * element_num];
convArgs.conv_args[i].sb_address = &((int8_t *)bs_ptr)[i * element_num];
convArgs.conv_args[i].filter_num =
(uint32_t)(i == n - 1 ? fpga::get_aligned_filter_num(
channel - (n - 1) * element_num_per_div)
: element_num_per_div);
convArgs.conv_args[i].output.scale_address =
(float *)fpga::fpga_malloc(2 * sizeof(float));
convArgs.conv_args[i].image.scale_address = input_x->scale;
}
return true; return true;
} }
......
src/operators/math/depthwise_conv_3x3.cpp
浏览文件 @ 7034b8ae
...@@ -1465,180 +1465,187 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter, ...@@ -1465,180 +1465,187 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter,
Tensor *output, const Tensor *new_scale, Tensor *output, const Tensor *new_scale,
const Tensor *new_bias, bool if_relu) { const Tensor *new_bias, bool if_relu) {
#if __ARM_NEON #if __ARM_NEON
#ifdef _OPENMP //#ifdef _OPENMP
const float *newscale_data = new_scale->data<float>(); // const float *newscale_data = new_scale->data<float>();
const float *newbias_data = new_bias->data<float>(); // const float *newbias_data = new_bias->data<float>();
//
const int batch_size = static_cast<int>(input->dims()[0]); // const int batch_size = static_cast<int>(input->dims()[0]);
const int input_channel = static_cast<int>(input->dims()[1]); // const int input_channel = static_cast<int>(input->dims()[1]);
//
const int input_height = static_cast<int>(input->dims()[2]); // const int input_height = static_cast<int>(input->dims()[2]);
const int input_width = static_cast<int>(input->dims()[3]); // const int input_width = static_cast<int>(input->dims()[3]);
const int output_height = static_cast<int>(output->dims()[2]); // const int output_height = static_cast<int>(output->dims()[2]);
const int output_width = static_cast<int>(output->dims()[3]); // const int output_width = static_cast<int>(output->dims()[3]);
const int inhxw = input_height * input_width; // const int inhxw = input_height * input_width;
const int outhxw = output_height * output_width; // const int outhxw = output_height * output_width;
//
float32x4_t zero = vdupq_n_f32(0.0); // float32x4_t zero = vdupq_n_f32(0.0);
for (int b = 0; b < batch_size; b++) { // for (int b = 0; b < batch_size; b++) {
#pragma omp parallel for // #pragma omp parallel for
for (int c = 0; c < input_channel; c++) { // for (int c = 0; c < input_channel; c++) {
const float *filter_data = filter->data<float>() + c * 9; // const float *filter_data = filter->data<float>() + c * 9;
const float *input_data = input->data<float>() + c * inhxw; // const float *input_data = input->data<float>() + c * inhxw;
float *output_data = output->data<float>() + c * outhxw; // float *output_data = output->data<float>() + c * outhxw;
float32x4_t vnewbias = vdupq_n_f32(newbias_data[c]); // float32x4_t vnewbias = vdupq_n_f32(newbias_data[c]);
float32x4_t vnewscale = vdupq_n_f32(newscale_data[c]); // float32x4_t vnewscale = vdupq_n_f32(newscale_data[c]);
//
float w00 = filter_data[0]; // float w00 = filter_data[0];
float w01 = filter_data[1]; // float w01 = filter_data[1];
float w02 = filter_data[2]; // float w02 = filter_data[2];
float w10 = filter_data[3]; // float w10 = filter_data[3];
float w11 = filter_data[4]; // float w11 = filter_data[4];
float w12 = filter_data[5]; // float w12 = filter_data[5];
float w20 = filter_data[6]; // float w20 = filter_data[6];
float w21 = filter_data[7]; // float w21 = filter_data[7];
float w22 = filter_data[8]; // float w22 = filter_data[8];
//
int m; // int m;
for (m = 1; m < output_width - 2; m = m + 3) { // for (m = 1; m < output_width - 2; m = m + 3) {
float *output_ptr = output_data + m; // float *output_ptr = output_data + m;
float32x4x2_t input_buff_mid{}, input_buff_bottom{}; // float32x4x2_t input_buff_mid{}, input_buff_bottom{};
float32x4_t in0, in1, in2, in3, tmp0, tmp1, tmp2, tmp3, out0; // float32x4_t in0, in1, in2, in3, tmp0, tmp1, tmp2, tmp3, out0;
input_buff_mid = vld2q_f32(input_data + (2 * m - 1)); // input_buff_mid = vld2q_f32(input_data + (2 * m - 1));
input_buff_bottom = vld2q_f32(input_data + input_width + (2 * m - 1)); // input_buff_bottom = vld2q_f32(input_data + input_width + (2 * m -
// 1));
in0 = input_buff_mid.val[0]; //
tmp0 = input_buff_mid.val[1]; // in0 = input_buff_mid.val[0];
tmp1 = vextq_f32(in0, zero, 1); // tmp0 = input_buff_mid.val[1];
// tmp1 = vextq_f32(in0, zero, 1);
in2 = input_buff_bottom.val[0]; //
tmp2 = input_buff_bottom.val[1]; // in2 = input_buff_bottom.val[0];
tmp3 = vextq_f32(in2, zero, 1); // tmp2 = input_buff_bottom.val[1];
// tmp3 = vextq_f32(in2, zero, 1);
out0 = vmulq_n_f32(in0, w10); //
out0 = vmlaq_n_f32(out0, tmp0, w11); // out0 = vmulq_n_f32(in0, w10);
out0 = vmlaq_n_f32(out0, tmp1, w12); // out0 = vmlaq_n_f32(out0, tmp0, w11);
out0 = vmlaq_n_f32(out0, in2, w20); // out0 = vmlaq_n_f32(out0, tmp1, w12);
out0 = vmlaq_n_f32(out0, tmp2, w21); // out0 = vmlaq_n_f32(out0, in2, w20);
out0 = vmlaq_n_f32(out0, tmp3, w22); // out0 = vmlaq_n_f32(out0, tmp2, w21);
out0 = vmlaq_f32(vnewbias, vnewscale, out0); // out0 = vmlaq_n_f32(out0, tmp3, w22);
if (if_relu) { // out0 = vmlaq_f32(vnewbias, vnewscale, out0);
out0 = vmaxq_f32(out0, zero); // if (if_relu) {
} // out0 = vmaxq_f32(out0, zero);
vst1q_lane_f32(output_ptr, out0, 0); // }
vst1q_lane_f32(output_ptr + 1, out0, 1); // vst1q_lane_f32(output_ptr, out0, 0);
vst1q_lane_f32(output_ptr + 2, out0, 2); // vst1q_lane_f32(output_ptr + 1, out0, 1);
} // vst1q_lane_f32(output_ptr + 2, out0, 2);
for (m = 1; m < output_width - 2; m += 3) { // }
} // for (m = 1; m < output_width - 2; m += 3) {
for (int j = m; j < output_width; j++) { // }
output_data[j] = input_data[2 * j - 1] * w10 + input_data[2 * j] * w11 + // for (int j = m; j < output_width; j++) {
input_data[2 * j + 1] * w12 + // output_data[j] = input_data[2 * j - 1] * w10 + input_data[2 * j] *
input_data[2 * j - 1 + input_width] * w20 + // w11 +
input_data[2 * j + input_width] * w21 + // input_data[2 * j + 1] * w12 +
input_data[2 * j + 1 + input_width] * w22; // input_data[2 * j - 1 + input_width] * w20 +
output_data[j] = newscale_data[c] * output_data[j] + newbias_data[c]; // input_data[2 * j + input_width] * w21 +
if (if_relu) { // input_data[2 * j + 1 + input_width] * w22;
output_data[j] = output_data[j] < 0 ? 0 : output_data[j]; // output_data[j] = newscale_data[c] * output_data[j] +
} // newbias_data[c]; if (if_relu) {
} // output_data[j] = output_data[j] < 0 ? 0 : output_data[j];
// }
for (int i = 1; i < output_height; i += 1) { // }
for (int m = 1; m < output_width - 2; m += 3) { //
float *output_ptr = output_data + i * output_width + m; // for (int i = 1; i < output_height; i += 1) {
float32x4x2_t input_buff_top{}, input_buff_mid{}, input_buff_bottom{}; // for (int m = 1; m < output_width - 2; m += 3) {
float32x4_t in0, in1, in2, in3, in4, in5, tmp0, tmp1, tmp2, tmp3, // float *output_ptr = output_data + i * output_width + m;
tmp4, tmp5, out0; // float32x4x2_t input_buff_top{}, input_buff_mid{},
input_buff_top = // input_buff_bottom{}; float32x4_t in0, in1, in2, in3, in4, in5,
vld2q_f32(input_data + (2 * i - 1) * input_width + (2 * m - 1)); // tmp0, tmp1, tmp2, tmp3,
input_buff_mid = // tmp4, tmp5, out0;
vld2q_f32(input_data + (2 * i) * input_width + (2 * m - 1)); // input_buff_top =
input_buff_bottom = // vld2q_f32(input_data + (2 * i - 1) * input_width + (2 * m -
vld2q_f32(input_data + (2 * i + 1) * input_width + (2 * m - 1)); // 1));
// input_buff_mid =
in0 = input_buff_top.val[0]; // vld2q_f32(input_data + (2 * i) * input_width + (2 * m - 1));
tmp0 = input_buff_top.val[1]; // input_buff_bottom =
tmp1 = vextq_f32(in0, zero, 1); // vld2q_f32(input_data + (2 * i + 1) * input_width + (2 * m -
// 1));
in2 = input_buff_mid.val[0]; //
tmp2 = input_buff_mid.val[1]; // in0 = input_buff_top.val[0];
tmp3 = vextq_f32(in2, zero, 1); // tmp0 = input_buff_top.val[1];
// tmp1 = vextq_f32(in0, zero, 1);
in4 = input_buff_bottom.val[0]; //
tmp4 = input_buff_bottom.val[1]; // in2 = input_buff_mid.val[0];
tmp5 = vextq_f32(in4, zero, 1); // tmp2 = input_buff_mid.val[1];
// tmp3 = vextq_f32(in2, zero, 1);
out0 = vmulq_n_f32(in0, w00); //
out0 = vmlaq_n_f32(out0, tmp0, w01); // in4 = input_buff_bottom.val[0];
out0 = vmlaq_n_f32(out0, tmp1, w02); // tmp4 = input_buff_bottom.val[1];
out0 = vmlaq_n_f32(out0, in2, w10); // tmp5 = vextq_f32(in4, zero, 1);
out0 = vmlaq_n_f32(out0, tmp2, w11); //
out0 = vmlaq_n_f32(out0, tmp3, w12); // out0 = vmulq_n_f32(in0, w00);
out0 = vmlaq_n_f32(out0, in4, w20); // out0 = vmlaq_n_f32(out0, tmp0, w01);
out0 = vmlaq_n_f32(out0, tmp4, w21); // out0 = vmlaq_n_f32(out0, tmp1, w02);
out0 = vmlaq_n_f32(out0, tmp5, w22); // out0 = vmlaq_n_f32(out0, in2, w10);
out0 = vmlaq_f32(vnewbias, vnewscale, out0); // out0 = vmlaq_n_f32(out0, tmp2, w11);
if (if_relu) { // out0 = vmlaq_n_f32(out0, tmp3, w12);
out0 = vmaxq_f32(out0, zero); // out0 = vmlaq_n_f32(out0, in4, w20);
} // out0 = vmlaq_n_f32(out0, tmp4, w21);
vst1q_lane_f32(output_ptr, out0, 0); // out0 = vmlaq_n_f32(out0, tmp5, w22);
vst1q_lane_f32(output_ptr + 1, out0, 1); // out0 = vmlaq_f32(vnewbias, vnewscale, out0);
vst1q_lane_f32(output_ptr + 2, out0, 2); // if (if_relu) {
} // out0 = vmaxq_f32(out0, zero);
int m; // }
for (m = 1; m < output_width - 2; m += 3) { // vst1q_lane_f32(output_ptr, out0, 0);
} // vst1q_lane_f32(output_ptr + 1, out0, 1);
for (int j = m; j < output_width; j++) { // vst1q_lane_f32(output_ptr + 2, out0, 2);
output_data[i * output_width + j] = // }
input_data[(2 * i - 1) * input_width + 2 * j - 1] * w00 + // int m;
input_data[(2 * i - 1) * input_width + 2 * j] * w01 + // for (m = 1; m < output_width - 2; m += 3) {
input_data[(2 * i - 1) * input_width + 2 * j + 1] * w02 + // }
input_data[(2 * i) * input_width + 2 * j - 1] * w10 + // for (int j = m; j < output_width; j++) {
input_data[(2 * i) * input_width + 2 * j] * w11 + // output_data[i * output_width + j] =
input_data[(2 * i) * input_width + 2 * j + 1] * w12 + // input_data[(2 * i - 1) * input_width + 2 * j - 1] * w00 +
input_data[(2 * i + 1) * input_width + 2 * j - 1] * w20 + // input_data[(2 * i - 1) * input_width + 2 * j] * w01 +
input_data[(2 * i + 1) * input_width + 2 * j] * w21 + // input_data[(2 * i - 1) * input_width + 2 * j + 1] * w02 +
input_data[(2 * i + 1) * input_width + 2 * j + 1] * w22; // input_data[(2 * i) * input_width + 2 * j - 1] * w10 +
output_data[i * output_width + j] = // input_data[(2 * i) * input_width + 2 * j] * w11 +
newscale_data[c] * output_data[i * output_width + j] + // input_data[(2 * i) * input_width + 2 * j + 1] * w12 +
newbias_data[c]; // input_data[(2 * i + 1) * input_width + 2 * j - 1] * w20 +
if (if_relu) { // input_data[(2 * i + 1) * input_width + 2 * j] * w21 +
output_data[i * output_width + j] = // input_data[(2 * i + 1) * input_width + 2 * j + 1] * w22;
output_data[i * output_width + j] < 0 // output_data[i * output_width + j] =
? 0 // newscale_data[c] * output_data[i * output_width + j] +
: output_data[i * output_width + j]; // newbias_data[c];
} // if (if_relu) {
} // output_data[i * output_width + j] =
} // output_data[i * output_width + j] < 0
output_data[0] = input_data[0] * w11 + input_data[1] * w12 + // ? 0
input_data[input_height] * w21 + // : output_data[i * output_width + j];
input_data[input_height + 1] * w22; // }
// }
output_data[0] = newscale_data[c] * output_data[0] + newbias_data[c]; // }
if (if_relu) { // output_data[0] = input_data[0] * w11 + input_data[1] * w12 +
output_data[0] = output_data[0] < 0 ? 0 : output_data[0]; // input_data[input_height] * w21 +
} // input_data[input_height + 1] * w22;
for (int i = 1; i < output_height; i++) { //
output_data[i * output_width] = // output_data[0] = newscale_data[c] * output_data[0] + newbias_data[c];
input_data[(2 * i - 1) * input_width] * w01 + // if (if_relu) {
input_data[(2 * i - 1) * input_width + 1] * w02 + // output_data[0] = output_data[0] < 0 ? 0 : output_data[0];
input_data[(2 * i) * input_width] * w11 + // }
input_data[(2 * i) * input_width + 1] * w12 + // for (int i = 1; i < output_height; i++) {
input_data[(2 * i + 1) * input_width] * w21 + // output_data[i * output_width] =
input_data[(2 * i + 1) * input_width + 1] * w22; // input_data[(2 * i - 1) * input_width] * w01 +
// input_data[(2 * i - 1) * input_width + 1] * w02 +
output_data[i * output_width] = // input_data[(2 * i) * input_width] * w11 +
newscale_data[c] * output_data[i * output_width] + newbias_data[c]; // input_data[(2 * i) * input_width + 1] * w12 +
if (if_relu) { // input_data[(2 * i + 1) * input_width] * w21 +
output_data[i * output_width] = output_data[i * output_width] < 0 // input_data[(2 * i + 1) * input_width + 1] * w22;
? 0 //
: output_data[i * output_width]; // output_data[i * output_width] =
} // newscale_data[c] * output_data[i * output_width] +
} // newbias_data[c];
} // if (if_relu) {
} // output_data[i * output_width] = output_data[i * output_width] < 0
// ? 0
#else // : output_data[i *
// output_width];
// }
// }
// }
// }
//
//#else
const float *input_data = input->data<float>(); const float *input_data = input->data<float>();
const float *filter_data = filter->data<float>(); const float *filter_data = filter->data<float>();
...@@ -1646,9 +1653,6 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter, ...@@ -1646,9 +1653,6 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter,
const float *newscale_data = new_scale->data<float>(); const float *newscale_data = new_scale->data<float>();
const float *newbias_data = new_bias->data<float>(); const float *newbias_data = new_bias->data<float>();
float32x4_t vnewbias = vdupq_n_f32(0.0);
float32x4_t vnewscale = vdupq_n_f32(1.0);
const int in_h = static_cast<int>(input->dims()[2]); const int in_h = static_cast<int>(input->dims()[2]);
const int in_w = static_cast<int>(input->dims()[3]); const int in_w = static_cast<int>(input->dims()[3]);
const int out_h = static_cast<int>(output->dims()[2]); const int out_h = static_cast<int>(output->dims()[2]);
...@@ -1660,22 +1664,22 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter, ...@@ -1660,22 +1664,22 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter,
const int if_pad = in_l - 1 == (out_l - 1) * 2 ? 1 : 0; const int if_pad = in_l - 1 == (out_l - 1) * 2 ? 1 : 0;
const int batch_size = static_cast<int>(input->dims()[0]); const int batch_size = static_cast<int>(input->dims()[0]);
const int c = static_cast<int>(input->dims()[1]); const int c = static_cast<int>(input->dims()[1]);
const float *input_row_ptr;
float *output_row_ptr;
const int w_times = (out_w - 2) / 3; const int w_times = (out_w - 2) / 3;
float32x4x2_t input_buff_mid{}, input_buff_bottom[w_times + 1];
float32x4_t elewise_res0, elewise_res1, elewise_res2, res3;
int out2in_mid;
float32x4_t zero = vdupq_n_f32(0.0); float32x4_t zero = vdupq_n_f32(0.0);
for (int b = batch_size; b > 0; --b) { for (int b = batch_size; b > 0; --b) {
const float *filter_data_tmp = filter_data; #pragma omp parallel for
for (int j = 0; j < c; ++j) { for (int j = 0; j < c; j++) {
const float *input_row_ptr;
float *output_row_ptr;
float32x4x2_t input_buff_mid{}, input_buff_bottom[w_times + 1];
float32x4_t elewise_res0, elewise_res1, elewise_res2, res3;
int out2in_mid;
float32x4_t vnewbias = vdupq_n_f32(0.0);
float32x4_t vnewscale = vdupq_n_f32(1.0);
auto output_data_tmp = output_data + j * out_h * out_w; auto output_data_tmp = output_data + j * out_h * out_w;
auto input_data_tmp = input_data + j * in_h * in_w; auto input_data_tmp = input_data + j * in_h * in_w;
auto input_const = input_data_tmp; auto input_const = input_data_tmp;
const float *filter_data_tmp = filter_data + 9 * j;
vnewbias = vdupq_n_f32(newbias_data[j]); vnewbias = vdupq_n_f32(newbias_data[j]);
vnewscale = vdupq_n_f32(newscale_data[j]); vnewscale = vdupq_n_f32(newscale_data[j]);
...@@ -1726,7 +1730,9 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter, ...@@ -1726,7 +1730,9 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter,
if (if_relu) { if (if_relu) {
res3 = vmaxq_f32(res3, zero); res3 = vmaxq_f32(res3, zero);
} }
vst1q_f32(output_row_ptr, res3); vst1q_lane_f32(output_row_ptr, res3, 0);
vst1q_lane_f32(output_row_ptr + 1, res3, 1);
vst1q_lane_f32(output_row_ptr + 2, res3, 2);
input_row_ptr += 6; input_row_ptr += 6;
output_row_ptr += 3; output_row_ptr += 3;
...@@ -1765,7 +1771,9 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter, ...@@ -1765,7 +1771,9 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter,
res3 = vmaxq_f32(res3, zero); res3 = vmaxq_f32(res3, zero);
} }
if ((w4 != w_times)) { if ((w4 != w_times)) {
vst1q_f32(output_row_ptr, res3); vst1q_lane_f32(output_row_ptr, res3, 0);
vst1q_lane_f32(output_row_ptr + 1, res3, 1);
vst1q_lane_f32(output_row_ptr + 2, res3, 2);
} else { } else {
if (out_l - 2 - w_times * 3 == 1) { if (out_l - 2 - w_times * 3 == 1) {
vst1q_lane_f32(output_row_ptr, res3, 0); vst1q_lane_f32(output_row_ptr, res3, 0);
...@@ -1865,12 +1873,11 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter, ...@@ -1865,12 +1873,11 @@ void DepthwiseConvAddBNRelu3x3s2p1v2(const Tensor *input, const Tensor *filter,
: output_data_tmp[i * out_l + out_l - 1]; : output_data_tmp[i * out_l + out_l - 1];
} }
} }
filter_data_tmp += 9;
} }
input_data += inhxw * c; input_data += inhxw * c;
output_data += outhxw * c; output_data += outhxw * c;
} }
#endif //#endif
#endif #endif
} }
......
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