提交 50b074a6 编写于 作者: Z zhangyang

change format

上级 d8f5dc50
...@@ -52,21 +52,20 @@ class FusionConvAddBNMatcher : public framework::FusionOpMatcher { ...@@ -52,21 +52,20 @@ class FusionConvAddBNMatcher : public framework::FusionOpMatcher {
}; };
template <typename DeviceType, typename T> template <typename DeviceType, typename T>
class FusionConvAddBNOp class FusionConvAddBNOp : public framework::OperatorWithKernel<
: public framework::OperatorWithKernel< DeviceType, FusionConvAddBNParam,
DeviceType, FusionConvAddBNParam, operators::ConvAddBNKernel<DeviceType, T>> {
operators::ConvAddBNKernel<DeviceType, T>> {
public: public:
FusionConvAddBNOp(const string &type, const VariableNameMap &inputs, FusionConvAddBNOp(const string &type, const VariableNameMap &inputs,
const VariableNameMap &outputs, const VariableNameMap &outputs,
const framework::AttributeMap &attrs, const framework::AttributeMap &attrs,
std::shared_ptr<framework::Scope> scope) std::shared_ptr<framework::Scope> scope)
: framework::OperatorWithKernel< : framework::OperatorWithKernel<
DeviceType, FusionConvAddBNParam, DeviceType, FusionConvAddBNParam,
operators::ConvAddBNKernel<DeviceType, T>>( operators::ConvAddBNKernel<DeviceType, T>>(type, inputs, outputs,
type, inputs, outputs, attrs, scope) {} attrs, scope) {}
void InferShape() const override; void InferShape() const override;
protected: protected:
}; };
......
...@@ -32,8 +32,7 @@ using framework::DDim; ...@@ -32,8 +32,7 @@ using framework::DDim;
using framework::OpKernelBase; using framework::OpKernelBase;
template <typename DeviceType, typename T> template <typename DeviceType, typename T>
class ConvAddBNKernel class ConvAddBNKernel : public OpKernelBase<DeviceType, FusionConvAddBNParam> {
: public OpKernelBase<DeviceType, FusionConvAddBNParam> {
public: public:
void Compute(const FusionConvAddBNParam &param) const; void Compute(const FusionConvAddBNParam &param) const;
bool Init(FusionConvAddBNParam *param); bool Init(FusionConvAddBNParam *param);
......
...@@ -36,7 +36,8 @@ bool ConvAddBNKernel<FPGA, float>::Init(FusionConvAddBNParam *param) { ...@@ -36,7 +36,8 @@ bool ConvAddBNKernel<FPGA, float>::Init(FusionConvAddBNParam *param) {
auto bn_scale_ptr = param->InputScale()->data<float>(); auto bn_scale_ptr = param->InputScale()->data<float>();
auto bn_bias_ptr = param->InputBias()->data<float>(); auto bn_bias_ptr = param->InputBias()->data<float>();
const float epsilon = param->Epsilon(); const float epsilon = param->Epsilon();
PADDLE_MOBILE_ENFORCE(input->dims()[1] == bias->dims()[0] && bias->dims()[0] == param->InputBias()->dims()[0], PADDLE_MOBILE_ENFORCE(input->dims()[1] == bias->dims()[0] &&
bias->dims()[0] == param->InputBias()->dims()[0],
"Image channel should be equal to bias number"); "Image channel should be equal to bias number");
const int channel = input->dims()[1]; const int channel = input->dims()[1];
...@@ -47,39 +48,42 @@ bool ConvAddBNKernel<FPGA, float>::Init(FusionConvAddBNParam *param) { ...@@ -47,39 +48,42 @@ bool ConvAddBNKernel<FPGA, float>::Init(FusionConvAddBNParam *param) {
auto new_bias_ptr = new_bias->mutable_data<float>({channel}); auto new_bias_ptr = new_bias->mutable_data<float>({channel});
for (int i = 0; i < channel; i++) { for (int i = 0; i < channel; i++) {
new_scale_ptr[i] = bn_scale_ptr[i] / static_cast<float>(pow((bn_var_ptr[i] + epsilon), 0.5)); new_scale_ptr[i] = bn_scale_ptr[i] /
new_bias_ptr[i] = bn_bias_ptr[i] +(bias_ptr[i] - bn_mean_ptr[i]) * new_scale_ptr[i]; static_cast<float>(pow((bn_var_ptr[i] + epsilon), 0.5));
bs_ptr[i*2] = new_scale_ptr[i]; new_bias_ptr[i] =
bs_ptr[i*2 + 1] = new_bias_ptr[i]; bn_bias_ptr[i] + (bias_ptr[i] - bn_mean_ptr[i]) * new_scale_ptr[i];
bs_ptr[i * 2] = new_scale_ptr[i];
bs_ptr[i * 2 + 1] = new_bias_ptr[i];
} }
param->SetNewScale(new_scale); param->SetNewScale(new_scale);
param->SetNewBias(new_bias); param->SetNewBias(new_bias);
fpga::ConvArgs convArgs; fpga::ConvArgs convArgs;
convArgs.relu_enabled = relu_enabled; convArgs.relu_enabled = relu_enabled;
convArgs.filter_address = (void*)filter_ptr; convArgs.filter_address = (void *)filter_ptr;
convArgs.filter_num = filter->dims()[0]; convArgs.filter_num = filter->dims()[0];
convArgs.group_num = param->Groups(); convArgs.group_num = param->Groups();
convArgs.sb_address = (void*)bs_ptr; convArgs.sb_address = (void *)bs_ptr;
convArgs.kernel.stride_h = param->Strides()[0]; convArgs.kernel.stride_h = param->Strides()[0];
convArgs.kernel.stride_w = param->Strides()[1]; convArgs.kernel.stride_w = param->Strides()[1];
convArgs.kernel.height = filter->dims()[2]; convArgs.kernel.height = filter->dims()[2];
convArgs.kernel.width = filter->dims()[3]; convArgs.kernel.width = filter->dims()[3];
convArgs.image.address = (void*)input_ptr; convArgs.image.address = (void *)input_ptr;
convArgs.image.channels = input->dims()[1]; convArgs.image.channels = input->dims()[1];
convArgs.image.height = input->dims()[2]; convArgs.image.height = input->dims()[2];
convArgs.image.width = input->dims()[3]; convArgs.image.width = input->dims()[3];
convArgs.image.pad_height = param->Paddings()[0]; convArgs.image.pad_height = param->Paddings()[0];
convArgs.image.pad_width = param->Paddings()[1]; convArgs.image.pad_width = param->Paddings()[1];
convArgs.image.scale_address = input->fpga_args().scale_pointer(); convArgs.image.scale_address = input->fpga_args().scale_pointer();
convArgs.output.address = (void*)out_ptr; convArgs.output.address = (void *)out_ptr;
convArgs.output.scale_address = out->fpga_args().scale_pointer(); convArgs.output.scale_address = out->fpga_args().scale_pointer();
param->SetFpgaArgs(convArgs); param->SetFpgaArgs(convArgs);
return true; return true;
} }
template <> template <>
void ConvAddBNKernel<FPGA, float>::Compute(const FusionConvAddBNParam &param) const { void ConvAddBNKernel<FPGA, float>::Compute(
const FusionConvAddBNParam &param) const {
fpga::ComputeFpgaConv(param.FpgaArgs()); fpga::ComputeFpgaConv(param.FpgaArgs());
} }
template class ConvAddBNKernel<FPGA, float>; template class ConvAddBNKernel<FPGA, float>;
......
...@@ -36,7 +36,8 @@ bool ConvAddBNReluKernel<FPGA, float>::Init(FusionConvAddBNReluParam *param) { ...@@ -36,7 +36,8 @@ bool ConvAddBNReluKernel<FPGA, float>::Init(FusionConvAddBNReluParam *param) {
auto bn_scale_ptr = param->InputScale()->data<float>(); auto bn_scale_ptr = param->InputScale()->data<float>();
auto bn_bias_ptr = param->InputBias()->data<float>(); auto bn_bias_ptr = param->InputBias()->data<float>();
const float epsilon = param->Epsilon(); const float epsilon = param->Epsilon();
PADDLE_MOBILE_ENFORCE(input->dims()[1] == bias->dims()[0] && bias->dims()[0] == param->InputBias()->dims()[0], PADDLE_MOBILE_ENFORCE(input->dims()[1] == bias->dims()[0] &&
bias->dims()[0] == param->InputBias()->dims()[0],
"Image channel should be equal to bias number"); "Image channel should be equal to bias number");
const int channel = input->dims()[1]; const int channel = input->dims()[1];
...@@ -47,39 +48,42 @@ bool ConvAddBNReluKernel<FPGA, float>::Init(FusionConvAddBNReluParam *param) { ...@@ -47,39 +48,42 @@ bool ConvAddBNReluKernel<FPGA, float>::Init(FusionConvAddBNReluParam *param) {
auto new_bias_ptr = new_bias->mutable_data<float>({channel}); auto new_bias_ptr = new_bias->mutable_data<float>({channel});
for (int i = 0; i < channel; i++) { for (int i = 0; i < channel; i++) {
new_scale_ptr[i] = bn_scale_ptr[i] / static_cast<float>(pow((bn_var_ptr[i] + epsilon), 0.5)); new_scale_ptr[i] = bn_scale_ptr[i] /
new_bias_ptr[i] = bn_bias_ptr[i] +(bias_ptr[i] - bn_mean_ptr[i]) * new_scale_ptr[i]; static_cast<float>(pow((bn_var_ptr[i] + epsilon), 0.5));
bs_ptr[i*2] = new_scale_ptr[i]; new_bias_ptr[i] =
bs_ptr[i*2 + 1] = new_bias_ptr[i]; bn_bias_ptr[i] + (bias_ptr[i] - bn_mean_ptr[i]) * new_scale_ptr[i];
bs_ptr[i * 2] = new_scale_ptr[i];
bs_ptr[i * 2 + 1] = new_bias_ptr[i];
} }
param->SetNewScale(new_scale); param->SetNewScale(new_scale);
param->SetNewBias(new_bias); param->SetNewBias(new_bias);
fpga::ConvArgs convArgs; fpga::ConvArgs convArgs;
convArgs.relu_enabled = relu_enabled; convArgs.relu_enabled = relu_enabled;
convArgs.filter_address = (void*)filter_ptr; convArgs.filter_address = (void *)filter_ptr;
convArgs.filter_num = filter->dims()[0]; convArgs.filter_num = filter->dims()[0];
convArgs.group_num = param->Groups(); convArgs.group_num = param->Groups();
convArgs.sb_address = (void*)bs_ptr; convArgs.sb_address = (void *)bs_ptr;
convArgs.kernel.stride_h = param->Strides()[0]; convArgs.kernel.stride_h = param->Strides()[0];
convArgs.kernel.stride_w = param->Strides()[1]; convArgs.kernel.stride_w = param->Strides()[1];
convArgs.kernel.height = filter->dims()[2]; convArgs.kernel.height = filter->dims()[2];
convArgs.kernel.width = filter->dims()[3]; convArgs.kernel.width = filter->dims()[3];
convArgs.image.address = (void*)input_ptr; convArgs.image.address = (void *)input_ptr;
convArgs.image.channels = input->dims()[1]; convArgs.image.channels = input->dims()[1];
convArgs.image.height = input->dims()[2]; convArgs.image.height = input->dims()[2];
convArgs.image.width = input->dims()[3]; convArgs.image.width = input->dims()[3];
convArgs.image.pad_height = param->Paddings()[0]; convArgs.image.pad_height = param->Paddings()[0];
convArgs.image.pad_width = param->Paddings()[1]; convArgs.image.pad_width = param->Paddings()[1];
convArgs.image.scale_address = input->fpga_args().scale_pointer(); convArgs.image.scale_address = input->fpga_args().scale_pointer();
convArgs.output.address = (void*)out_ptr; convArgs.output.address = (void *)out_ptr;
convArgs.output.scale_address = out->fpga_args().scale_pointer(); convArgs.output.scale_address = out->fpga_args().scale_pointer();
param->SetFpgaArgs(convArgs); param->SetFpgaArgs(convArgs);
return true; return true;
} }
template <> template <>
void ConvAddBNReluKernel<FPGA, float>::Compute(const FusionConvAddBNReluParam &param) const { void ConvAddBNReluKernel<FPGA, float>::Compute(
const FusionConvAddBNReluParam &param) const {
fpga::ComputeFpgaConv(param.FpgaArgs()); fpga::ComputeFpgaConv(param.FpgaArgs());
} }
template class ConvAddBNReluKernel<FPGA, float>; template class ConvAddBNReluKernel<FPGA, float>;
......
...@@ -32,25 +32,26 @@ bool ConvAddReluKernel<FPGA, float>::Init(FusionConvAddReluParam *param) { ...@@ -32,25 +32,26 @@ bool ConvAddReluKernel<FPGA, float>::Init(FusionConvAddReluParam *param) {
Tensor *out = param->Output(); Tensor *out = param->Output();
auto out_ptr = out->mutable_data<float>(); auto out_ptr = out->mutable_data<float>();
PADDLE_MOBILE_ENFORCE(input->dims()[1] == bias->dims()[0], "Image channel should be equal to bias number"); PADDLE_MOBILE_ENFORCE(input->dims()[1] == bias->dims()[0],
"Image channel should be equal to bias number");
int channel = input->dims()[1]; int channel = input->dims()[1];
float *bs_ptr = (float *)fpga::fpga_malloc(2 * channel * sizeof(float)); float *bs_ptr = (float *)fpga::fpga_malloc(2 * channel * sizeof(float));
for (int i=0; i<channel; i++){ for (int i = 0; i < channel; i++) {
bs_ptr[i*2] = 1; bs_ptr[i * 2] = 1;
bs_ptr[i*2 + 1] = bias_ptr[i]; bs_ptr[i * 2 + 1] = bias_ptr[i];
} }
fpga::ConvArgs convArgs; fpga::ConvArgs convArgs;
convArgs.relu_enabled = relu_enabled; convArgs.relu_enabled = relu_enabled;
convArgs.filter_address = (void*)filter_ptr; convArgs.filter_address = (void *)filter_ptr;
convArgs.filter_num = filter->dims()[0]; convArgs.filter_num = filter->dims()[0];
convArgs.group_num = param->Groups(); convArgs.group_num = param->Groups();
convArgs.sb_address = (void*)bs_ptr; convArgs.sb_address = (void *)bs_ptr;
convArgs.kernel.stride_h = param->Strides()[0]; convArgs.kernel.stride_h = param->Strides()[0];
convArgs.kernel.stride_w = param->Strides()[1]; convArgs.kernel.stride_w = param->Strides()[1];
convArgs.kernel.height = filter->dims()[2]; convArgs.kernel.height = filter->dims()[2];
convArgs.kernel.width = filter->dims()[3]; convArgs.kernel.width = filter->dims()[3];
convArgs.image.address = (void*)input_ptr; convArgs.image.address = (void *)input_ptr;
convArgs.image.channels = input->dims()[1]; convArgs.image.channels = input->dims()[1];
convArgs.image.height = input->dims()[2]; convArgs.image.height = input->dims()[2];
convArgs.image.width = input->dims()[3]; convArgs.image.width = input->dims()[3];
...@@ -58,14 +59,15 @@ bool ConvAddReluKernel<FPGA, float>::Init(FusionConvAddReluParam *param) { ...@@ -58,14 +59,15 @@ bool ConvAddReluKernel<FPGA, float>::Init(FusionConvAddReluParam *param) {
convArgs.image.pad_height = param->Paddings()[0]; convArgs.image.pad_height = param->Paddings()[0];
convArgs.image.pad_width = param->Paddings()[1]; convArgs.image.pad_width = param->Paddings()[1];
convArgs.image.scale_address = input->fpga_args().scale_pointer(); convArgs.image.scale_address = input->fpga_args().scale_pointer();
convArgs.output.address = (void*)out_ptr; convArgs.output.address = (void *)out_ptr;
convArgs.output.scale_address = out->fpga_args().scale_pointer(); convArgs.output.scale_address = out->fpga_args().scale_pointer();
param->SetFpgaArgs(convArgs); param->SetFpgaArgs(convArgs);
return true; return true;
} }
template <> template <>
void ConvAddReluKernel<FPGA, float>::Compute(const FusionConvAddReluParam &param) const { void ConvAddReluKernel<FPGA, float>::Compute(
const FusionConvAddReluParam &param) const {
fpga::ComputeFpgaConv(param.FpgaArgs()); fpga::ComputeFpgaConv(param.FpgaArgs());
} }
template class ConvAddReluKernel<FPGA, float>; template class ConvAddReluKernel<FPGA, float>;
......
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