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50b074a6
编写于
8月 03, 2018
作者:
Z
zhangyang
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
change format
上级
d8f5dc50
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
49 addition
and
41 deletion
+49
-41
src/operators/fusion_conv_add_bn_op.h
src/operators/fusion_conv_add_bn_op.h
+9
-10
src/operators/kernel/conv_add_bn_kernel.h
src/operators/kernel/conv_add_bn_kernel.h
+1
-2
src/operators/kernel/fpga/conv_add_bn_kernel.cpp
src/operators/kernel/fpga/conv_add_bn_kernel.cpp
+14
-10
src/operators/kernel/fpga/conv_add_bn_relu_kernel.cpp
src/operators/kernel/fpga/conv_add_bn_relu_kernel.cpp
+14
-10
src/operators/kernel/fpga/conv_add_relu_kernel.cpp
src/operators/kernel/fpga/conv_add_relu_kernel.cpp
+11
-9
未找到文件。
src/operators/fusion_conv_add_bn_op.h
浏览文件 @
50b074a6
...
...
@@ -52,21 +52,20 @@ class FusionConvAddBNMatcher : public framework::FusionOpMatcher {
};
template
<
typename
DeviceType
,
typename
T
>
class
FusionConvAddBNOp
:
public
framework
::
OperatorWithKernel
<
DeviceType
,
FusionConvAddBNParam
,
operators
::
ConvAddBNKernel
<
DeviceType
,
T
>>
{
class
FusionConvAddBNOp
:
public
framework
::
OperatorWithKernel
<
DeviceType
,
FusionConvAddBNParam
,
operators
::
ConvAddBNKernel
<
DeviceType
,
T
>>
{
public:
FusionConvAddBNOp
(
const
string
&
type
,
const
VariableNameMap
&
inputs
,
const
VariableNameMap
&
outputs
,
const
framework
::
AttributeMap
&
attrs
,
std
::
shared_ptr
<
framework
::
Scope
>
scope
)
const
VariableNameMap
&
outputs
,
const
framework
::
AttributeMap
&
attrs
,
std
::
shared_ptr
<
framework
::
Scope
>
scope
)
:
framework
::
OperatorWithKernel
<
DeviceType
,
FusionConvAddBNParam
,
operators
::
ConvAddBNKernel
<
DeviceType
,
T
>>
(
type
,
inputs
,
outputs
,
attrs
,
scope
)
{}
operators
::
ConvAddBNKernel
<
DeviceType
,
T
>>
(
type
,
inputs
,
outputs
,
attrs
,
scope
)
{}
void
InferShape
()
const
override
;
void
InferShape
()
const
override
;
protected:
};
...
...
src/operators/kernel/conv_add_bn_kernel.h
浏览文件 @
50b074a6
...
...
@@ -32,8 +32,7 @@ using framework::DDim;
using
framework
::
OpKernelBase
;
template
<
typename
DeviceType
,
typename
T
>
class
ConvAddBNKernel
:
public
OpKernelBase
<
DeviceType
,
FusionConvAddBNParam
>
{
class
ConvAddBNKernel
:
public
OpKernelBase
<
DeviceType
,
FusionConvAddBNParam
>
{
public:
void
Compute
(
const
FusionConvAddBNParam
&
param
)
const
;
bool
Init
(
FusionConvAddBNParam
*
param
);
...
...
src/operators/kernel/fpga/conv_add_bn_kernel.cpp
浏览文件 @
50b074a6
...
...
@@ -36,7 +36,8 @@ bool ConvAddBNKernel<FPGA, float>::Init(FusionConvAddBNParam *param) {
auto
bn_scale_ptr
=
param
->
InputScale
()
->
data
<
float
>
();
auto
bn_bias_ptr
=
param
->
InputBias
()
->
data
<
float
>
();
const
float
epsilon
=
param
->
Epsilon
();
PADDLE_MOBILE_ENFORCE
(
input
->
dims
()[
1
]
==
bias
->
dims
()[
0
]
&&
bias
->
dims
()[
0
]
==
param
->
InputBias
()
->
dims
()[
0
],
PADDLE_MOBILE_ENFORCE
(
input
->
dims
()[
1
]
==
bias
->
dims
()[
0
]
&&
bias
->
dims
()[
0
]
==
param
->
InputBias
()
->
dims
()[
0
],
"Image channel should be equal to bias number"
);
const
int
channel
=
input
->
dims
()[
1
];
...
...
@@ -47,39 +48,42 @@ bool ConvAddBNKernel<FPGA, float>::Init(FusionConvAddBNParam *param) {
auto
new_bias_ptr
=
new_bias
->
mutable_data
<
float
>
({
channel
});
for
(
int
i
=
0
;
i
<
channel
;
i
++
)
{
new_scale_ptr
[
i
]
=
bn_scale_ptr
[
i
]
/
static_cast
<
float
>
(
pow
((
bn_var_ptr
[
i
]
+
epsilon
),
0.5
));
new_bias_ptr
[
i
]
=
bn_bias_ptr
[
i
]
+
(
bias_ptr
[
i
]
-
bn_mean_ptr
[
i
])
*
new_scale_ptr
[
i
];
bs_ptr
[
i
*
2
]
=
new_scale_ptr
[
i
];
bs_ptr
[
i
*
2
+
1
]
=
new_bias_ptr
[
i
];
new_scale_ptr
[
i
]
=
bn_scale_ptr
[
i
]
/
static_cast
<
float
>
(
pow
((
bn_var_ptr
[
i
]
+
epsilon
),
0.5
));
new_bias_ptr
[
i
]
=
bn_bias_ptr
[
i
]
+
(
bias_ptr
[
i
]
-
bn_mean_ptr
[
i
])
*
new_scale_ptr
[
i
];
bs_ptr
[
i
*
2
]
=
new_scale_ptr
[
i
];
bs_ptr
[
i
*
2
+
1
]
=
new_bias_ptr
[
i
];
}
param
->
SetNewScale
(
new_scale
);
param
->
SetNewBias
(
new_bias
);
fpga
::
ConvArgs
convArgs
;
convArgs
.
relu_enabled
=
relu_enabled
;
convArgs
.
filter_address
=
(
void
*
)
filter_ptr
;
convArgs
.
filter_address
=
(
void
*
)
filter_ptr
;
convArgs
.
filter_num
=
filter
->
dims
()[
0
];
convArgs
.
group_num
=
param
->
Groups
();
convArgs
.
sb_address
=
(
void
*
)
bs_ptr
;
convArgs
.
sb_address
=
(
void
*
)
bs_ptr
;
convArgs
.
kernel
.
stride_h
=
param
->
Strides
()[
0
];
convArgs
.
kernel
.
stride_w
=
param
->
Strides
()[
1
];
convArgs
.
kernel
.
height
=
filter
->
dims
()[
2
];
convArgs
.
kernel
.
width
=
filter
->
dims
()[
3
];
convArgs
.
image
.
address
=
(
void
*
)
input_ptr
;
convArgs
.
image
.
address
=
(
void
*
)
input_ptr
;
convArgs
.
image
.
channels
=
input
->
dims
()[
1
];
convArgs
.
image
.
height
=
input
->
dims
()[
2
];
convArgs
.
image
.
width
=
input
->
dims
()[
3
];
convArgs
.
image
.
pad_height
=
param
->
Paddings
()[
0
];
convArgs
.
image
.
pad_width
=
param
->
Paddings
()[
1
];
convArgs
.
image
.
scale_address
=
input
->
fpga_args
().
scale_pointer
();
convArgs
.
output
.
address
=
(
void
*
)
out_ptr
;
convArgs
.
output
.
address
=
(
void
*
)
out_ptr
;
convArgs
.
output
.
scale_address
=
out
->
fpga_args
().
scale_pointer
();
param
->
SetFpgaArgs
(
convArgs
);
return
true
;
}
template
<
>
void
ConvAddBNKernel
<
FPGA
,
float
>::
Compute
(
const
FusionConvAddBNParam
&
param
)
const
{
void
ConvAddBNKernel
<
FPGA
,
float
>::
Compute
(
const
FusionConvAddBNParam
&
param
)
const
{
fpga
::
ComputeFpgaConv
(
param
.
FpgaArgs
());
}
template
class
ConvAddBNKernel
<
FPGA
,
float
>;
...
...
src/operators/kernel/fpga/conv_add_bn_relu_kernel.cpp
浏览文件 @
50b074a6
...
...
@@ -36,7 +36,8 @@ bool ConvAddBNReluKernel<FPGA, float>::Init(FusionConvAddBNReluParam *param) {
auto
bn_scale_ptr
=
param
->
InputScale
()
->
data
<
float
>
();
auto
bn_bias_ptr
=
param
->
InputBias
()
->
data
<
float
>
();
const
float
epsilon
=
param
->
Epsilon
();
PADDLE_MOBILE_ENFORCE
(
input
->
dims
()[
1
]
==
bias
->
dims
()[
0
]
&&
bias
->
dims
()[
0
]
==
param
->
InputBias
()
->
dims
()[
0
],
PADDLE_MOBILE_ENFORCE
(
input
->
dims
()[
1
]
==
bias
->
dims
()[
0
]
&&
bias
->
dims
()[
0
]
==
param
->
InputBias
()
->
dims
()[
0
],
"Image channel should be equal to bias number"
);
const
int
channel
=
input
->
dims
()[
1
];
...
...
@@ -47,39 +48,42 @@ bool ConvAddBNReluKernel<FPGA, float>::Init(FusionConvAddBNReluParam *param) {
auto
new_bias_ptr
=
new_bias
->
mutable_data
<
float
>
({
channel
});
for
(
int
i
=
0
;
i
<
channel
;
i
++
)
{
new_scale_ptr
[
i
]
=
bn_scale_ptr
[
i
]
/
static_cast
<
float
>
(
pow
((
bn_var_ptr
[
i
]
+
epsilon
),
0.5
));
new_bias_ptr
[
i
]
=
bn_bias_ptr
[
i
]
+
(
bias_ptr
[
i
]
-
bn_mean_ptr
[
i
])
*
new_scale_ptr
[
i
];
bs_ptr
[
i
*
2
]
=
new_scale_ptr
[
i
];
bs_ptr
[
i
*
2
+
1
]
=
new_bias_ptr
[
i
];
new_scale_ptr
[
i
]
=
bn_scale_ptr
[
i
]
/
static_cast
<
float
>
(
pow
((
bn_var_ptr
[
i
]
+
epsilon
),
0.5
));
new_bias_ptr
[
i
]
=
bn_bias_ptr
[
i
]
+
(
bias_ptr
[
i
]
-
bn_mean_ptr
[
i
])
*
new_scale_ptr
[
i
];
bs_ptr
[
i
*
2
]
=
new_scale_ptr
[
i
];
bs_ptr
[
i
*
2
+
1
]
=
new_bias_ptr
[
i
];
}
param
->
SetNewScale
(
new_scale
);
param
->
SetNewBias
(
new_bias
);
fpga
::
ConvArgs
convArgs
;
convArgs
.
relu_enabled
=
relu_enabled
;
convArgs
.
filter_address
=
(
void
*
)
filter_ptr
;
convArgs
.
filter_address
=
(
void
*
)
filter_ptr
;
convArgs
.
filter_num
=
filter
->
dims
()[
0
];
convArgs
.
group_num
=
param
->
Groups
();
convArgs
.
sb_address
=
(
void
*
)
bs_ptr
;
convArgs
.
sb_address
=
(
void
*
)
bs_ptr
;
convArgs
.
kernel
.
stride_h
=
param
->
Strides
()[
0
];
convArgs
.
kernel
.
stride_w
=
param
->
Strides
()[
1
];
convArgs
.
kernel
.
height
=
filter
->
dims
()[
2
];
convArgs
.
kernel
.
width
=
filter
->
dims
()[
3
];
convArgs
.
image
.
address
=
(
void
*
)
input_ptr
;
convArgs
.
image
.
address
=
(
void
*
)
input_ptr
;
convArgs
.
image
.
channels
=
input
->
dims
()[
1
];
convArgs
.
image
.
height
=
input
->
dims
()[
2
];
convArgs
.
image
.
width
=
input
->
dims
()[
3
];
convArgs
.
image
.
pad_height
=
param
->
Paddings
()[
0
];
convArgs
.
image
.
pad_width
=
param
->
Paddings
()[
1
];
convArgs
.
image
.
scale_address
=
input
->
fpga_args
().
scale_pointer
();
convArgs
.
output
.
address
=
(
void
*
)
out_ptr
;
convArgs
.
output
.
address
=
(
void
*
)
out_ptr
;
convArgs
.
output
.
scale_address
=
out
->
fpga_args
().
scale_pointer
();
param
->
SetFpgaArgs
(
convArgs
);
return
true
;
}
template
<
>
void
ConvAddBNReluKernel
<
FPGA
,
float
>::
Compute
(
const
FusionConvAddBNReluParam
&
param
)
const
{
void
ConvAddBNReluKernel
<
FPGA
,
float
>::
Compute
(
const
FusionConvAddBNReluParam
&
param
)
const
{
fpga
::
ComputeFpgaConv
(
param
.
FpgaArgs
());
}
template
class
ConvAddBNReluKernel
<
FPGA
,
float
>;
...
...
src/operators/kernel/fpga/conv_add_relu_kernel.cpp
浏览文件 @
50b074a6
...
...
@@ -32,25 +32,26 @@ bool ConvAddReluKernel<FPGA, float>::Init(FusionConvAddReluParam *param) {
Tensor
*
out
=
param
->
Output
();
auto
out_ptr
=
out
->
mutable_data
<
float
>
();
PADDLE_MOBILE_ENFORCE
(
input
->
dims
()[
1
]
==
bias
->
dims
()[
0
],
"Image channel should be equal to bias number"
);
PADDLE_MOBILE_ENFORCE
(
input
->
dims
()[
1
]
==
bias
->
dims
()[
0
],
"Image channel should be equal to bias number"
);
int
channel
=
input
->
dims
()[
1
];
float
*
bs_ptr
=
(
float
*
)
fpga
::
fpga_malloc
(
2
*
channel
*
sizeof
(
float
));
for
(
int
i
=
0
;
i
<
channel
;
i
++
)
{
bs_ptr
[
i
*
2
]
=
1
;
bs_ptr
[
i
*
2
+
1
]
=
bias_ptr
[
i
];
for
(
int
i
=
0
;
i
<
channel
;
i
++
)
{
bs_ptr
[
i
*
2
]
=
1
;
bs_ptr
[
i
*
2
+
1
]
=
bias_ptr
[
i
];
}
fpga
::
ConvArgs
convArgs
;
convArgs
.
relu_enabled
=
relu_enabled
;
convArgs
.
filter_address
=
(
void
*
)
filter_ptr
;
convArgs
.
filter_address
=
(
void
*
)
filter_ptr
;
convArgs
.
filter_num
=
filter
->
dims
()[
0
];
convArgs
.
group_num
=
param
->
Groups
();
convArgs
.
sb_address
=
(
void
*
)
bs_ptr
;
convArgs
.
sb_address
=
(
void
*
)
bs_ptr
;
convArgs
.
kernel
.
stride_h
=
param
->
Strides
()[
0
];
convArgs
.
kernel
.
stride_w
=
param
->
Strides
()[
1
];
convArgs
.
kernel
.
height
=
filter
->
dims
()[
2
];
convArgs
.
kernel
.
width
=
filter
->
dims
()[
3
];
convArgs
.
image
.
address
=
(
void
*
)
input_ptr
;
convArgs
.
image
.
address
=
(
void
*
)
input_ptr
;
convArgs
.
image
.
channels
=
input
->
dims
()[
1
];
convArgs
.
image
.
height
=
input
->
dims
()[
2
];
convArgs
.
image
.
width
=
input
->
dims
()[
3
];
...
...
@@ -58,14 +59,15 @@ bool ConvAddReluKernel<FPGA, float>::Init(FusionConvAddReluParam *param) {
convArgs
.
image
.
pad_height
=
param
->
Paddings
()[
0
];
convArgs
.
image
.
pad_width
=
param
->
Paddings
()[
1
];
convArgs
.
image
.
scale_address
=
input
->
fpga_args
().
scale_pointer
();
convArgs
.
output
.
address
=
(
void
*
)
out_ptr
;
convArgs
.
output
.
address
=
(
void
*
)
out_ptr
;
convArgs
.
output
.
scale_address
=
out
->
fpga_args
().
scale_pointer
();
param
->
SetFpgaArgs
(
convArgs
);
return
true
;
}
template
<
>
void
ConvAddReluKernel
<
FPGA
,
float
>::
Compute
(
const
FusionConvAddReluParam
&
param
)
const
{
void
ConvAddReluKernel
<
FPGA
,
float
>::
Compute
(
const
FusionConvAddReluParam
&
param
)
const
{
fpga
::
ComputeFpgaConv
(
param
.
FpgaArgs
());
}
template
class
ConvAddReluKernel
<
FPGA
,
float
>;
...
...
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