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提交 28c87a4e 编写于 作者: Z zhaojiaying01
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src/operators/math/gemm.cpp
浏览文件 @ 28c87a4e
...@@ -1546,283 +1546,281 @@ void WriteWithBnRelu(int mc, int nc, float *c, float *C, int ldc, float *scale, ...@@ -1546,283 +1546,281 @@ void WriteWithBnRelu(int mc, int nc, float *c, float *C, int ldc, float *scale,
"q8", "q10", "q11", "q12", "q13", "q14"); "q8", "q10", "q11", "q12", "q13", "q14");
} }
/* /*
// C = A * B // C = A * B
void VecWriteBasic(int n, float *c, float *C, int ldc) { void VecWriteBasic(int n, float *c, float *C, int ldc) {
int nc1 = n / 16; int nc1 = n / 16;
int _nc1 = n % 16; int _nc1 = n % 16;
int nc2 = _nc1 / 4; int nc2 = _nc1 / 4;
int nc3 = 16 - 4 * (_nc1 % 4); int nc3 = 16 - 4 * (_nc1 % 4);
asm volatile( asm volatile(
"subs %[nc1], %[nc1], #1 \n\t" "subs %[nc1], %[nc1], #1 \n\t"
"blt end_nc1_%= \n\t" "blt end_nc1_%= \n\t"
"loop_nc1_%=: \n\t" "loop_nc1_%=: \n\t"
"vld1.32 {q0, q1}, [%[c]]! \n\t" "vld1.32 {q0, q1}, [%[c]]! \n\t"
"vst1.32 {q0, q1}, [%[C]]! \n\t" "vst1.32 {q0, q1}, [%[C]]! \n\t"
"vld1.32 {q2, q3}, [%[c]]! \n\t" "vld1.32 {q2, q3}, [%[c]]! \n\t"
"vst1.32 {q2, q3}, [%[C]]! \n\t" "vst1.32 {q2, q3}, [%[C]]! \n\t"
"subs %[nc1], %[nc1], #1 \n\t" "subs %[nc1], %[nc1], #1 \n\t"
"bge loop_nc1_%= \n\t" "bge loop_nc1_%= \n\t"
"end_nc1_%=: \n\t" "end_nc1_%=: \n\t"
"subs %[nc2], %[nc2], #1 \n\t" "subs %[nc2], %[nc2], #1 \n\t"
"blt end_nc2_%= \n\t" "blt end_nc2_%= \n\t"
"loop_nc2_%=: \n\t" "loop_nc2_%=: \n\t"
"vld1.32 {q4}, [%[c]]! \n\t" "vld1.32 {q4}, [%[c]]! \n\t"
"vst1.32 {q4}, [%[C]]! \n\t" "vst1.32 {q4}, [%[C]]! \n\t"
"subs %[nc2], %[nc2], #1 \n\t" "subs %[nc2], %[nc2], #1 \n\t"
"bge loop_nc2_%= \n\t" "bge loop_nc2_%= \n\t"
"end_nc2_%=: \n\t" "end_nc2_%=: \n\t"
"cmp %[nc3], #16 \n\t" "cmp %[nc3], #16 \n\t"
"beq end_nc3_%= \n\t" "beq end_nc3_%= \n\t"
"sub %[c], %[c], %[nc3] \n\t" "sub %[c], %[c], %[nc3] \n\t"
"sub %[C], %[C], %[nc3] \n\t" "sub %[C], %[C], %[nc3] \n\t"
"vld1.32 {q5}, [%[c]]! \n\t" "vld1.32 {q5}, [%[c]]! \n\t"
"vst1.32 {q5}, [%[C]]! \n\t" "vst1.32 {q5}, [%[C]]! \n\t"
"end_nc3_%=: \n\t" "end_nc3_%=: \n\t"
: :
: [C] "r"(C), [c] "r"(c), [nc1] "r"(nc1), [nc2] "r"(nc2), [nc3] "r"(nc3) : [C] "r"(C), [c] "r"(c), [nc1] "r"(nc1), [nc2] "r"(nc2), [nc3] "r"(nc3)
: "memory", "q0", "q1", "q2", "q3", "q4", "q5"); : "memory", "q0", "q1", "q2", "q3", "q4", "q5");
} }
// C = alpha * A * B + beta * C // C = alpha * A * B + beta * C
void VecWriteWithAlphaBeta(int n, float *c, float *C, int ldc) {} void VecWriteWithAlphaBeta(int n, float *c, float *C, int ldc) {}
// C = A * B + C // C = A * B + C
void VecWriteWithAdd(int n, float *c, float *C, int ldc) { void VecWriteWithAdd(int n, float *c, float *C, int ldc) {
int nc1 = n / 16; int nc1 = n / 16;
int _nc1 = n % 16; int _nc1 = n % 16;
asm volatile( asm volatile(
"subs %[nc1], %[nc1], #1 \n\t" "subs %[nc1], %[nc1], #1 \n\t"
"blt end_nc1_%= \n\t" "blt end_nc1_%= \n\t"
"loop_nc1_%=: \n\t" "loop_nc1_%=: \n\t"
"vld1.32 {q0, q1}, [%[c]]! \n\t" "vld1.32 {q0, q1}, [%[c]]! \n\t"
"vld1.32 {q2, q3}, [%[C]] \n\t" "vld1.32 {q2, q3}, [%[C]] \n\t"
"vadd.f32 q10, q0, q2 \n\t" "vadd.f32 q10, q0, q2 \n\t"
"vadd.f32 q11, q1, q3 \n\t" "vadd.f32 q11, q1, q3 \n\t"
"vst1.32 {q10, q11}, [%[C]]! \n\t" "vst1.32 {q10, q11}, [%[C]]! \n\t"
"vld1.32 {q4, q5}, [%[c]]! \n\t" "vld1.32 {q4, q5}, [%[c]]! \n\t"
"vld1.32 {q6, q7}, [%[C]] \n\t" "vld1.32 {q6, q7}, [%[C]] \n\t"
"vadd.f32 q12, q4, q6 \n\t" "vadd.f32 q12, q4, q6 \n\t"
"vadd.f32 q13, q5, q7 \n\t" "vadd.f32 q13, q5, q7 \n\t"
"vst1.32 {q12, q13}, [%[C]]! \n\t" "vst1.32 {q12, q13}, [%[C]]! \n\t"
"subs %[nc1], %[nc1], #1 \n\t" "subs %[nc1], %[nc1], #1 \n\t"
"bge loop_nc1_%= \n\t" "bge loop_nc1_%= \n\t"
"end_nc1_%=: \n\t" "end_nc1_%=: \n\t"
: [C] "+r"(C), [c] "+r"(c) : [C] "+r"(C), [c] "+r"(c)
: [nc1] "r"(nc1) : [nc1] "r"(nc1)
: "memory", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q10", "q11", : "memory", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q10",
"q12", "q13"); "q11", "q12", "q13");
if (_nc1 != 0) { if (_nc1 != 0) {
for (int j = 0; j < _nc1; j++) { for (int j = 0; j < _nc1; j++) {
*C++ += *c++; *C++ += *c++;
}
} }
} }
}
// C = A * B + C, relu(C) // C = A * B + C, relu(C)
void VecWriteWithAddRelu(int n, float *c, float *C, int ldc) { void VecWriteWithAddRelu(int n, float *c, float *C, int ldc) {
int nc1 = n / 16; int nc1 = n / 16;
int _nc1 = n % 16; int _nc1 = n % 16;
asm volatile( asm volatile(
"vmov.f32 q14, #0.0 \n\t" "vmov.f32 q14, #0.0 \n\t"
"subs %[nc1], %[nc1], #1 \n\t" "subs %[nc1], %[nc1], #1 \n\t"
"blt end_nc1_%= \n\t" "blt end_nc1_%= \n\t"
"loop_nc1_%=: \n\t" "loop_nc1_%=: \n\t"
"vld1.32 {q0, q1}, [%[c]]! \n\t" "vld1.32 {q0, q1}, [%[c]]! \n\t"
"vld1.32 {q2, q3}, [%[C]] \n\t" "vld1.32 {q2, q3}, [%[C]] \n\t"
"vadd.f32 q10, q0, q2 \n\t" "vadd.f32 q10, q0, q2 \n\t"
"vadd.f32 q11, q1, q3 \n\t" "vadd.f32 q11, q1, q3 \n\t"
"vmax.f32 q10, q10, q14 \n\t" "vmax.f32 q10, q10, q14 \n\t"
"vmax.f32 q11, q11, q14 \n\t" "vmax.f32 q11, q11, q14 \n\t"
"vst1.32 {q10, q11}, [%[C]]! \n\t" "vst1.32 {q10, q11}, [%[C]]! \n\t"
"vld1.32 {q4, q5}, [%[c]]! \n\t" "vld1.32 {q4, q5}, [%[c]]! \n\t"
"vld1.32 {q6, q7}, [%[C]] \n\t" "vld1.32 {q6, q7}, [%[C]] \n\t"
"vadd.f32 q12, q4, q6 \n\t" "vadd.f32 q12, q4, q6 \n\t"
"vadd.f32 q13, q5, q7 \n\t" "vadd.f32 q13, q5, q7 \n\t"
"vmax.f32 q12, q12, q14 \n\t" "vmax.f32 q12, q12, q14 \n\t"
"vmax.f32 q13, q13, q14 \n\t" "vmax.f32 q13, q13, q14 \n\t"
"vst1.32 {q12, q13}, [%[C]]! \n\t" "vst1.32 {q12, q13}, [%[C]]! \n\t"
"subs %[nc1], %[nc1], #1 \n\t" "subs %[nc1], %[nc1], #1 \n\t"
"bge loop_nc1_%= \n\t" "bge loop_nc1_%= \n\t"
"end_nc1_%=: \n\t" "end_nc1_%=: \n\t"
: [C] "+r"(C), [c] "+r"(c) : [C] "+r"(C), [c] "+r"(c)
: [nc1] "r"(nc1) : [nc1] "r"(nc1)
: "memory", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q10", "q11", : "memory", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q10",
"q12", "q13"); "q11", "q12", "q13");
if (_nc1 != 0) { if (_nc1 != 0) {
for (int j = 0; j < _nc1; j++) { for (int j = 0; j < _nc1; j++) {
*C += *c; *C += *c;
if (*C < 0) { if (*C < 0) {
*C = 0; *C = 0;
}
C++;
c++;
} }
C++;
c++;
} }
} }
}
// C = A * B, batchnorm(C)
void VecWriteWithBn(int n, float *c, float *C, int ldc, float *scale,
float *bias) {
int nc1 = n / 16;
int _nc1 = n % 16;
int nc2 = _nc1 / 4;
int nc3 = 16 - 4 * (_nc1 % 4);
asm volatile(
"subs %[nc1], %[nc1], #1 \n\t"
"blt end_nc1_%= \n\t"
"loop_nc1_%=: \n\t"
"vld1.32 {q0, q1}, [%[c]]! \n\t"
"vld1.32 {q2, q3}, [%[scale]]! \n\t"
"vld1.32 {q10, q11}, [%[bias]]! \n\t"
"vmla.f32 q10, q0, q2 \n\t"
"vmla.f32 q11, q1, q3 \n\t"
"vst1.32 {q10, q11}, [%[C]]! \n\t"
"vld1.32 {q4, q5}, [%[c]]! \n\t"
"vld1.32 {q6, q7}, [%[scale]]! \n\t"
"vld1.32 {q12, q13}, [%[bias]]! \n\t"
"vmla.f32 q12, q4, q6 \n\t"
"vmla.f32 q13, q5, q7 \n\t"
"vst1.32 {q12, q13}, [%[C]]! \n\t"
"subs %[nc1], %[nc1], #1 \n\t"
"bge loop_nc1_%= \n\t"
"end_nc1_%=: \n\t"
"subs %[nc2], %[nc2], #1 \n\t" // C = A * B, batchnorm(C)
"blt end_nc2_%= \n\t" void VecWriteWithBn(int n, float *c, float *C, int ldc, float *scale,
"loop_nc2_%=: \n\t" float *bias) {
int nc1 = n / 16;
"vld1.32 {q0}, [%[c]]! \n\t" int _nc1 = n % 16;
"vld1.32 {q1}, [%[scale]]! \n\t" int nc2 = _nc1 / 4;
"vld1.32 {q10}, [%[bias]]! \n\t" int nc3 = 16 - 4 * (_nc1 % 4);
"vmla.f32 q10, q0, q1 \n\t"
"vst1.32 {q10}, [%[C]]! \n\t"
"subs %[nc2], %[nc2], #1 \n\t"
"bge loop_nc2_%= \n\t"
"end_nc2_%=: \n\t"
"cmp %[nc3], #16 \n\t" asm volatile(
"beq end_nc3_%= \n\t" "subs %[nc1], %[nc1], #1 \n\t"
"blt end_nc1_%= \n\t"
"loop_nc1_%=: \n\t"
"sub %[c], %[c], %[nc3] \n\t" "vld1.32 {q0, q1}, [%[c]]! \n\t"
"sub %[scale], %[scale], %[nc3] \n\t" "vld1.32 {q2, q3}, [%[scale]]! \n\t"
"sub %[bias], %[bias], %[nc3] \n\t" "vld1.32 {q10, q11}, [%[bias]]! \n\t"
"sub %[C], %[C], %[nc3] \n\t" "vmla.f32 q10, q0, q2 \n\t"
"vmla.f32 q11, q1, q3 \n\t"
"vst1.32 {q10, q11}, [%[C]]! \n\t"
"vld1.32 {q4, q5}, [%[c]]! \n\t"
"vld1.32 {q6, q7}, [%[scale]]! \n\t"
"vld1.32 {q12, q13}, [%[bias]]! \n\t"
"vmla.f32 q12, q4, q6 \n\t"
"vmla.f32 q13, q5, q7 \n\t"
"vst1.32 {q12, q13}, [%[C]]! \n\t"
"subs %[nc1], %[nc1], #1 \n\t"
"bge loop_nc1_%= \n\t"
"end_nc1_%=: \n\t"
"vld1.32 {q0}, [%[c]]! \n\t" "subs %[nc2], %[nc2], #1 \n\t"
"vld1.32 {q1}, [%[scale]]! \n\t" "blt end_nc2_%= \n\t"
"vld1.32 {q10}, [%[bias]]! \n\t" "loop_nc2_%=: \n\t"
"vmla.f32 q10, q0, q1 \n\t"
"vst1.32 {q10}, [%[C]]! \n\t"
"end_nc3_%=: \n\t"
: "vld1.32 {q0}, [%[c]]! \n\t"
: [C] "r"(C), [c] "r"(c), [nc1] "r"(nc1), [nc2] "r"(nc2), [nc3] "r"(nc3), "vld1.32 {q1}, [%[scale]]! \n\t"
[scale] "r"(scale), [bias] "r"(bias) "vld1.32 {q10}, [%[bias]]! \n\t"
: "memory", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q10", "q11", "vmla.f32 q10, q0, q1 \n\t"
"q12", "q13"); "vst1.32 {q10}, [%[C]]! \n\t"
}
// C = A * B, batchnorm(C), relu(C) "subs %[nc2], %[nc2], #1 \n\t"
void VecWriteWithBnRelu(int n, float *c, float *C, int ldc, float *scale, "bge loop_nc2_%= \n\t"
float *bias) { "end_nc2_%=: \n\t"
int nc1 = n / 16;
int _nc1 = n % 16;
int nc2 = _nc1 / 4;
int nc3 = 16 - 4 * (_nc1 % 4);
asm volatile( "cmp %[nc3], #16 \n\t"
"vmov.f32 q14, #0.0 \n\t" "beq end_nc3_%= \n\t"
"subs %[nc1], %[nc1], #1 \n\t"
"blt end_nc1_%= \n\t"
"loop_nc1_%=: \n\t"
"vld1.32 {q0, q1}, [%[c]]! \n\t" "sub %[c], %[c], %[nc3] \n\t"
"vld1.32 {q2, q3}, [%[scale]]! \n\t" "sub %[scale], %[scale], %[nc3] \n\t"
"vld1.32 {q10, q11}, [%[bias]]! \n\t" "sub %[bias], %[bias], %[nc3] \n\t"
"vmla.f32 q10, q0, q2 \n\t" "sub %[C], %[C], %[nc3] \n\t"
"vmla.f32 q11, q1, q3 \n\t"
"vmax.f32 q10, q10, q14 \n\t"
"vmax.f32 q11, q11, q14 \n\t"
"vst1.32 {q10, q11}, [%[C]]! \n\t"
"vld1.32 {q4, q5}, [%[c]]! \n\t" "vld1.32 {q0}, [%[c]]! \n\t"
"vld1.32 {q6, q7}, [%[scale]]! \n\t" "vld1.32 {q1}, [%[scale]]! \n\t"
"vld1.32 {q12, q13}, [%[bias]]! \n\t" "vld1.32 {q10}, [%[bias]]! \n\t"
"vmla.f32 q12, q4, q6 \n\t" "vmla.f32 q10, q0, q1 \n\t"
"vmla.f32 q13, q5, q7 \n\t" "vst1.32 {q10}, [%[C]]! \n\t"
"vmax.f32 q12, q12, q14 \n\t" "end_nc3_%=: \n\t"
"vmax.f32 q13, q13, q14 \n\t"
"vst1.32 {q12, q13}, [%[C]]! \n\t"
"subs %[nc1], %[nc1], #1 \n\t" :
"bge loop_nc1_%= \n\t" : [C] "r"(C), [c] "r"(c), [nc1] "r"(nc1), [nc2] "r"(nc2), [nc3]
"end_nc1_%=: \n\t" "r"(nc3), [scale] "r"(scale), [bias] "r"(bias) : "memory", "q0", "q1", "q2",
"q3", "q4", "q5", "q6", "q7", "q10", "q11", "q12", "q13");
}
"subs %[nc2], %[nc2], #1 \n\t" // C = A * B, batchnorm(C), relu(C)
"blt end_nc2_%= \n\t" void VecWriteWithBnRelu(int n, float *c, float *C, int ldc, float *scale,
"loop_nc2_%=: \n\t" float *bias) {
int nc1 = n / 16;
int _nc1 = n % 16;
int nc2 = _nc1 / 4;
int nc3 = 16 - 4 * (_nc1 % 4);
"vld1.32 {q0}, [%[c]]! \n\t" asm volatile(
"vld1.32 {q1}, [%[scale]]! \n\t" "vmov.f32 q14, #0.0 \n\t"
"vld1.32 {q10}, [%[bias]]! \n\t" "subs %[nc1], %[nc1], #1 \n\t"
"vmla.f32 q10, q0, q1 \n\t" "blt end_nc1_%= \n\t"
"vmax.f32 q10, q10, q14 \n\t" "loop_nc1_%=: \n\t"
"vst1.32 {q10}, [%[C]]! \n\t"
"subs %[nc2], %[nc2], #1 \n\t" "vld1.32 {q0, q1}, [%[c]]! \n\t"
"bge loop_nc2_%= \n\t" "vld1.32 {q2, q3}, [%[scale]]! \n\t"
"end_nc2_%=: \n\t" "vld1.32 {q10, q11}, [%[bias]]! \n\t"
"vmla.f32 q10, q0, q2 \n\t"
"vmla.f32 q11, q1, q3 \n\t"
"vmax.f32 q10, q10, q14 \n\t"
"vmax.f32 q11, q11, q14 \n\t"
"vst1.32 {q10, q11}, [%[C]]! \n\t"
"cmp %[nc3], #16 \n\t" "vld1.32 {q4, q5}, [%[c]]! \n\t"
"beq end_nc3_%= \n\t" "vld1.32 {q6, q7}, [%[scale]]! \n\t"
"vld1.32 {q12, q13}, [%[bias]]! \n\t"
"vmla.f32 q12, q4, q6 \n\t"
"vmla.f32 q13, q5, q7 \n\t"
"vmax.f32 q12, q12, q14 \n\t"
"vmax.f32 q13, q13, q14 \n\t"
"vst1.32 {q12, q13}, [%[C]]! \n\t"
"sub %[c], %[c], %[nc3] \n\t" "subs %[nc1], %[nc1], #1 \n\t"
"sub %[scale], %[scale], %[nc3] \n\t" "bge loop_nc1_%= \n\t"
"sub %[bias], %[bias], %[nc3] \n\t" "end_nc1_%=: \n\t"
"sub %[C], %[C], %[nc3] \n\t"
"vld1.32 {q0}, [%[c]]! \n\t" "subs %[nc2], %[nc2], #1 \n\t"
"vld1.32 {q1}, [%[scale]]! \n\t" "blt end_nc2_%= \n\t"
"vld1.32 {q10}, [%[bias]]! \n\t" "loop_nc2_%=: \n\t"
"vmla.f32 q10, q0, q1 \n\t"
"vmax.f32 q10, q10, q14 \n\t" "vld1.32 {q0}, [%[c]]! \n\t"
"vst1.32 {q10}, [%[C]]! \n\t" "vld1.32 {q1}, [%[scale]]! \n\t"
"end_nc3_%=: \n\t" "vld1.32 {q10}, [%[bias]]! \n\t"
"vmla.f32 q10, q0, q1 \n\t"
"vmax.f32 q10, q10, q14 \n\t"
"vst1.32 {q10}, [%[C]]! \n\t"
"subs %[nc2], %[nc2], #1 \n\t"
"bge loop_nc2_%= \n\t"
"end_nc2_%=: \n\t"
"cmp %[nc3], #16 \n\t"
"beq end_nc3_%= \n\t"
"sub %[c], %[c], %[nc3] \n\t"
"sub %[scale], %[scale], %[nc3] \n\t"
"sub %[bias], %[bias], %[nc3] \n\t"
"sub %[C], %[C], %[nc3] \n\t"
"vld1.32 {q0}, [%[c]]! \n\t"
"vld1.32 {q1}, [%[scale]]! \n\t"
"vld1.32 {q10}, [%[bias]]! \n\t"
"vmla.f32 q10, q0, q1 \n\t"
"vmax.f32 q10, q10, q14 \n\t"
"vst1.32 {q10}, [%[C]]! \n\t"
"end_nc3_%=: \n\t"
: :
: [C] "r"(C), [c] "r"(c), [nc1] "r"(nc1), [nc2] "r"(nc2), [nc3] "r"(nc3), : [C] "r"(C), [c] "r"(c), [nc1] "r"(nc1), [nc2] "r"(nc2), [nc3]
[scale] "r"(scale), [bias] "r"(bias) "r"(nc3), [scale] "r"(scale), [bias] "r"(bias) : "memory", "q0", "q1", "q2",
: "memory", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q10", "q11", "q3", "q4", "q5", "q6", "q7", "q10", "q11", "q12", "q13", "q14");
"q12", "q13", "q14"); }
} */
*/
#endif // __aarch64__ #endif // __aarch64__
#else #else
......
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