Add drivers/net/ti/ folder and move all TI's code in this folder for better
maintenance.
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>

The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with
the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and
can set the blinking pattern of each of its 4 LEDs, supports SyncE as
well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8574 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.
Signed-off-by: NQuentin Schulz <quentin.schulz@bootlin.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Part of the config is common between the VSC8584 and the VSC8574, so to
prepare for the upcoming support of VSC8574, use the phy_device.priv
pointer that will keep the function that holds code that is PHY-specific
and that should be called during config function.
Signed-off-by: NQuentin Schulz <quentin.schulz@bootlin.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The VSC8584 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with the
MAC via SGMII, QSGMII or 1000BASE-X, supports downshifting and can set
the blinking pattern of each of its 4 LEDs, supports hardware offloading
of MACsec and supports SyncE as well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8584 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.

The revA of the VSC8584 PHY (which is not and will not be publicly
released) should NOT patch the firmware of the microcontroller or it'll
make things worse, the easiest way is just to not support it.
Signed-off-by: NQuentin Schulz <quentin.schulz@bootlin.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The algorithm in the ast2500_calc_clock_config() routine suffers from
integer rounding and the requested rate does not get the appropriate
set of Numerator, Denumerator, Post Divider parameters.

This is the case for the D2-PLL clock used by the MAC controllers in
RGMII mode. The requested rated is 250MHz but a 251MHz is assigned.

The easiest way to fix this problem is to introduce an array of clock
settings defining the N, M, P parameters for well known frequencies
used by the Aspeed SoC.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This is a large update of the AST2500 SoC DTS file bringing it to the
level of commit 927c2fc2db19 :

    Author:  Joel Stanley <joel@jms.id.au>
    Date:    Sat Jun 2 01:18:53 2018 -0700

         ARM: dts: aspeed: Fix hwrng register address

There are some differences on the compatibility property names. scu,
reset and clock drivers are also different.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Use simple arrays under the device priv structure to hold the RX and
TX descriptors and handle memory coherency by invalidating or flushing
the d-cache when required.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Implement the MDIO bus read/write functions using the readl_poll_timeout()
routine, initialize the bus and scan for the PHY. RGMII and RMII mode
are supported.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The driver is based on the previous one and the code is only adapted
to fit the driver model. The support for the Faraday ftgmac100
controller is the same with MAC and MDIO bus support for RGMII/RMII
modes.

Configuration is updated to enable compile again. At this stage, the
driver compiles but is not yet functional.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs
(e.g. MT7628 and MT7688), including a minimum setup of the integrated
switch. This driver is loosly based on the driver version included in
this MediaTek github repository:

https://github.com/MediaTek-Labs/linkit-smart-uboot.git

Tested on the MT7688 LinkIt smart-gateway and on the
Gardena-smart-gateway.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Frank Wunderlich <frankwu@gmx.de>
Cc: Weijie Gao <hackpascal@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

- replace the dynamic size of the relocation table
  with a fixed but configurable size
- fixes non-working CONFIG_OF_SEPARATE=y due to invalid _end symbol

Currently the size of the relocation table will be shrunk
to the actual size needed. Although this gives a maximal
space saving, it messes up the _end symbol. This breaks
features like appended DTBs because the _end symbol doesn't
point to the real end of the U-Boot binary.

Remove the size shrinking and make the size of the relocation
table fixed but configurable. This follows the Linux approach
and the user can adjust the size to his needs.

Also rename the relocation table section from .rel to .data.reloc
to follow the Linux approach and to avoid ambiguities with the
.rel.* sections added by the linker.
Reported-by: NLars Povlsen <lars.povlsen@microsemi.com>
Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

It is perfectly fine to write th DTCNTL TAP count and enable the
SCC sampling clock operation in the same write.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

When the bus switches to 1.8V mode of operation, it is necessary to
verify that the card correctly initiated and completed the voltage
switch. This is done by reading out the state of DATA0 line.

This patch implement support for reading out the state of the DATA0
line, so the MMC core code can correctly switch to 1.8V mode.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

Make sure to clear HS400 configuration when resetting the SCC block.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

Add check to avoid touching the SCC tuning registers in case the IP
doesn't support them or if the support isn't in place yet.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

Preinitialize the SD card signals regulator to 3.3V, which is the
default post-reset setting, to be sure the regulator is set to a
valid value.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

Configure the clock settings before reconfiguring any other IO settings.
This is required when the clock must be stopped before changing eg. the
pin configuration or any of the other properties of the bus. Running the
clock configuration first allows the MMC core to do just that.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

In case the controller performs card tuning, that is, sends MMC
command 19 or 21, silence possible CRC error warning prints. The
warnings are bound to happen, since the tuning will fail for some
settings while searching for the optimal configuration of the bus
and that is perfectly OK.

This patch passes around the MMC command structure and adds check
into tmio_sd_check_error() to avoid printing CRC error warning
when the tuning happens.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

Properly handle return values and abort operations when they are
non-zero. This is a minor improvement, which fixes two remaining
unchecked return values.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

The SD UHS SDR12, SDR25, SDR50, SDR104, DDR50 and MMC HS200, HS400
modes all use 1.8V signaling, while all the legacy modes use 3.3V
signaling. While there are extra modes which use 1.2V signaling,
the existing hardware does not support those.

Simplify the pinmux such that 3.3V signaling implies legacy mode
pinmux and the rest implies UHS mode pinmux. This prevents the
massive case statement from growing further. Moreover, it fixes
an edge case where during SD 1.8V switch, the bus mode is still
set to default while the signaling is already set to 1.8V, which
results in an attempt to communicate with a 1.8V card using pins
in 3.3V mode and thus communication failure.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire
64bit DRAM space as cachable. On CortexA57, this might result in odd
side effects, where the CPU tries to prefetch from those areas and if
there is no DRAM backing them, CPU bus hang can happen.

This patch fixes it by generating the mem_map structure based on the
actual memory layout obtained from the DT, thus not marking areas
without any DRAM behind them as cachable.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Fixes: c1ec3476 ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3")
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add definition of the POCCTRL register and bits therein to R8A77990 E3
pincontrol driver. This allows the pincontrol driver to configure SDHI
pin voltage according to power-source DT property.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Use fixed 4bit size for generating the DRV register element mask,
not the size of the value, which can be smaller.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Just 2 non-functinal changes:

 1. Rename of EMDK to EMSDP so it matches real marketing name
 2. Add essential README for IoTDK

Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Real marketing name of the board was recently updated so
to accommodate that change renaming the board and all
related to it.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

This part should've been remove in commit 88d60db0 ("arm: ti: boot:
Remove environment partition"), but I missed it somehow. Remove reading
dtb file from environment partition on eMMC, as we don't have it
anymore.
Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org>

Fixes possible resource leak in dm_test_tee() reported by Coverity.

Reported-by: Coverity (CID: 184175)
Signed-off-by: NJens Wiklander <jens.wiklander@linaro.org>

This line is no more needed and can be removed.

Only CONFIG_CMD_SOURCE is defined in Kconfig and
used in defconfig files.

CONFIG_SOURCE if not defined in source code and
"config SOURCE" is not present in any Kconfig.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

The Makefile already tests for SPL_DM_REGULATOR_GPIO, but Kconfig
does not provide it. This adds SPL_DM_REGULATOR_GPIO to Kconfig.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>