- 17 5月, 2021 4 次提交
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https://source.denx.de/u-boot/custodians/u-boot-marvell由 Tom Rini 提交于
- Add base support for Marvell OcteonTX2 CN9130 DB (mostly done by Kostya) - Sync Armada 8k MMU setup with Marvell version (misc Marvell authors) - spi: kirkwood: Some fixes especially for baudrate generation (misc Marvell authors) - mvebu: x530: Reduce SPL image size (Stefan) - Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)
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由 Kunihiko Hayashi 提交于
Even if only USB gadget is defined, dwc3 generic driver enables a definition and probe/remove functions for host driver. This enables the definition if USB_HOST is enabled only. Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
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由 Andre Przywara 提交于
All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register in their MUSB implementation, so they need a quirk to hardcode this. Currently this quirk depends on listing the SoCs affected in musb_reg.h, which means that this list needs to grow with every new chip. Move the quirk feature into Kconfig, next to PIO_ONLY, and change the default to y (for Allwinner builds), while listing the early implementations as exceptions. This fixes USB peripheral operation on some newer SoCs, which were not explicitly listed before. Tested on H6, H616, R40 (which were broken before), and also on the H5 and A20, for regressions. Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
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- 16 5月, 2021 12 次提交
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由 Konstantin Porotchkin 提交于
This patch adds the base support for the Marvell Octeon TX2 CN913x DB. Only one defconfig is added with this patch. Other board variants are available (NAND, MMC booting) and images for these boards can be generated by following the documentation added in the included README. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN913x DB. This is only the base port with not all interfaces supported fully. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Rename the misleading cmd "rx_training" to "mvebu_comphy_rx_training" to avoid confusion and mixup with DDR3/4 training. This makes it clear, that this command is platform specific and handles the COMPHY RX training. Also depend this cmd on ARMADA_8K and not TARGET_MVEBU_ARMADA_8K to make is available for OcteonTX2 CN913x. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Pali Rohár <pali@kernel.org> Cc: Marek Behun <marek.behun@nic.cz> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NMarek Behún <marek.behun@nic.cz> Acked-by: NPali Rohár <pali@kernel.org>
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由 Marcin Wojtas 提交于
The pcie_dw_mvebu configure ATU regions for memory, configuration and IO space types. However the latter is not obligatory and when not specified in the device tree, causes wrong ATU configuration. Fix that by adding a dependency on the detected PCIE regions count. Signed-off-by: NMarcin Wojtas <mw@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/18136Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Tested-by: NKostya Porotchkin <kostap@marvell.com>
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由 Grzegorz Jaszczyk 提交于
Some of the setups including cn9130 opens mmio window starting from 0xc0000000, reflect it in the u-boot code. Signed-off-by: NGrzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Grzegorz Jaszczyk 提交于
Signed-off-by: NGrzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Grzegorz Jaszczyk 提交于
There is region left by ATF, which needs to remain in memory to provide RT services. To prevent overwriting it by u-boot, do not provide any mapping for this memory region, so any attempt to access it will trigger synchronous exception. Update sr 2021-04-12: Don't update armada3700/cpu.c mmu table, as this has specific changes included in mainline. Signed-off-by: NGrzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 jinghua 提交于
1. RAM: base address 0x0 size 2Gbytes 2. MMIO: base address 0xf0000000 size 1Gbytes Signed-off-by: NOfir Fedida <ofedida@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Grzegorz Jaszczyk 提交于
After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2 ("spi: kirkwood: prevent configuring speed exceeding max controller freq") the spi frequency could be set to 0 on platform where spi-max-frequency is not defined (e.g. on armada-388-gp). Prevent limiting speed in mentioned cases. Signed-off-by: NGrzegorz Jaszczyk <jaz@semihalf.com> Tested-by: NKostya Porotchkin <kostap@marvell.com> Reviewed-by: NMarcin Wojtas <marcin@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marcin Wojtas 提交于
This patch adds a limitation in the kirkwood_spi driver set_speed hook, which prevents setting too high transfer speed. Signed-off-by: NMarcin Wojtas <mw@semihalf.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Tested-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
The Armada SoC family implementation of this SPI hardware module has extended the configuration register to allow for a wider range of SPI clock rates. Specifically the Serial Baud Rate Pre-selection bits in the SPI Interface Configuration Register now also use bits 6 and 7 as well. Modify the baud rate calculation to handle these differences for the Armada case. Potentially a baud rate can be setup using a number of different pre-scalar and scalar combinations. This code tries all possible pre-scalar divisors (8 in total) to try and find the most accurate set. Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Currently, building U-Boot for x530 fails since the SPL image is too big. This patch reduces the SPL size by changing the following Kconfig options: Enable CONFIG_SPL_TINY_MEMSET Disable CONFIG_SPI_FLASH_BAR By disabling CONFIG_SPI_FLASH_BAR, the tiny SPI NOR framework can be used. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Pratyush Yadav <p.yadav@ti.com> Cc: Tom Rini <trini@konsulko.com> Tested-by: NChris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: NPratyush Yadav <p.yadav@ti.com>
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- 15 5月, 2021 4 次提交
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由 Tom Rini 提交于
Rsync all defconfig files using moveconfig.py Signed-off-by: NTom Rini <trini@konsulko.com>
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https://source.denx.de/u-boot/custodians/u-boot-amlogic由 Tom Rini 提交于
- dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro - usb: dwc3-meson-g12a: skip phy on -ENODATA aswell - net: dwmac_meson8b: do not set TX delay in TXID & RXID - net: designware: meson8b: add g12a compatible
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- 14 5月, 2021 20 次提交
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由 Neil Armstrong 提交于
Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
When the PHY interface is set as TXID & RXID, the delays should be taken from DT, but first they should not be hardcoded since the PHY driver will set them. Fixes: 798424e8 ("net: designware: add Amlogic Meson8b & later glue driver") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Neil Armstrong 提交于
If the PHY isn't specified in the DT, -ENODATA means it should be skipped, handle it like -ENOENT. With that, devices without USB3 supported can have USB working (Odroid-HC4). Fixes: adb049ab ("usb: dwc3: Add Meson G12A USB Glue") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
This lacks the right u-boot specific DT include to make HDMI work. Reported-by: NB1oHazard <ty3uk@mail.ua> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Bin Meng 提交于
This reverts commit bc8bbb77. This commit breaks U-Boot booting on SiFive Unleashed board, as there is no such CSR on U54 core. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NLeo Yu-Chi Liang <ycliang@andestech.com>
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由 Vincent Chen 提交于
The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work properly due to the wrong implementations. It will cause the u-boot PWM command to not work as expected. The bugs will be resolved in this patch. Signed-off-by: NVincent Chen <vincent.chen@sifive.com> Reviewed-by: NRick Chen <rick@andestech.com>
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由 Sean Anderson 提交于
It is no longer necessary to disallow ai ram, since it is enabled by the sram driver. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
Testing showed that disabling AI while leaving PLL1 enabled disabled the aisram. This suggests that AI is a more appropriate clock for that ram bank. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
This is more consistent with the naming of other ram banks, and matches what Linux is doing. Reported-by: NDamien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
We just need to initialize all the clocks pre-reloc. The clock driver creates a bunch of devices, so we need to increase the pre-reloc malloc arena. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
These devices are necessary for the clock driver, which is required by the sram driver, to run pre-relocation. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
Variables which had previously been stored in .bss are moved to .data. In addition, probed needs to be reset when the clock driver is re-bound post-relocation. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
No other (real) clocks have the cpu clock as their parent; instead they are children of aclk. Move the clint clock under aclk to match them. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
This simplifies the PLL creation process, since we don't have to pass all the parameters individually. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
This conditional always evaluated as false, regardless of the value of reg. Fix it so that it properly tests the bits in the PLL register. Also test PLL_EN, now that we set it. Reported-by: NDamien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NDamien Le Moal <damien.lemoal@wdc.com>
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由 Sean Anderson 提交于
If the user/dev explicitly requests a clock be assigned a certain rate, then we should warn them if we can't do it. This makes it clear if the clock is running at the default rate. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Rick Chen 提交于
Add Leo as co-maintainer for RISC-V. Signed-off-by: NRick Chen <rick@andestech.com>
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由 Tom Rini 提交于
- Improve support for various forms of extension boards and add DT overlay application support.
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由 Kory Maincent 提交于
Update the Kconfig and the board file to make the am335x board compatible with cape detection. Signed-off-by: NKory Maincent <kory.maincent@bootlin.com>
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