To be more EABI compliant and as a preparation for building
with clang, use the platform-specific r9 register for gd
instead of r8.

note: The FIQ is not updated since it is not used in u-boot,
and under discussion for the time being.

The following checkpatch warning is ignored:
WARNING: Use of volatile is usually wrong: see
Documentation/volatile-considered-harmful.txt
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

r9 is a platform-specific register in ARM EABI and not per
definition a general purpose register. Do not use it while
relocating so it can be used for gd.

cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>

Every ARM cpu config.mk (arch/arm/cpu/{CPUDIR}/config.mk) defines:

PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float

So, this patch moves the common compiler options to arch/arm/config.mk.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Reload address was written to the counter register
instead of load register.
The problem happens when timer expires but never
reload to ~0UL (it is downcount timer).
Reported-by: NStephen MacMahon <stephenm@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The movt/movw instruction can be used to hardcode an
memory location in the instruction itself. The linker
starts complaining about this if the compiler decides
to do so: "relocation R_ARM_MOVW_ABS_NC against `a local
symbol' can not be used" and it is not support by U-boot
as well. Prevent their use by requiring word relocations.
This allows u-boot to be build at other optimalization
levels then -Os.
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
Cc: TigerLiu@viatech.com.cn
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: NSimon Glass <sjg@chromium.org>

Since UBIFS is enabled for cpux9k2, more malloc space is needed.
For the current uboot 2013.10-rcX the size is to small, this will fix the
startup problems by increasing the malloc space to 4MiB.
Signed-off-by: NJens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Since commit 5dc5f36 removed B2 board support,
there are no boards enabling s3c44b0_rtc.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Andrea Scian <andrea.scian@dave-tech.it>

Since commit 5dc5f36 removed B2 board support,
there are no boards enabling serial_s3c44b0.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Andrea Scian <andrea.scian@dave-tech.it>

Since commit 5dc5f36 removed B2 board support,
there are no boards enabling s3c44b0_i2c.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Andrea Scian <andrea.scian@dave-tech.it>
Acked-by: NHeiko Schocher <hs@denx.de>

Because commit 5dc5f36 removed B2 board support,
arch/arm/cpu/s3c44b0/* and arch/arm/include/asm/arch-s3c44b0/*
are not necessary anymore.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Andrea Scian <andrea.scian@dave-tech.it>

Even though the MMU/D-cache is off, some DMA engines still
expect strict address alignment.

For example, the incoming Faraday FTMAC110 & FTGMAC100 ethernet
controllers expect the tx/rx descriptors should always be aligned
to 16-bytes boundary.
Signed-off-by: NKuo-Jung Su <dantesu@faraday-tech.com>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>

Because the stack pointer is already set in arch/arm/lib/crt0.S,
we do not need to set it in arch/arm/lib/spl.c.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

After further testing, this patch has two problems.  First,
examples/standalone/Makefile was already inherting PLATFORM_LIBS from
the top-level Makefile so this lead to duplicating the private libgcc.
Second, currently the private libgcc has a reference to 'hang' that is
not being fulfilled.

This reverts commit 4412db46.
Signed-off-by: NTom Rini <trini@ti.com>

Put all informations about targets, including state (active or
orphan) and maintainers, in boards.cfg; remove MAINTAINERS;
adjust the build system accordingly.
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>

Conflicts:
	tools/Makefile

This change allow to use sd card on Goni the same like mmc 0.
SD card is mmc dev 1, so it can be used like this: "fatls mmc 1:2".
SD card is inited even if eMMC initialization fails.
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

On s5pc1xx mmc devices offset is multiply of 0x100000,
wrong value was 0x10000. Register offset always points
to mmc 0 before this change.

Add macro definition of mmc dev register offset to s5pc1xx and
exynos mmc.
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung at samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

As per new convention ARCH_CPU_DTS is not defined in "dtc/Makefile".
Hence Arndale comilation is failing. Fix this by adding proper include
file in "board/samsung/dts/exynos5250-arndale.dts".
Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

The source clock frequency of I2C bus on p1022 is the platform(CCB)
clock, not CCB/2. The wrong source clock frequency leads to wrong
I2C bus speed setting. so, fixed it.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>

- Added section "u_boot_list" in arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
- Use the function i2c_init_all instead of i2c_init
Signed-off-by: NYing Zhang <b40530@freescale.com>

LCD4 needs a slightly different GPIO configuration than the
original LWMON5 variant. GPIO49 needs to be configured to a
default output value of 0 (permanent voltage supply).

Additionally lcd4 also needs to enable the LSB transmitter.
Signed-off-by: NStefan Roese <sr@denx.de>

For most boards which define CONFIG_SPL_PAD_TO,
it is defined in config header files.
Currently, there exists only one exception, cam_enc_4xx board.

This patch moves CONFIG_SPL_PAD_TO definition
from board/ait/cam_enc_4xx/config.mk
to include/configs/cam_enc_4xx.h.

With this modification, we can delete a glue code
in the top level config.mk:

ifneq ($(CONFIG_SPL_PAD_TO),)
CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO)
endif
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>

Currently no makefiles (board-specific config.mk)
set the following variables:

CONFIG_SPL_TEXT_BASE
CONFIG_UBOOT_PAD_TO
CONFIG_RESET_VECTOR_ADDRESS
CONFIG_TPL_PAD_TO

For all target boards using above macros
they are set in header files (include/configs/*.h),
so we do not need to set them as CPPFLAGS.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: NOliver Metz <oliver@freetz.org>
Tested-by: NLuka Perkov <luka@openwrt.org>

Signed-off-by: NOliver Metz <oliver@freetz.org>
Tested-by: NLuka Perkov <luka@openwrt.org>

Fix my email address.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>

Use of uImage formatted u-boot have long been preferred, and recent
changes to better support Falcon mode on MMC now enforces it on MMC.
Signed-off-by: NHenrik Nordstrom <henrik@henriknordstrom.net>

libata already has similar functions as implemented in the ahci code.
Refactor the code to use the libata variants and remove the dependency on
ata.h. Convert some defines to use the version from libata.h. Also, remove
some unnecessary memset's of bss data.

This is a step toward hopefully merging ahci.c and dw_ahsata.c which are
essentially the same driver.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Reviewed-by: NTom Rini <trini@ti.com>

Based on Linux libata code, most drives are less than 10 sec, but some
need up to 20 sec.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Reviewed-by: NTom Rini <trini@ti.com>

Some Intel SSDs can send a COMINIT after the initial COMRESET. This causes
the link to go down and we need to re-initialize the link.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Move the link bring-up handling to a separate weak function in order to
allow platforms to override it. This is needed on highbank platform which
needs special phy handling.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Replace hard-coded register values with proper defines for PORT_SCR_STAT
register.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

This fixes a memory leak when scsi inquiry fails.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Reviewed-by: NTom Rini <trini@ti.com>

gcc 4.7 will generate unaligned accesses to local char arrays, so make
them static to avoid that.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Reviewed-by: NTom Rini <trini@ti.com>

The AHCI driver was incorrectly using the Capabilities register NP (number
of ports) field to determine which ports to activate. This commit changes
it to correctly use the PORTS_IMPL register as a port map.
Signed-off-by: NRichard Gibbs <richard.gibbs@calxeda.com>
Reviewed-by: NTom Rini <trini@ti.com>