Console boot log:

U-Boot SPL 2021.04-00836-ga6232e06-dirty (Apr 16 2021 - 15:16:35 +0200)
Trying to boot from MMC1

U-Boot 2021.04-00836-ga6232e06-dirty (Apr 16 2021 - 15:16:35 +0200)

CPU:   Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 44C
Reset cause: POR
Model: Ronetix iMX7-CM Board
Board: iMX7-CM
DRAM:  512 MiB
PMIC:  PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet@30be0000 (eth0) using random MAC address - fe:be:37:01:5a:3f
eth0: ethernet@30be0000
Hit any key to stop autoboot:  0
Signed-off-by: NIlko Iliev <iliev@ronetix.at>

instead using ls and awk to determine file size use stat instead.
This fixes an invalid size reporting for user or group names that have
spaces in them.

This adds a dependency on the stat application which is part of
the coreutils package which also includes ls.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Add initial support for Compulab iot-gate-imx8 board (imx8mm-cl-iot-gate).
The initial support includes:
 - MMC
 - eMMC
 - I2C
 - FEC
 - Serial console
Signed-off-by: NKirill Kapranov <kirill.kapranov@compulab.co.il>
Signed-off-by: NUri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: NValentin Raevsky <valentin@compulab.co.il>
Signed-off-by: NYing-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Peter Robinson <pbrobinson@gmail.com>

Add board dts for imx8mm-cl-iot-gate
Signed-off-by: NKirill Kapranov <kirill.kapranov@compulab.co.il>
Signed-off-by: NUri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: NValentin Raevsky <valentin@compulab.co.il>
Signed-off-by: NYing-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Peter Robinson <pbrobinson@gmail.com>

Remove the invalid 'regulator-always-on' property to resolve:
starting USB...
Bus usb@2184000: Error enabling VBUS supply (ret=-13)
probe failed, error -13
Bus usb@2184200: USB EHCI 1.00
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

i.Core MX8M Mini needs to mount on top of this Carrier board for
creating complete i.Core MX8M Mini C.TOUCH 2.0 board.

Linux dts commit details:

commit <a142252061ff> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
C.TOUCH 2.0")

Add support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

i.Core MX8M Mini needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.

Linux dts commit details:

commit <051c08eea682> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
EDIMM2.2 Starter Kit")

Add support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini
from Engicam.

General features:
- NXP i.MX8M Mini
- Up to 2GB LDDR4
- 8/16GB eMMC
- Gigabit Ethernet
- USB 2.0 Host/OTG
- PCIe Gen2 interface
- I2S
- MIPI DSI to LVDS
- rest of i.MX8M Mini features

i.Core MX8M Mini needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Linux dts commit details:

commit <470d6dad5ddd> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
SoM")

Add support for it.
Signed-off-by: NMatteo Lisi <matteo.lisi@engicam.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

/soc@0
aips1
aips2
aips3
clk
iomuxc
osc_24m

are common node enablements across imx8mm platform for dm-spi,
dm-pre-reloc stages.

Move them into common dtsi, imx8mm-u-boot.dtsi

Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Add PHY's reset GPIO, so that U-Boot does a PHY hard reset.
This is needed, since the PHY might become unresponsive if
watchdog reboots the system while a transaction is ongoing.

The reset GPIO is added to the U-Boot specific DT files, since
the kernel does not setup the reserved registers correctly after
resetting the PHY and thus must not reset it.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.com>

In CP115, comphy4 can be configured into SFI port1
(in addition to SFI0). This patch adds the option
described above.

In addition, rename all existing SFI/XFI references:
COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0

No functional change for exsiting configuration.

Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0
Signed-off-by: NIgal Liberman <igall@marvell.com>
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>

According to Design Reference Specification the PHY PLL and Calibration
register from PHY0 are shared for multi-port PHY. PLL control registers
inside other PHY channels are not used.

This commit reworks utmi device tree nodes in a way that common PHY PLL
registers are moved to main utmi node. Accordingly both child nodes
utmi-unit range is reduced and register offsets in utmi_phy.h are updated
to this change.

This fixes issues in scenarios when only utmi port1 was in use, which
resulted with lack of correct pll initialization.

Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097
Signed-off-by: NGrzegorz Jaszczyk <jaz@semihalf.com>

Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of
1.5G/3G/6.25G were referenced in the driver non configuration (dts)
was using it.

This patch removes unused definitions.

Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488
Signed-off-by: NGrzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>

Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX.
Those definition might be confused with MDIO PHY definitions.

This patch does the following changes:
 - PHY_TYPE_XX --> COMPHY_TYPE_XX
 - PHY_SPEED_XX --> COMPHY_SPEED_XX

This improves readability, no functional change.

Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa
Signed-off-by: NIgal Liberman <igall@marvell.com>
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>

Because of the incorrectly supported SGMII_2500 mode, this patch
disables eth2 for now until this issue will be fixed in mainline.

Also fix an incorrect comment.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Marek Behun <marek.behun@nic.cz>

This patch adds the base support for the Marvell Octeon TX2 CN9130 CRB.
Not all interfaces are supported fully yet.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN9130 CRB. This is only the base port with not all
interfaces supported fully.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Add support for SoCs based on AP807 die.
Remove unused include file for Armada-8020 SoC.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Use a single dtsi file for CP110 die instead of master/slave.
Moving to single file will allow miltiple DTSI inclusions with
re-defined CP index and name.
This change will also allow support for SoCs containing more than
two CP110 dies on board.
Move pin control definitions from CP110 DTS to board DTS files
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

With this extended test, we get the following failure :

=> ut dm reset_base
Test: dm_test_reset_base: reset.c
test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2)
Test: dm_test_reset_base: reset.c (flat tree)
test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2)
Failures: 2

A fix is needed in reset_get_by_index_nodev() when introduced in [1].

[1] ea9dc35a ("reset: Get the RESET by index without device")
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

When zImage support was added to SPL, the messages were hidden to reduce
code size. However, the wrong config symbol was used. Since this file is
only built when CONFIG_SPL_FRAMEWORK=y, the messages were always hidden.

Use the correct symbol so the messages are printed in U-Boot proper.
Also use IS_ENABLED to drop the #ifdef.

Fixes: 431889d6 ("spl: zImage support in Falcon mode")
Signed-off-by: NSamuel Holland <samuel@sholland.org>

When flush_cache() is called during boot on our ~7M kernel image, the
hundreds of thousands of WATCHDOG_RESET calls end up adding
significantly to boottime. Flushing a single cache line doesn't take
many microseconds, so doing these calls for every cache line is
complete overkill.

The generic watchdog_reset() provided by wdt-uclass.c actually
contains some rate-limiting logic that should in theory mitigate this,
but alas, that rate-limiting must be disabled on powerpc because of
its get_timer() implementation - get_timer() works just fine until
interrupts are disabled, but it just so happens that the "big"
flush_cache() call happens in the part of bootm where interrupts are
indeed disabled. [1] [2] [3]

I have checked with objdump that the generated code doesn't change
when this option is left at its default value of 0: gcc is smart
enough to see that the ">=" comparison is tautologically true, hence
all assignments to "flushed" are eliminated as dead stores.

On our board, setting the option to something like 65536 ends up
reducing total boottime by about 0.8 seconds.

[1] https://patchwork.ozlabs.org/project/uboot/patch/20200605111657.28773-1-rasmus.villemoes@prevas.dk/
[2] https://lists.denx.de/pipermail/u-boot/2021-April/446906.html
[3] https://lists.denx.de/pipermail/u-boot/2021-April/447280.htmlReviewed-by: NStefan Roese <sr@denx.de>
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>

CONFIG_5xx hasn't existed since commit 50258977 (powerpc, 5xx:
remove support for 5xx). Remove this last mention of it.
Reviewed-by: NStefan Roese <sr@denx.de>
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>

Having WATCHDOG_RESET() called automatically from the timer interrupt
runs counter to the idea of a watchdog device - if the board runs into
an infinite loops with interrupts still enabled, the watchdog will
never fire.

When using CONFIG_(SPL_)WDT, the watchdog_reset function is a lot more
complicated than just poking a few SOC-specific registers - it
involves accessing all kinds of global data, and if the interrupt
happens at the wrong time (say, in the middle of an WATCHDOG_RESET()
call from ordinary code), that can end up corrupting said global data.

Allow the board to opt out of calling WATCHDOG_RESET() from the timer
interrupt handler by setting CONFIG_SYS_WATCHDOG_FREQ to 0 - as that
setting is currently nonsensical (it would be compile-time
divide-by-zero), it cannot affect any existing boards.

Add documentation for both the existing and extended meaning of
CONFIG_SYS_WATCHDOG_FREQ.
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>

Import updated devicetree files from the Linux v5.12 release.

Besides some node and audio port renames this changes the PHY modes to
either rgmii-id or rgmii-txid. From the board files the Pinephone sees
a lot of updates.

This also adds the long missing USB PHY property for controller 0, which
allows the U-Boot PHY driver to eventually use port 0 in host mode
(pending another U-Boot patch).
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net>

Update R40 .dts{,i} and dt-binding headers to current version from kernel.

Files taken from Linux 5.12-rc1 release
(commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8)
Signed-off-by: NIvan Uvarov <i.uvarov@cognitivepilot.com>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>

This patch adds support for the following I2C devices connected to
I2C bus 0 on the Octeon EBB7304:
- Dallas DS1337 RTC
- TLV EEPROM
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

We already have a clock driver for MIPS Octeon. This patch changes the
Octeon DT nodes to supply the clock property via the clock driver
instead of using an hard-coded value, which is not correct in all cases.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

This patch adds the basic support for the PCIe target board equipped
with the Octeon III CN2350 SoC.
Signed-off-by: NStefan Roese <sr@denx.de>

Add the AHCI compatible SATA DT node to the Octeon CN73xx dtsi file.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

For easy AHCI/ SATA integration, this patch adds board_ahci_enable()
for the MVEBU AHCI driver, which will be used by this platform. This
platform specific "enable" function will setup the proper endian
swapping in the AHCI controller so that it can be used by the common
AHCI code.

Additionally the endian swizzle entry for AHCI in
octeon_should_swizzle_table[] is removed, as this enabled the original
lowlevel code function, e.g. octeon_configure_qlm(), for the QLM setup
to work correctly.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

This patch adds the necessary platform infrastructure code, so that the
MIPS Octeon drivers "serial_octeon_pcie_console" & "serial_bootcmd" can
be used. This is e.g. the bootmem initialization in a compatible way to
the Marvell 2013 U-Boot, so that the exisiting PC remote tools like
"oct-remote-console" & "oct-remote-load" can be used. This is be done in
the newly introduced arch_misc_init(), which calls the necessary init
functions when enabled.

These patches are in preparation for the MIPS Octeon NIC23 board
support, which is a desktop PCIe target board enabling these features.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

As DEBUG is no Kconfig symbol, we can't use the IS_ENABLED() macros.
This patch switches to the unfortunately necessary #ifdef usage again
to make it work correctly.
Signed-off-by: NStefan Roese <sr@denx.de>

While porting from the Marvell source, I introduced a bug by misplacing
the parenthesis. This patch fixes this issue.
Signed-off-by: NStefan Roese <sr@denx.de>

This makes is easier to use this macro from non-DDR related files.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the PCIe controller node to the MIPS Octeon 73xx dtsi
file.
Signed-off-by: NStefan Roese <sr@denx.de>

Setting CONFIG_SYS_PCI_64BIT is needed for correct PCIe functionality on
MIPS Octeon.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the newly added C files to the Makefile to enable
compilation. This is done in a separate step, to not introduce build
breakage while adding the single files with potentially missing
externals.
Signed-off-by: NStefan Roese <sr@denx.de>

Import octeon_qlm.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Import octeon_fdt.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>