While IECTRL is disabled, input signals are pulled-down internally.
If pin-muxing is set up first, glitch signals (Low to High transition)
might be input to hardware blocks.

Bad case scenario:
[1] The hardware block is already running before pinctrl is handled.
   (the reset is de-asserted by default or by a firmware, for example)
[2] The pin-muxing is set up.  The input signals to hardware block
   are pulled-down by the chip-internal biasing.
[3] The pins are input-enabled.  The signals from the board reach the
    hardware block.

Actually, one invalid character is input to the UART blocks for such
SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the
power on reset.

To avoid such problems, pins should be input-enabled before muxing.

[ ported from Linux commit bac7f4c1bf5e7c6ccd5bb71edc015b26c77f7460 ]

Fixes: 5dc626f8 ("pinctrl: uniphier: add UniPhier pinctrl core support")
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The build fails if compiled with CONFIG_CMD_DDRMPHY_DUMP=y since commit
46abfcc9 ("ARM: uniphier: rework struct uniphier_board_data").

Fixes: 46abfcc9 ("ARM: uniphier: rework struct uniphier_board_data")
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

For the case where an external VBUS is used, we should enable the external
VBUS comparator in the driver. This would prevent an unnecessary overcurrent
error which would then disable the host port.

The overcurrent condition was happening on the SoCFPGA Cyclone5 devkit, thus
USB was not working on the devkit. This patch fixes that problem.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Fix the BOOTCFG value for eMMC in the same way as commit
  214c3f0f
  [imx: MX6DQ{P}/DL:SABRESD Fix bmode eMMC failure]
did for sabresd.
Signed-off-by: NSoeren Moch <smoch@web.de>

Move to booting a zImage kernel by default to align with the other
i.MX boards.

While at it, adjust the fdt_addr so that we can boot a standard
mainline kernel.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Use the new NXP emails.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Use Peng Fan's new NXP email address in MAINTAINERS files.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Acked-by: NPeng Fan <peng.fan@nxp.com>

During very early boot-ROM execution the pinmux
configuration isi in Hi-Z state. If pull-up is enabled
on GPIO pad's there will be a short period of toggle
from high to low on the IO when GPIO is set low during
boot. To avoid this glitch, disable pull-up configuration
in GPIO pinmux.
Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com>

In case when usb_composite_register() failed once (for whatever reason),
it will fail further even if all conditions are correct. Example:

    => fastboot 2
    Invalid Controller Index
    couldn't find an available UDC
    g_dnl_register: failed!, error: -19
    exit not allowed from main input shell.

    => fastboot 0
    g_dnl_register: failed!, error: -22
    exit not allowed from main input shell.

Despite that 0 is correct index for USB controller, "fastboot 0" command
will fail, because "composite" structure wasn't cleared properly on
previous fail (on "fastboot 2" command).

This patch fixes that erroneous behavior, allowing us to use composite
even after previous failure.
Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org>

Signed-off-by: NTom Rini <trini@konsulko.com>

"fastboot oem format" command reuses "gpt write" command, which in turn
requires correct partitions defined in $partitions variable. This patch
adds such definition of Android partitions for DRA7XX EVM board.

By default $partitions variable contains Linux partition table. In order
to prepare Android environment one can run next commands from U-Boot
shell:

    => env set partitions $partitions_android
    => env save

After those operations one can go to fastboot mode and perform
"fastboot oem format" to create Android partition table.

While at it, enable CONFIG_RANDOM_UUID to spare user from providing
UUIDs for each partition manually.
Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

This introduces some minor cleanups, regarding aspects such as board name, code
and headers organization as well as deprecated and missing config options.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
Reviewed-by: NTom Rini <trini@konsulko.com>

Fix typo in comment about position of 'A' bit in several start.S.
Signed-off-by: NYuichiro Goto <goto.yuichiro@espark.co.jp>

There are a number of AMCC platforms which are close to, or with some
toolchains exceeding, the size constraints.  Disable CONFIG_SYS_LONGHELP
to get us room to build with again.
Signed-off-by: NTom Rini <trini@konsulko.com>

Copy these from Linux v4.5-rc6 tag.

This is needed so that we can keep up with newer gcc versions.  Note
that we don't have the uapi/ hierarchy from the kernel so continue to
use <linux/types.h>
Signed-off-by: NTom Rini <trini@konsulko.com>

The UniPhier SoC family has not supported ARMv8 yet, but these would
cause warnings if they were compiled with a 64bit compiler.  Before
adding the ARMv8 support really, fix them now.

Because UniPhier SoCs do not support Large Physical Address Extension,
casting "phys_addr_t" into "unsigned long" would carry the address
as is.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Before adding ARMv8 support, this commit refactors the directory
structure.  Move ARMv7 specific files to arch/arm/mach-uniphier/arm32
to avoid a mess by mixture of ARMv7 and ARMv8 code.  Also move the
"select CPU_V7" to the lower-level menu because we will have to
select ARM64 instead of CPU_V7 for ARMv8 SoCs.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This reverts commit d9a3bec6.

While this is a correct change to do long term it unfortunately breaks a
number of platforms that are using pdata and not named struct members so
they are getting all of their data after 'base' incorrect.
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

Due to the company's awful projecting, PH1-LD10 and PH1-sLD11 have
been renamed to PH1-LD20 and PH1-LD11, respectively.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The chains of "depends on <SoC_name>" in the current Kconfig is
clumsy.  The idea here is to allow users to choose a SoC group first
(SoC group consists of some SoCs that can coexist in one binary).
Then, allow to enable/disable each SoC support in the selected SoC
group.  This makes the Kconfig menu clearer.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

PH1-Pro5 support and ProXstream2/PH1-LD6b support can coexist in one
image and there is bit more room in SPL to accommodate all of them.
Merge uniphier_pro5_defconfig into uniphier_pxs2_defconfig.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Rename the variable that contains the base address for consistency.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These macros are no longer used.  These base addresses are
SoC-dependent, so they should not be placed in the header.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, DRAM size is converted twice:
  size in byte -> size in Gbit -> enum

Optimize the code by converting the "size in byte" into enum directly.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Move frequency-dependent register settings to arrays for clean-up.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Support DDR3-1600 / 512MB DDR size.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Move frequency-dependent register settings to arrays for clean-up.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The if-else statements for the frequency-dependent register settings
seem clumsy.  Moving them to arrays would make it cleaner.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The DDR PHY settings no longer depend on the DRAM size.  Drop the
argument from the init function.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now these three are almost the same.  The only difference is the DTPR1
register dependency on the DRAM size, but it can be ignored.  (It has
already been ignored in PH1-sLD8 and PH1-Pro4.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add a field to distinguish DDR3+ from (standard) DDR3.  It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).

Default DDR3 spec for each SoC:

  PH1-LD4, PH1-sLD8: DDR3+
  Others: DDR3
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These settings control the clocks around the memory controller.
The debug ability is unneeded once it works properly.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These settings were used only for the PH1-sLD3 and older SoCs.  The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>