Move to driver model for USB on QEMU.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Move to driver model for pci on QEMU.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Move chipset-specific codes such as PAM init, PCIe ECAM and MP table
from pci.c to qemu.c, to prepare for DM PCI conversion.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The call to pci_run_vga_bios() is not needed as this is handled
in the vesa_fb driver.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Currently timer_init() is called in board_r.c which is quite late.
Some vgabios execution requires we set up the i8254 timer correctly,
but video initialization comes before timer_init(). Move the call
to board_f.c.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA display controller
class in the PCI configuration space, and should also prevent
it from responding to VGA legacy memory range and I/O addresses.

However test result shows that with just VGA Disable bit set and
a PCIe graphics card connected to one of the PCIe controllers on
the E6xx, accessing the VGA legacy space still causes system hang.
After a number of attempts, it turns out besides VGA Disable bit,
the SDVO (D3:F0) device should be disabled to make it work.

To simplify, use the Function Disable register (offset 0xc4)
to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
two devices will be completely disabled (invisible in the PCI
configuration space) unless a system reset is performed.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Add Kconfig options for 8259 and 8254.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c,
to match their header file names (i8254.h and i8259.h).
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Initialize counter 1, used to refresh request signal. This is
required for legacy purpose as some codes like vgabios utilizes
counter 1 to provide delay functionality.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

This cleans up i8254 and i8259 codes to fix several cosmetic
issues, like coding convention and some comments improvement.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

PARANOID_IRQ_TRIGGERS is not referenced anywhere in U-Boot.
Remove these dead codes wrapped by it.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

CONFIG_SYS_NUM_IRQS is actually not something we can configure,
but an architecture defined number of ISA IRQs. Move it from
x86-common.h to asm/interrupt.h and rename it to SYS_NUM_IRQS.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Prior to commit 5ba534d2 ("arm: Switch 32-bit ARM to using generic
global_data setup") we used to have assembly code that configured the
malloc_base address.

Since this commit we use the board_init_f_mem() function in C to setup
malloc_base address.

In board_init_f_mem() there was a deliberate choice to support only
early malloc() or full malloc() in SPL, but not both.

Adapt this logic to allow both to be used, one after the other, in SPL.

This issue has been observed in a Congatec board, where we need to
retrieve the manufacturing information from the SPI NOR (the SPI API
calls malloc) prior to configuring the DRAM. In this case as malloc_base
was not configured we always see malloc to fail.

With this change we are able to use malloc in SPL prior to DRAM gets
initialized.

Also update the CONFIG_SYS_SPL_MALLOC_START entry in the README file.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This adds support to update firmware on qspi flash present on
am437x-sk-evm and am43xx-epos-evm via DFU.

On device:
=> setenv dfu_alt_info ${dfu_alt_info_qspi}
=> dfu 0 sf 0:0

On host:
$ sudo dfu-util -l
$ sudo dfu-util -D u-boot.bin -a u-boot.bin
Signed-off-by: NVignesh R <vigneshr@ti.com>

CONFIG_OF_EMBED=y is the option which is here only for testing purpose
and shouldn't be enabled by default as is describe at:
"dts: Add a comment about CONFIG_OF_EMBED being for local use"
(sha1: 3d3f60cb)

But still enabling this option locally shouldn't end up with compilation
error when you build SPL. This patch fix it.

Compilation error:
lib/built-in.o: In function `fdtdec_setup':
/mnt/disk/u-boot/lib/fdtdec.c:1246: undefined reference to
`__dtb_dt_begin'
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reported-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Dear u-boot community,

I just made a small change on the openrisc-generic platform
configuration to take in account the new naming convention (or1k instead
of or32, so the build process gets fine).

Could you take care to review and approve the following patch, please?

Kind regards,

Looks like one spot got missed. Probably due to the backslash.
Signed-off-by: NAndy Fleming <afleming@gmail.com>

-> Add National instrument ethernet transceiver configuration used (DP83848)
-> Change cpsw slave phy address
-> modify nand configuration to use the correct ECC and correct nand features

CONFIG_AHCI_SETFEATURES_XFER is not selected by any user, so delete
the dead code.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

get_clocks is wrapped by CONFIG_FSL_CLK and CONFIG_M68K in seperate
piece code. They can be merged into one snippet.
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Cc: "angelo@sysam.it" <angelo@sysam.it>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: "Andreas Bießmann" <andreas.devel@googlemail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Acked-by: NAngelo Dureghello <angelo@sysam.it>

CONFIG_BOOTDELAY is defined in config_distro_defaults.h
Signed-off-by: NMatwey V. Kornilov <matwey.kornilov@gmail.com>
[trini: Drop omap3_logic.h settings which were a warning and no longer
        correct usage].
Signed-off-by: NTom Rini <trini@konsulko.com>

By reading 2 consecutive bytes from i2c to an u16 value
we have an endianess issue.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

Since busses are sorted in alphabetical order, introducing more
than nine busses led to unexpected behaviour.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

osdsize adjusts the gdsys IHS osd dimensions in characters.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

hrcon DH(dual head) has two video outputs per FPGA.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

- i2c addresses for the videoboard port expanders were
  wrong.
- the fpga reset signal was not initialized.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

The strider platform moved some generic code into ioep-fpga.c.
Make use of that on hrcon platform.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

The gdsys strider board is based on a Freescale MPC8308 SOC.
It boots from NOR-Flash, kernel and rootfs are stored on
SD-Card.

On board peripherals include:
- 1x 10/100 Mbit/s Ethernet (optional)
- Lattice ECP3 FPGA connected via eLBC
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
[trini: Drop setting CONFIG_SYS_GENERIC_BOARD, this is always true now]
Signed-off-by: NTom Rini <trini@konsulko.com>

hrcon has no CH7301 DVI-transmitter.
Probably not removed when copying from iocon.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

- Reset FPGAs in last_stage_init()
Signed-off-by: NReinhard Pfau <pfau@gdsys.de>
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

Support dlvision-10g hardware with displayport output.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

DP501 only supports DP 1.1a.
Limit settings for link bandwidth and lane count to
values allowed by DP 1.1a.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>

With Club 3D dual link adapter there are AUX-channel timeouts
when EDID is read. Increasing retry interval time to max (400us)
fixes this.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Bus has to be held for repeated start regardless of
read/write access.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Acked-by: NHeiko Schocher <hs@denx.de>

Reinhard Pfau complained that macros in ihs_i2c do not follow best practices.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Acked-by: NHeiko Schocher <hs@denx.de>