- 16 3月, 2016 9 次提交
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由 Paul Kocialkowski 提交于
Boards using the TWL6030 regulator may not all use the LDOs the same way. Some might also not use MMC1 at all, so VMMC would't have to be enabled. This delegates TWL6030 MMC power initializations to board-specific functions, that may still call twl6030_power_mmc_init for the default behavior. Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
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由 Paul Kocialkowski 提交于
Not every device has multiple MMC slots available, so it makes sense to enable only the required LDOs for the available slots. Generic code in omap_hsmmc will enable both VMMC and VAUX1, in doubt. Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
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由 Paul Kocialkowski 提交于
This enables the VAUX1 supply, used for eMMC power in standard configurations. Its voltage is determined by the value of the BOOT2 pin of the TWL6030. Note that the TWL6030 might already have enabled this regulator at startup (depending on the value of the BOOT3 pin of the TWL6030), according to the TWL6030 datasheet. Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
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由 Paul Kocialkowski 提交于
This makes the twl6030 mmc and usb-related power registers and values definitions more explicit and clear and adds prefixes to them. Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
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由 Paul Kocialkowski 提交于
Reboot mode garbage is found on cold reset and might be seen as valid on the next warm reset, thus it has to be cleared on cold reset. Signed-off-by: NPaul Kocialkowski <contact@paulk.fr> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Paul Kocialkowski 提交于
There is no need to set the reboot mode to a particular value prior to reboot, since valid values will have been caught and cleared earlier. In addition, this breaks the reboot-bootloader fastboot call, by overriding the required value for fastboot. Signed-off-by: NPaul Kocialkowski <contact@paulk.fr> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Paul Kocialkowski 提交于
This introduces a define for the offset to the reboot reason, rather than hardcoding it. Signed-off-by: NPaul Kocialkowski <contact@paulk.fr> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Paul Kocialkowski 提交于
This switches reboot mode handling to a string-based interface, that allows more flexibility to set a common interface with the next generations of OMAP devices. Signed-off-by: NPaul Kocialkowski <contact@paulk.fr> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jagan Teki 提交于
Global definition of priv seems no-sense to use it for non-dm case and pass the pointer to functions which are common to both dm and non-dm. So, fix this by removing omap3_spi_slave from non-dm and make visible to omap3_spi_priv for both dm and non-dm. Cc: Christophe Ricard <christophe-h.ricard@st.com> Reported-by: NTom Rini <trini@konsulko.com> Signed-off-by: NJagan Teki <jteki@openedev.com>
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- 15 3月, 2016 31 次提交
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由 Masahiro Yamada 提交于
To make SPL_OF_CONTROL work on ARM64 SoCs, _image_binary_end must be defined in the linker script. LD spl/u-boot-spl lib/built-in.o: In function `fdtdec_setup': lib/fdtdec.c:1186: undefined reference to `_image_binary_end' lib/fdtdec.c:1186: undefined reference to `_image_binary_end' make[1]: *** [spl/u-boot-spl] Error 1 make: *** [spl/u-boot-spl] Error 2 Note: CONFIG_SPL_SEPARATE_BSS must be defined as well on ARM64 SoCs. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
All the mux configurations needs to be done as part of the IODelay sequence to avoid glitch. Adding all the mux configuration, MANUAL/VIRTUAL mode configuration as needed for DRA72-evm. Also update the mux for SD card detect on DRA74-evm. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NVignesh R <vigneshr@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
Updating the memory banks properly so that DT is populated accordingly. And updating this only after DDR is properly detected by eeprom, so that git bisect is still maintained. Acked-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Enable configs that are required for detecting memory > 2GB. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Enable EEPROM support for DRA74-evm. Acked-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
DRA7 EVM revH and later EVMs have EEPROM populated that can contain board description information such as name, revision, DDR definition, etc. Adding support for this EEPROM format. Acked-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
There are certain EMIF timing failures seen on the some x15 boards. Updating the EMIF settings to get rid of these timing failures. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Adam Ford 提交于
A few boards still use ns16550_platdata structures, but assume the structure is going to be in a specific order. By explicitly naming each entry, this should also help 'future-proof' in the event the structure changes. Tested on the Logic PD Torpedo + Wireless. I only changed a handful of devices that used the same syntax as the Logic board. Appologies if I missed one or stepped on toes. Thanks to Derald Woods and Alexander Graf. Signed-off-by: NAdam Ford <aford173@gmail.com> V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c V4: Fix subject heading V3: Remove reg_offset out in all the structs. It was reverted out, and and if it did exist, it would get initialized to 0 by default. V2: I hastily copy-pasted the boards without looking at the UART number. This addresses 3 boards that use UART3 and not UART1. Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Lokesh Vutla 提交于
Early system initialization is being done before initf_dm is being called in U-Boot. Then system will fail to boot if any of the DM enabled driver is being called in this system initialization code. So, rearrange the code a bit so that DM enabled drivers can be called during early system initialization. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
Given that DRA7/OMAP5 SoCs can support more than 2GB of memory, enable interleaving for this higher memory to increase performance. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
Read and write leveling can be enabled independently. Check for these enable bits before updating the read and write leveling output values. This will allow to use the combination of software and hardware leveling. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control) enables Self refresh mode by default and during warm reset the EMIF contents are preserved. After warm reset EMIF sees that it is idle and puts DDR in self-refresh. When in SR, leveling operations cannot be done as DDR can only accept SR exit command, so its hanging during warm reset. In order to fix this reset the power management control register before EMIF initialization if it is a warm reset. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
On DRA7, refresh ctrl shadow should be updated with the final value. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
OMAP timer driver directly typecasts fdt_addr_t to a pointer. This is not strictly correct, as it gives a build warning when fdt_addr_t is u64. So, use map_physmem for a proper typecasts. This is inspired by commit 167efe01 ("dm: ns16550: Use an address instead of a pointer for the uart base") Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Vitaly Andrianov 提交于
Because KS2 u-boot works in 32 bit address space the existing ram_size global data field cannot be used. The maximum, which the get_ram_size() can detect is 2GB only. The ft_board_setup() needs the actual ddr3 size to fix up dtb. This commit introduces the ddr3_get_size() which uses SPD data to calculate the ddr3 size. This function replaces the "ddr3_size" environment variable, which was used to get the SODIMM size. For platforms, which don't have SODIMM with SPD and ddr3 is populated to a board a simple ddr3_get_size function that returns ddr3 size has to be implemented. See hardware-k2l.h Signed-off-by: NVitaly Andrianov <vitalya@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Vitaly Andrianov 提交于
This commit replaces hard-coded EMIF and PHY DDR3 configurations for predefined SODIMMs to a calculated configuration. The SODIMM parameters are read from SODIMM's SPD and used to calculated the configuration. The current commit supports calculation for DDR3 with 1600MHz and 1333MHz only. Signed-off-by: NVitaly Andrianov <vitalya@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
The maximum device and arm speeds can be determined by reading EFUSE_BOOTROM register. As there is already a framework for reading this register, adding support for all possible speeds on k2g devices. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
Its not compulsory that speed definition should be same on EFUSE_BOOTROM register for all keystone 2 devices. So, allow for board specific speed definitions. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Suman Anna 提交于
The DSPs are powered on by default upon a Power ON reset, and they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E during the boot in u-boot. This is not functional on K2G though. Extend the existing DSP power-off support to the only DSP present on K2G. Do note that the PSC clock domain module id for DSP on K2G differs from that of previous Keystone2 SoCs. Signed-off-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Suman Anna 提交于
Define a macro for the DSP GEM power domain id number and use it instead of a hard-coded number in the code that disables all the DSPs on various Keystone2 SoCs. Signed-off-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Stefan Roese 提交于
These cyg_ prototypes are not referenced anywhere in current mainline U-Boot. So lets remove them. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Stefan Roese 提交于
The original name of this function is unclear. This patch renames this CRC16 function to crc16_ccitt() matching its name with its implementation. To make the usage of this function more flexible, lets add the CRC start value as parameter to this function. This way it can be used by other functions requiring different start values than 0 as well. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Stefan Roese 提交于
lib/crc16.c is changed to match the common U-Boot coding-style. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 York Sun 提交于
FIT image supports more than 32 bits in addresses by using #address-cell field. Fixing 64-bit support by using this field. Signed-off-by: NYork Sun <york.sun@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 York Sun 提交于
FIT image supports load address and entry address. Getting these addresses can use a common function. Signed-off-by: NYork Sun <york.sun@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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