Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.

Impact:
Boot from IFC may not be successful if IFC_CS3 is used.

Workaround:
If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR.
Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size

Impact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect data

Workaround:
The workaround is to switch to GPCM mode for NOR Flash access.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

For an IFC Erratum (A-003399) we will need to access IFC registers in
cpu_init_early_f() so expand the TLB covering CCSR to 1M.

Since we need a TLB to cover 1M we move to using TLB1 array for all the
early mappings so we can cover various sizes beyond 4k.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

And various defines to enable NAND support and NAND spl code for the
P1010RDB platform.
Signed-off-by: NDipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add NAND support (including spl) on IFC, such as is found on the p1010.

Note that using hardware ECC on IFC with small-page NAND (which is what
comes on the p1010rdb reference board) means there will be insufficient
OOB space for JFFS2, since IFC does not support 1-bit ECC.  UBI should
work, as it does not use OOB for anything but ECC.

When hardware ECC is not enabled in CSOR, software ECC is now used.
Signed-off-by: NDipen Dudhat <Dipen.Dudhat@freescale.com>
[scottwood@freescale.com: ECC rework and misc fixes]
Signed-off-by: NScott Wood <scottwood@freescale.com>

Boot methods supported: NOR Flash, SPI Flash and SDCARD
This patch adds the following basic interfaces:
DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash.

P1010RDB Overview
-----------------
1Gbyte DDR3 (on board DDR)
Local Bus (IFC):
	32Mbyte 16bit NOR flash
	32Mbyte SLC NAND Flash
	64KB CPLD device(GPCM interface)
SPI Flash:
	128 Mbit SPI Flash memory
SD/MMC:
	connector to interface with the SD memory card
SATA:
	1 internal SATA connect to 2.5. 160G SATA2 HDD
	1 eSATA connector to rear panel
USB 2.0:
	x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
	x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
eTSEC:
	eTSEC1: Connected to RGMII PHY VSC8641XKO
	eTSEC2: Connected to SGMII PHY VSC8221
	eTSEC3: Connected to SGMII PHY VSC8221
eCAN:
	Two DB-9 female connectors for Field bus interface
UART:
	supports two UARTs up to 115200 bps for console
TDM:
	2 FXS ports connected via an external SLIC to the TDM interface.
SLIC:
	SPI SLIC
I2C:
	Serial EEprom
	Real time clock
	256 Kbit M24256 I2C EEPROM
PCIe:
	PCIe and mPCIe connectors.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NDipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The following boards share a common design but with minor variations
between them:

P1020MSBG-PC
P1020RDB-PC
P1020UTM-PC
P1021RDB-PC
P1024RDB
P1025RDB
P2020RDB-PC

The P1020RDB-PC shares its roots in the existing P1020RDB board design,
however uses DDR3 instead of DDR2.
P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK.

Key features on these boards include:
* DDR3
* NOR flash
* NAND flash (on RDB's only)
* SPI flash (on RDB's only)
* SDHC/MMC card slot
* VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
* PCIE slot and mini-PCIE slots

As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported
with this approach. ODT option is forced to fit this set of boards, again
because they don't have regular DIMMs.

CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet
specification for writing timing.

VSC firmware Address is defined by default in config file for eTSEC1.

SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.

Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC
have pins multiplexing. QE function needs to be disabled to access Nor Flash
and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below

'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NZhao Chenhui <b26998@freescale.com>
Signed-off-by: NMatthew McClintock <msm@freescale.com>
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NTang Yuantian <b29983@freescale.com>
Signed-off-by: Nramneek.mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NMatthew McClintock <msm@freescale.com>
Signed-off-by: NXie Xiaobo <X.Xie@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NAkhil Goyal <akhil.goyal@freescale.com>

Before main memory (DDR) is initialized, the on-chip L1 cache is used as a
memory area for the stack and the global data (gd_t) structure.  This is
called the initial RAM area, or initram.  The L1 cache is locked and the TLBs
point to a non-existent address (so that there's no chance it will overlap
main memory or any device).  The L1 cache is also configured not to write
out to memory or the L2 cache, so everything stays in the L1 cache.

One of the things we might do while running out of initram is relocate CCSR.
On reset, CCSR is typically located at some high 32-bit address, like
0xfe000000, and this may not be the best place for CCSR.  For example, on
36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit
memory space.

On some future Freescale SOCs, the L1 cache will be forced to write to the
backing store, so we can no longer have the TLBs point to non-existent address.
Instead, we will point the TLBs to an unused area in CCSR.  In order for this
technique to work, CCSR needs to be relocated before the initram memory is
enabled.

Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs
we create now for relocating CCSR are deleted after the relocation is finished.
cpu_init_early_f() will still need to create a TLB for CCSR (at the new
location) for normal U-Boot purposes.  This is done to keep the impact to
existing U-Boot code minimal and to better isolate the CCSR relocation code.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
This is necessary for the assembly-language code that relocates CCSR, since
the assembler does not understand 64-bit constants.

CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the
CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it
should not be defined in a board header file.  Similarly,
CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so
it should also not be defined in the board header file.

CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that
CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT,
and so CCSR will not be relocated.

Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot
builds (e.g. NAND) are required to relocate CCSR only during the last stage
(i.e. the "real" U-Boot).  All other stages should define
CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated.

README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add UTMI and ULPI PHY support for USB controller on qoriq series of
processors with internal UTMI PHY implemented, for example P1010/P1014
 - Use both getenv() and hwconfig to get USB phy type till getenv()
   is depricated
 - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc
   has internal UTMI phy
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Acked-by: NRemy Bohmer <linux@bohmer.net>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Since commit d388298a by
Stefano Babic this file is no longer needed so delete it.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Loïc Minier <loic.minier@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This reverts commit 041c5422.

The lines removed by this commit weren't redundant. The logic is (and
probably should be better commented):

Find the intersection of the advertised capabilities of both sides of
the link (lpa).
From that intersection, find the highest capability we can run at
(that will be the negotiated link).

Now imagine that the intersection (lpa) is (LPA_100HALF | LPA_10FULL).

The code will now set phydev->speed to 100, and phydev->duplex to 1,
but this link does not support 100FULL.

Kudos to Andy Fleming <afleming@gmail.com> for binging this to
attention and for the explanation.
Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

* 'master' of git://git.denx.de/u-boot-arm:
  ARM: remove broken "ixdp425" and "ixpdg425" boards

Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: NStefan Roese <sr@denx.de>

Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>

* 'master' of git://git.denx.de/u-boot-arm:
  OMAP3: beagle: Fix build warning in beagle.c

This is a trivial fix in the documentation, which corrects
board_init_r() source reference.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Acked-by: NMike Frysinger <vapier@gentoo.org>

Fix build warning

beagle.c:532: warning: initialization from incompatible pointer type
Signed-off-by: NDirk Behme <dirk.behme@googlemail.com>
CC: Jason Kridner <jkridner@beagleboard.org>
CC: Koen Kooi <koen@dominion.thruhere.net>
CC: Joel A Fernandes <agnel.joel@gmail.com>
Cc: Greg Turner <gregturner@ti.com>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: NJason Kridner <jkridner@beagleboard.org>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

The MAC address stored in the inventory eeprom begins at offset 1.
Signed-off-by: NHolger Brunck <holger.brunck@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
cc: Wolfgang Denk <wd@denx.de>

On some systems, we get a warning when %lu is used with size_t's, so
use the correct format string.
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The new sanity check introduces a printf warning for some systems:
	eth.c:233: warning: format '%zu' expects type 'size_t', but argument 3 has type 'int'

Rather than tweak the format string, use the new assert() helper instead.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Recent commit a4814a69 cleaned up generation of
asm-offsets.s for SoC dirs, but missed adding it to the ignore
list which makes it show up in `git status`.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

There is no code anywhere that references BOOTFLAG_* so remove these
defines.
Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Peter Tyser <ptyser@xes-inc.com>

Commit 09349866 (Put common autoload code into auto_load() function)
broke handling of autoload environment variable not being set.
The bootp/dhcp code will just keep on requesting IP address forever
and never start TFTP download.

Fix it by moving TftpStart() outside the conditional like it was before.
Signed-off-by: NPeter Korsgaard <jacmet@sunsite.dk>
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Flush the dcache before removing the TLB with caches enabled.
Otherwise this might lead to problems later on, e.g. while booting
Linux (as seen on ICON-440SPe).
Signed-off-by: NStefan Roese <sr@denx.de>

Change bd_t->bi_phy* arrays from 1 to 2 for PPC405EX since
405EX has 2 ethernet interfaces.
Signed-off-by: NBernhard Weirich <bernhard.weirich@riedel.net>
Signed-off-by: NStefan Roese <sr@denx.de>

This commit fixes a build warning in the DA830 EVM build
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

Result of running the following command to address Wolfgang's
comment about camel case:

for file in `find . | grep '\.[chS]$'`; do perl -i -pe
's/(green|yellow|red|blue)_LED_(on|off)/$1_led_$2/g' $file; done

Discussion:
http://patchwork.ozlabs.org/patch/84988/Signed-off-by: NJason Kridner <jkridner@beagleboard.org>
Signed-off-by: NJoel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

omap4: fix pad configuration settings for SDP and Panda
Signed-off-by: NAneesh V <aneesh@ti.com>
Signed-off-by: NSebastien Jan <s-jan@ti.com>
Signed-off-by: NDavid Anders <x0132446@ti.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

Tuning some IO settings for better performance and power.
And consolidate all such IO settings at one place.
Signed-off-by: NAneesh V <aneesh@ti.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

SDRAM init was not working on ES1.0 due to a programming
error. A pointer that was passed by value to a function
was set in function emif_get_device_details(), but the effect
wouldn't be seen in the calling function. The issue came
out while testing for ES1.0 because ES1.0 doesn't have any
SDRAM chips connected to CS1
Signed-off-by: NAneesh V <aneesh@ti.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

Factor out common parts from omap4_sdp4430.h and omap4_panda.h
into a new file omap4_common.h
Signed-off-by: NAneesh V <aneesh@ti.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

This patch contains updates the sources in the board files
to use the generic API.
Signed-off-by: NSanjeev Premi <premi@ti.com>

This patch contains the generic changes required after
change to generic API in the previous patch.
Signed-off-by: NSanjeev Premi <premi@ti.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

Convert all OMAP specific functions to use the common API
definitions in include/asm/gpio.h. In the process, made
few additional changes:
 - Use -EINVAL consistently. -1 was used in many places.
 - Removed one-liner static functions that were used only
   once. Replaced the content as necessary.
 - Combines implementation of functions omap_get_gpio_dataout()
   and omap_get_gpio_datain(). To do so, new static function
   _get_gpio_direction() was added.
Signed-off-by: NSanjeev Premi <premi@ti.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>