- 22 7月, 2015 7 次提交
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由 Simon Glass 提交于
The SPL device tree size must be minimised to save memory. Only include properties that are needed by SPL - this is determined by the presence of the "u-boot,dm-pre-reloc" property. Also remove a predefined list of unused properties from the nodes that remain. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This tool allows us to extract subsets of a device tree file. It is used by the SPL vuild, which needs to cut down the device tree size for use in limited memory. This tool was originally written for libfdt but it has not been accepted upstream, so for now, include it in U-Boot. Several utilfdt library functions been included inline here. If fdtgrep is eventually accepted in libfdt then we can bring that version of libfdt in here, and drop fdtgrep (requiring that fdtgrep is provided by the user). If it is not accepted then another approach would be to write a special tool for chopping down device tree files for SPL. While it would use the same libfdt support, it would be less code than fdtgrep.c because it would not have general-purpose functions. Another approach (which was used with v1 of this series) is to sprinkler all the device tree files with #ifdef. I don't like that idea. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
These have been sent upstream but not accepted to libfdt. For now, bring these into U-Boot to enable fdtgrep to operate. We will use fdtgrep to cut device tree files down for SPL. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Property names are stored in a string table. When a node property is removed, the string table is not updated since other nodes may have a property with the same name. Thus it is possible for the string table to build up a number of unused strings. Add a function to remove these. This works by building a new device tree from the old one, adding strings one by one as needed. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Offer to display the available image types in help. Also, rather than hacking the genimg_get_type_id() function to display a list of types, do this in the tool. Also, sort the list. The list of image types is quite long, and hard to discover. Print it out when we show help information. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Provide access to the dhrystone benchmark command. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Drystone provides a convenient sanity check that the CPU is running at full speed. Add this as a command which can be enabled as needed. Note: I investigated using Coremark for this but there was a license agreement and I could not work out if it was GPL-compatible. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 21 7月, 2015 33 次提交
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由 Zhichun Hua 提交于
When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: NZhichun Hua <zhichun.hua@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Zhichun Hua 提交于
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit position [13:12] of TCR_ELx register. Signed-off-by: NZhichun Hua <zhichun.hua@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com>
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Freescale DSPI driver has been converted to Driver Model. The new driver depends on OF_CONTROL, DM, DM_SPI. This patch enable FSL_DSPI and its dependence configure options. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Enable DSPI flash related configurations for LS2085ARDB. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Enable DSPI flash related configurations. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: NHaikun Wang <Haikun.Wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Add dts source files for LS2085AQDS and LS2085ARDB boards. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Add DSPI controller dts node in fsl-ls2085a.dtsi Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Bring in required device tree files for ls2085a from Linux. These are initially unchanged and have a number of pieces not needed by U-Boot. Signed-off-by: NHaikun Wang <Haikun.Wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
As SCFG_ENDIANCR register is added to choose little-endian or big-endian for audio IPs on Rev2.0 silion, little-endian mode is selected. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Wang Dongsheng 提交于
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com> Acked-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Wang Dongsheng 提交于
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well. Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
As the function 'sprintf' does not check buffer boundaries but outputs to the buffer 'enet' of fixed size (16), this patch removes the function 'sprintf', and uses 'strcpy' instead. It will assign the character arrays 'enet' and 'phy' the corresponding character strings. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Linux itb image size has been increased from 30MB. So updating kernel_size to 40MB in env variable. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Export functions required by Aquntia PHY firmware load application. functions are memset, strcpy, mdelay, mdio_get_current_dev, phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Change infinite loop mechanism to timer based polling for QBMAN release in ldpaa_eth_rx. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Polling of TX conf frames is not a mandatory option. Packets can be transferred via WRIOP without TX conf frame. Configure ldpaa_eth driver to use TX path without confirmation frame Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Volatile command does not return frame immidiately, need to wait till a frame is available in DQRR. Ideally it should be a blocking call. Add timeout handling for DQRR frame instead of retry counter. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Do not immediately return if the enqueue function returns -EBUSY; re-try mulitple times. if timeout occures, release the buffer. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Stuart Yoder 提交于
This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Stuart Yoder 提交于
delete any existing ICID pools in the DPC and create a new one based on the stream ID partitioning for the SoC Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Stuart Yoder 提交于
Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Management complex major version should match to the firmware present in flash. Return error during mismatch of major version. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Update qbman driver - As per latest available qbman driver - Use of atomic APIs Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> CC: Geoff Thorpe <Geoff.Thorpe@freescale.com> CC: Haiying Wang <Haiying.Wang@freescale.com> CC: Roy Pledge <Roy.Pledge@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in dpio_attr. These are now offsets from the SoC QBMan portals base. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 J. German Rivera 提交于
Load AIOP image from NOR flash into DDR so that the MC firmware the MC fw can start it at boot time Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Flush buffer before releasing to BMan after TX_conf to ensure, the core does not have any cachelines that the WRIOP will DMA to. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 J. German Rivera 提交于
Make it easier for the user to notice when the MC firmware had problems booting. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Stuart Yoder 提交于
Signed-off-by: Stuart Yoder <stuart.yoder at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
The agreed split of the top of memory is 256M for debug server and 256M for MC. This patch implements the split. In addition, the MC mem must be 512MB aligned, so the amount of memory to hide must be 512MB to achieve that alignment. Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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