- 07 9月, 2016 11 次提交
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由 Christopher Spinrath 提交于
ft_board_setup may return early in the case that the board revision cannot be obtained. In that case it is assumed that no revision specific correction in the fdt is neccessary. But the mtd partitions will not be fixed up either altough they are not revision specific. Move the call to fdt_fixup_mtdparts in front of the revision specific part to ensure that the partitions are fixed up even if the board revision cannot be obtained. While on it, fix a spelling mistake in a comment introduced by the same commit. Fixes: 62d6bac6 ("ARM: board: cm_fx6: fixup mtd partitions in the fdt") Signed-off-by: NChristopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: NStefano Babic <sbabic@denx.de> Reviewed-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Eric Nelson 提交于
Only a single pad is changed to change sdhc2_dat3 from an SDIO pin to and from GPIO4:5, so remove the array and use the imx_iomux_v3_setup_pad() routine. Signed-off-by: NEric Nelson <eric@nelint.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Breno Lima 提交于
Use imx7s-warp.dts as fdt_file because this is the name that upstream kernel will deploy. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Acked-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Fabio Estevam 提交于
Since commit a13d3757 ("warp: Use imx_ddr_size() for calculating the DDR size") warp board no longer boots. The reason for the breakage is that the warp board is using the DDR configuration from mx6slevk. A fundamental difference between warp and mx6slevk is that warp only uses one DDR chip select while mx6slevk uses two. The imx_ddr() function calculates the RAM size in runtime by reading the values of registers MDCTL and MDMISC. So in order to fix this warp boot issue, create a imximage DDR file specific to warp, where the MDCTL register is configured to only activates a single chip select. Reported-by: NBreno Lima <breno.lima@nxp.com> Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Tested-by: NBreno Lima <breno.lima@nxp.com>
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由 Vanessa Maegima 提交于
Add PMIC support. Tested by command "pmic PFUZE3000 dump". Signed-off-by: NVanessa Maegima <vanessa.maegima@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NStefano Babic <sbabic@denx.de>
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由 Akshay Bhat 提交于
Add support for Advantech DMS-BA16 board. The board is based on Advantech BA16 module which has a i.MX6D processor. The board supports: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: NAkshay Bhat <akshay.bhat@timesys.com> Cc: u-boot@lists.denx.de Cc: sbabic@denx.de
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由 Fabio Estevam 提交于
mx7dsabresd has two targets: - mx7dsabresd_defconfig: boots in non-secure mode - mx7dsabresd_secure_defconfig: boots in secure mode Print the mode that is being used to help users to easily identify which target is running on the board. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Stefan Agner 提交于
Currently the command buffer gets allocated with a size of 32 bytes. This causes warning messages on systems with cache lines bigger than 32 bytes: CACHE: Misaligned operation at range [9df17a00, 9df17a20] Define command buffer to be at least 32 bytes, but more if cache line is bigger. Signed-off-by: NStefan Agner <stefan.agner@toradex.com> Reviewed-by: NStefano Babic <sbabic@denx.de>
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由 Tim Harvey 提交于
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Soeren Moch 提交于
HDMI output must be enabled very early to also enable the pre-console buffer Signed-off-by: NSoeren Moch <smoch@web.de> Reviewed-by: NStefano Babic <sbabic@denx.de>
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由 Soeren Moch 提交于
'usb start' is much faster now, so always enable usb keyboard Signed-off-by: NSoeren Moch <smoch@web.de> Reviewed-by: NStefano Babic <sbabic@denx.de>
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- 02 9月, 2016 1 次提交
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由 Peter Chubb 提交于
The Colorado TK1 SOM is a small form factor board similar to the Jetson TK1. The main differences lie in the pinmux, and in that the PCIe controller is set to use in 4lanes+1lane, rather than 2+2. The pinmux header here was generated from a spreadsheet provided by Colorado Engineering using the tegra-pinmux scripts. The spreadsheet was converted from v09 to v11 by me. Signed-off-by: NPeter Chubb <peter.chubb@data61.csiro.au> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 31 8月, 2016 1 次提交
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由 Stephen Warren 提交于
The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric versioning scheme, with version numbers such as 000/100/200/300/400/500. Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00. However, that numbering scheme is not easily visible outside of NVIDIA, and so does not make much sense to use. Convert U-Boot to use the readily visible numeric scheme. Also, it turns out that the current A02 DT actually applies to board versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200 so that all U-Boot builds are named after the first version of the HW they support. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 30 8月, 2016 6 次提交
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由 Bin Meng 提交于
This introduces two board defconfig files for generating EFI 32-bit and 64-bit payloads, to run on QEMU x86 target. With these in place, hopefully buildman will catch any build error with EFI payload support on x86. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
There are lots of warnings when building EFI 64-bit payload. include/asm-generic/bitops/__fls.h:17:2: warning: left shift count >= width of type if (!(word & (~0ul << 32))) { ^ In fact, U-Boot itself as EFI payload is running in 32-bit mode. So BITS_PER_LONG needs to still be 32, but EFI status codes are 64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG to bridge those status codes with U-Boot's BITS_PER_LONG. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Since commit 73c5c399 "Makefile: Drop unnecessary -dtb suffixes", EFI payload does not build anymore. This fixes the build. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a debug() at this point to help figure out what is wrong. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Generally the microcode is combined into a single block only (and removed from the device tree) when there are multiple blocks. But this is not a requirement. Adjust the ivybridge code to avoid assuming this. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a debug() at this point to help figure out what is wrong. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher<hs@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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- 28 8月, 2016 13 次提交
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由 Masahiro Yamada 提交于
This will be useful, for example, to load firmware to DRAM and make it visible to other agents. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
This is very likely to be necessary for normal use cases. Set its default to 'y' for shorter defconfig files. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
The eMMC on sLD3 is assigned with dedicated pins (only multiplexed with GPIO), so it shouldn't hurt to enable eMMC on SPL all the time. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Commit 76c52ce2 ("ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodes") missed to increase this config for sLD3. This change is needed to add "u-boot,dm-pre-reloc" to some nodes; more devices are bound, more malloc memory is needed. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
The revision of the original support card (rev 3.5, rev 3.6) fits in the 8 bit width revision register. When it was extended in a weird way, it was versioned in the format of "3.6.x" (where it should have been "3.7", of course). What is worse, only the sub-level version "6.x" was recorded in the 8 bit width register, completely ignoring the compatibility of the revision register format. This patch saves madly-versioned support cards by assuming the major version "3" when the MSB 4 bit of the register is read as "6". With this, the support card revision that were displayed as "6.10" is now corrected to "3.6.10". Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
This supports the system reset via PSCI for ARMv7 SoCs. Because the system reset is not supported on PSCI 0.1, let's define CONFIG_ARMV7_PSCI_1_0. (it is supported since PSCI 0.2, but there is no CONFIG to enable it in U-Boot for now.) Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
With this, we can save unnecessary udelay(). Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
With the CONFIG_DM_MMC_OPS migration, the .set_ios callback can return an integer now. Return an appropriate error value rather than sudden death by BUG(). Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
No more reason to define this function above the ops structure. Move it near the caller. Also, change its return type to void because it never fails. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Catch up with the DM migration. As struct dm_mmc_ops does not have .init callback, call the init function directly from the probe function. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
They are both only referenced in this file. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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- 27 8月, 2016 8 次提交
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由 Kever Yang 提交于
This patch add maintainer information for rk3399 evb. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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由 Tony Lindgren 提交于
If we do nand device 0 command in u-boot on a device that has NAND support enabled but no NAND chip, we can get data abort at least on omaps. Fix the issue by replacing the check with nand_info[dev] as suggested by Scott Wood. The check for name existed before because before the array-to-pointer conversion there was no way to directly test nand_info[dev] for emptiness. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Masahiro Yamada 提交于
Most of them are my mistakes. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
This is needed to move CONFIG options for the recently-added xtfpga_defconfig. The tarball of the pre-built toolchain can be downloaded from: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Stefan Agner 提交于
The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: NStefan Agner <stefan.agner@toradex.com> Tested-by: NFabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Stefan Agner 提交于
Add LPAE support for mmu_set_region_dcache_behaviour. The function is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7. Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
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由 Tom Rini 提交于
Use a tab not 8 spaces. Signed-off-by: NTom Rini <trini@konsulko.com>
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