- 09 7月, 2017 1 次提交
-
-
由 Christophe Leroy 提交于
Signed-off-by: NChristophe Leroy <christophe.leroy@c-s.fr>
-
- 06 4月, 2017 1 次提交
-
-
由 Tom Rini 提交于
The architecture is currently unmaintained, remove. Cc: Benjamin Matthews <mben12@gmail.com> Cc: Chong Huang <chuang@ucrobotics.com> Cc: Dimitar Penev <dpn@switchfin.org> Cc: Haitao Zhang <hzhang@ucrobotics.com> Cc: I-SYST Micromodule <support@i-syst.com> Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de> Cc: Marek Vasut <marex@denx.de> Cc: Martin Strubel <strubel@section5.ch> Cc: Peter Meerwald <devel@bct-electronic.com> Cc: Sonic Zhang <sonic.adi@gmail.com> Cc: Valentin Yakovenkov <yakovenkov@niistt.ru> Cc: Wojtek Skulski <info@skutek.com> Cc: Wojtek Skulski <skulski@pas.rochester.edu> Signed-off-by: NTom Rini <trini@konsulko.com>
-
- 29 1月, 2017 1 次提交
-
-
由 Michael Kurz 提交于
This patch adds support for the QSPI IP found in stm32f7 devices. Signed-off-by: NMichael Kurz <michi.kurz@gmail.com>
-
- 16 1月, 2017 1 次提交
-
-
由 Jagan Teki 提交于
Dropped becuase - driver not used any board. - no dm conversion. Cc: Angelo Dureghello <angelo@sysam.it> Cc: Richard Retanubun <richardretanubun@ruggedcom.com> Signed-off-by: NJagan Teki <jagan@openedev.com> Acked-by: NAngelo Dureghello <angelo@sysam.it>
-
- 14 1月, 2017 1 次提交
-
-
由 Jagan Teki 提交于
Dropped becuase - driver and related configs not used any board. - no dm conversion. Cc: Heiko Schocher <hs@denx.de> Cc: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Signed-off-by: NJagan Teki <jagan@openedev.com>
-
- 21 12月, 2016 2 次提交
-
-
由 Jagan Teki 提交于
armada100_spi.c and related env is zapping becuase of "no DM conversion". Cc: Ajay Bhargav <ajay.bhargav@einfochips.com> Signed-off-by: NJagan Teki <jagan@openedev.com>
-
由 Jagan Teki 提交于
armada100_spi.c, related config options and related codes are zapping becuase of "no DM conversion". Cc: Werner Pfister <Pfister_Werner@intercontrol.de> Signed-off-by: NJagan Teki <jagan@openedev.com> Reviewed-by: NTom Rini <trini@konsulko.com>
-
- 27 9月, 2016 1 次提交
-
-
由 Stefan Roese 提交于
The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
-
- 10 6月, 2016 1 次提交
-
-
由 Purna Chandra Mandal 提交于
This driver implements SPI protocol in master mode to communicate with the SPI device connected on SPI bus. It handles /CS explicitly by controlling respective pin as gpio ('cs-gpios' property in dt node) and uses PIO mode for SPI transaction. It is configurable based on driver-model only. Cc: Jagan Teki <jteki@openedev.com> Signed-off-by: NPurna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
-
- 21 5月, 2016 1 次提交
-
-
由 Wills Wang 提交于
This patch add a compatible spi driver for ath79 series SOC. Signed-off-by: NWills Wang <wills.wang@live.com> Reviewed-by: NThomas Chou <thomas@wytron.com.tw> Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
-
- 13 11月, 2015 1 次提交
-
-
由 Tom Warren 提交于
This is the normal Tegra SPI driver modified to work with the QSPI controller in Tegra210. It does not do 2x/4x transfers or any other QSPI protocol. Signed-off-by: NYen Lin <yelin@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
-
- 25 10月, 2015 1 次提交
-
-
由 Jagan Teki 提交于
Added zynq qspi controller driver for Xilinx Zynq APSOC, this driver is driver-model driven with devicetree support. => sf probe SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB => mw.b 0x100 0xCC 0x1000000 => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s => sf read 0x3000000 0x0 0x1000000 device 0 whole chip SF: 16777216 bytes @ 0x0 Read: OK => cmp.b 0x3000000 0x100 0x1000000 Total of 16777216 byte(s) were the same Signed-off-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: NJagan Teki <jteki@openedev.com>
-
- 03 9月, 2015 1 次提交
-
-
由 Simon Glass 提交于
Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: NSimon Glass <sjg@chromium.org>
-
- 02 7月, 2015 1 次提交
-
-
由 Jagan Teki 提交于
Use object files as incresing alphabetic order, so-that it's easy for readability. Signed-off-by: NJagan Teki <jteki@openedev.com>
-
- 01 7月, 2015 3 次提交
-
-
由 Jagan Teki 提交于
Zap oc_tiny_spi driver since the boards used this driver is no longer been active. Signed-off-by: NJagan Teki <jteki@openedev.com> Cc: Thomas Chou <thomas@wytron.com.tw>
-
由 Jagan Teki 提交于
Zap ftssp010_spi driver since the boards used this driver is no longer been active. Signed-off-by: NJagan Teki <jteki@openedev.com> Cc: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Axel Lin <axel.lin@ingics.com>
-
由 Jagan Teki 提交于
Zap andes_spi driver since the boards used this driver is no longer been active. Signed-off-by: NJagan Teki <jteki@openedev.com> Cc: Macpaul Lin <macpaul@andestech.com>
-
- 19 4月, 2015 1 次提交
-
-
Move the Freescale DSPI driver over to driver model. Signed-off-by: NHaikun Wang <Haikun.Wang@freescale.com> Acked-by: NSimon Glass <sjg@chromium.org>
-
- 10 4月, 2015 1 次提交
-
-
由 Albert ARIBAUD \(3ADEV\) 提交于
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: NAlbert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
-
- 06 12月, 2014 2 次提交
-
-
由 Stefan Roese 提交于
This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI drivers is not possible. This driver is very loosely based on the Linux driver. Most of the Linux driver is removed. Only the polling loop for the transfer is really used from this driver, as we don't support interrupts and DMA right now. This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
-
由 Stefan Roese 提交于
This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
-
- 23 10月, 2014 5 次提交
-
-
由 Simon Glass 提交于
This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Simon Glass 提交于
Add a new implementation of soft_spi that uses device tree to specify the GPIOs. This will replace soft_spi_legacy for boards which use driver model. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
-
由 Simon Glass 提交于
Reserve the 'normal' name for use by driver model, and rename the old driver so that it is clear that it is for 'legacy' drivers only. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
-
由 Simon Glass 提交于
U-Boot includes a SPI emulation driver already but it is not explicit, and is hidden in the SPI flash code. Conceptually with sandbox's SPI implementation we have a layer which creates SPI bus transitions and a layer which interprets them, currently only for SPI flash. The latter is actually an emulation, and it should be possible to add more than one emulation - not just SPI flash. Add a SPI emulation uclass so that other emulations can be plugged in to support different types of emulated devices on difference buses/chip selects. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
-
由 Simon Glass 提交于
Add a uclass which provides access to SPI buses and includes operations required by SPI. For a time driver model will need to co-exist with the legacy SPI interface so some parts of the header file are changed depending on which is in use. The exports are adjusted also since some functions are not available with driver model. Boards must define CONFIG_DM_SPI to use driver model for SPI. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> (Discussed some follow-up comments which will address in future add-ons)
-
- 05 7月, 2014 1 次提交
-
-
由 Sergey Kostanbaev 提交于
This patch returns back support for old ep93xx processors family Signed-off-by: NSergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
-
- 09 6月, 2014 1 次提交
-
-
由 Alison Wang 提交于
Add Freescale QSPI driver support for VF610. Signed-off-by: NAlison Wang <Huan.Wang@freescale.com> Signed-off-by: NChao Fu <b44548@freescale.com>
-
- 11 1月, 2014 1 次提交
-
-
由 Kuo-Jung Su 提交于
The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF. However This patch implements only the SPI mode. NOTE: The DMA and CS/Clock control logic has been altered since hardware revision 1.19.0. So this patch would first detects the revision id of the underlying chip, and then switch to the corresponding software control routines. Signed-off-by: NKuo-Jung Su <dantesu@faraday-tech.com> Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com> CC: Tom Rini <trini@ti.com>
-
- 19 12月, 2013 1 次提交
-
-
由 Nobuhiro Iwamatsu 提交于
This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: NKouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
-
- 10 12月, 2013 1 次提交
-
-
由 Mike Frysinger 提交于
This adds a SPI framework for people to hook up simulated SPI clients. Signed-off-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
- 01 11月, 2013 1 次提交
-
-
由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
-
- 07 10月, 2013 1 次提交
-
-
由 Matt Porter 提交于
Adds a SPI master driver for the TI QSPI peripheral. - Added quad read support. - Added memory mapped support. Signed-off-by: NMatt Porter <matt.porter@linaro.org> Signed-off-by: NSourav Poddar <sourav.poddar@ti.com> Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
-
- 07 8月, 2013 1 次提交
-
-
Zynq spi controller driver supports 2 buses and 3 chipselects on each bus. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
-
- 24 7月, 2013 1 次提交
-
-
由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
-
- 26 3月, 2013 3 次提交
-
-
由 Allen Martin 提交于
Add driver for tegra114 SPI controller. This controller is not compatible with either the tegra20 or tegra30 controllers, so it requires a new driver. Signed-off-by: NAllen Martin <amartin@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
由 Allen Martin 提交于
Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: NAllen Martin <amartin@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
由 Allen Martin 提交于
Rename tegra SPI drivers to tegra20_flash and tegra20_slink in preparation for commonization and addition of tegra114_spi. Signed-off-by: NAllen Martin <amartin@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
- 19 3月, 2013 2 次提交
-
-
由 Simon Glass 提交于
This supports Intel ICH7/9. The Intel controller is a little unusual in that it is mostly intended for use with SPI flash, and has some optimisations and features specifically for that application. In particular it is not possible to support ongoing transactions that continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END. This driver supports writes of up to 64 bytes at a time, the limit for the controller. Future work will improve this. Signed-off-by: NBernie Thompson <bhthompson@chromium.org> Signed-off-by: NDuncan Laurie <dlaurie@chromium.org> Signed-off-by: NBill Richardson <wfrichar@chromium.org> Signed-off-by: NVadim Bendebury <vbendeb@chromium.org> Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Simon Glass 提交于
At present it is difficult to extend the SPI structure since all drivers allocate it themselves, and few of them zero all fields. Add a new function spi_alloc_slave() which can be used by SPI drivers to perform this allocation, and thus ensure that all drivers can better cope with SPI structure changes. Signed-off-by: NSimon Glass <sjg@chromium.org>
-