- 04 8月, 2015 21 次提交
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由 Nikhil Badola 提交于
Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
By default the bstopre value has been set to 0x100, used to be 1/4 value of refint. Modern DDR has increased the refresh time. Adjust to 1/4 of refresh interval dynamically. Individual board can still override this value in board ddr file, or to use auto-precharge. Signed-off-by: NYork Sun <yorksun@freescale.com>
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Signed-off-by: NHoria Geantă <horia.geanta@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU Fixes: b9eebfad ("fsl_sec: Add hardware accelerated SHA256 and SHA1") Signed-off-by: NHoria Geantă <horia.geanta@freescale.com> Reviewed-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NMingkai Hu <Mingkai.Hu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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Use fdt_setprop_u32() instead of fdt_setprop(). Fixes: 0181937f ("crypto/fsl: Add fixup for crypto node") Signed-off-by: NHoria Geantă <horia.geanta@freescale.com> Reviewed-by: NMingkai Hu <Mingkai.Hu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Minghuan Lian 提交于
The patch will initialize PCIe controller on EP mode 1. Setup bar: bar0 32bit 4K for specific configuration bar1 32bit 8K for MSIX bar2 64bit 4K for descriptor of memory bar4 64bit 1M for DMA memory test 2. Setup iATU: iATU inbound 0-3 to map bar transaction to memory address started at CONFIG_SYS_PCI_EP_MEMORY_BASE iATU outbound 0 to map 4G memory space Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Minghuan Lian 提交于
PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
MC firware version 8.0.0 contains new command flags. This patch contains modifications in FLIB files to support the new command flags. Signed-off-by: NItai Katz <itai.katz@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alex Porosanu 提交于
The sampling of the oscillator can be done in multiple modes for generating the entropy value. By default, this is set to von Neumann. This patch changes the sampling to raw data, since it has been discovered that the generated entropy has a better 'quality'. Signed-off-by: NAlex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alex Porosanu 提交于
The entropy delay (the length in system clocks of each entropy sample) for the RNG4 block of CAAM is dependent on the frequency of the SoC. By elaborate methods, it has been determined that a good starting value for all platforms integrating the CAAM IP is 3200. Using a higher value has additional benefit of speeding up the process of instantiating the RNG, since the entropy delay will be increased and instantiation of the RNG state handles will be reattempted by the driver. If the starting value is low, for certain platforms, this can lead to a quite lengthy process. This patch changes the starting value of the length of the entropy sample to 3200 system clocks. In addition to this change, the attempted entropy delay values are now printed on the console upon initialization of the RNG block. Signed-off-by: NAlex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alex Porosanu 提交于
The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the oscillator, when SEC runs at its maximum frequency. For certain platforms (f.i. T2080), the oscillator is very fast and thus if the SEC runs at a lower than normal frequency, the ring oscillator is incorrectly detected as being out of bounds. This patch effectively disables the maximum frequency check, by setting a high enough maximum allowable frequency for the oscillator. The reasoning behind this is that usually a broken oscillator will run too slow (i.e. not run at all) rather than run too fast. Signed-off-by: NAlex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
To improve eTSEC performance on LS1021A Rev2.0, snooping of all transmit frames from memory and all transmit BD memory accesses in enabled. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
On LS1021A Rev2.0, OCRAM's security level needs to be changed to non-secure access for SD boot. This patch will allow OCRAM access permission as R/W in SPL. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Wang Dongsheng 提交于
Bootrom will put cpus into WFE state when boot cpu release cpus, so target cpu cannot correctly go to spin state. Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target cpu can fall into u-boot spin table. Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 chenhui zhao 提交于
Program the external regulator to switch off voltage in deep sleep. Signed-off-by: NChenhui Zhao <chenhui.zhao@freescale.com> Acked-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Tang Yuantian 提交于
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Acked-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 gaurav rana 提交于
Enable bootscript support in secure boot for establishing chain of trust on LS1021atwr. Signed-off-by: NGaurav Rana <gaurav.rana@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhao Qiang 提交于
strncpy is safer than strcpy, use it to instead of strcpy. Signed-off-by: NZhao Qiang <B45475@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhao Qiang 提交于
when using printf, the parameter type need to be compatible type, so transform them to compatible type Signed-off-by: NZhao Qiang <B45475@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhuoyu Zhang 提交于
For ls1021a, Reserve secure code in to memory in case OCRAM is needed by other usage. Signed-off-by: NZhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Acked-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 03 8月, 2015 1 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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- 02 8月, 2015 18 次提交
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由 Tom Rini 提交于
This function is called from esdhc_send_cmd so we need it available to everyone. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Stefano Babic 提交于
Fix: undefined reference to `spi_flash_free' undefined reference to `spi_flash_probe' Signed-off-by: NStefano Babic <sbabic@denx.de> CC: Stefan Roese <sr@denx.de> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: NStefan Roese <sr@denx.de>
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由 Peng Fan 提交于
1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. 2. Support SPL 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default supports sd for usdhc2, but can do hardware rework to make usdhc2 support emmc. Boot Log: U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device Reset cause: POR Board: MX6UL 14x14 EVK I2C: ready DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
i.MX6UL's DRAM space starts from 0x80000000, same to i.MX6SX, so use same address with i.MX6SX. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs. 2. Add a new function mx6ul_dram_iocfg to configure dram io. 3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support runtime check, but not hardcoding #ifdef macros. 4. Introduce mx6ul-ddr.h, which includes the register address for DRAM IO configuration. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
DRAM space starts from 0x80000000 for i.MX6UL, so need to fix LOADADDR, SYS_TEXT_BASE. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
i.MX6UL does not have GPIO6/7, so do not include them for i.MX6UL. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6) Signed-off-by: NYe.Li <B37916@freescale.com> Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
1.Update WDOG settings. 2.No need to gate/ungate all PFDs for i.MX6UL. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com> Signed-off-by: NYe.Li <B37916@freescale.com>
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由 Peng Fan 提交于
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6 chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled. There is on specific switch for on/off L2 Cache, so default select SYS_L2CACHE_OFF. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
1. Add enet, uart, i2c, ipg clock support for i.MX6UL. 2. Correct get_periph_clk, it should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK. 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not use 'ifdef'. 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX. 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q) || defined....", only need one CONFIG_PCIE_IMX in header file. Signed-off-by: NYe.Li <B37916@freescale.com> Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
Since i.MX6UL use A7 core, but not A9 core, we do not need the erratas for i.MX6UL. Signed-off-by: NYe.Li <B37916@freescale.com> Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
Add i.MX6UL GPT timer support. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
Since i.MX6UL's cache line size is 64bytes, need to define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
1. Update imx register base address for i.MX6UL. 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE. 3. Remove #ifdef for register addresses that equal to "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips. 4. According fuse map, complete fuse_bank4_regs. 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX, because we can use runtime check Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Peng Fan 提交于
Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com> Signed-off-by: NYe.Li <B37916@freescale.com>
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由 Peng Fan 提交于
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which is not real id from DIGPROG register, so change i.MX6D to value 0x67 which was not occupied. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com> Signed-off-by: NYe.Li <B37916@freescale.com>
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