1. 13 2月, 2019 23 次提交
  2. 12 2月, 2019 10 次提交
  3. 11 2月, 2019 7 次提交
    • T
      Merge git://git.denx.de/u-boot-marvell · f4992977
      Tom Rini 提交于
      - Fix BUILD_TARGET for ARCH_MVEBU from Baruch
      - Fix MVEBU PCIe reset issues from Baruch
      - Increase DDR stability on x530 from Chris
      f4992977
    • C
      ARM: mvebu: x530: use MV_DDR_FREQ_SAR · a6ac775b
      Chris Packham 提交于
      MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware
      strapping. This also has the side effect of running the DDR clock in
      synchronous mode with the CPU core clock rather than from an independent
      PLL. We've seen this improve reliability in operation across a number of
      boards and temperature ranges.
      Signed-off-by: NChris Packham <judge.packham@gmail.com>
      Reviewed-by: NStefan Roese <sr@denx.de>
      Signed-off-by: NStefan Roese <sr@denx.de>
      a6ac775b
    • B
      Kconfig: fix BUILD_TARGET for ARCH_MVEBU · 0ef69208
      Baruch Siach 提交于
      Commit dc146ca1 ("Kconfig: Migrate CONFIG_BUILD_TARGET") made the
      mvebu default build target depend on CONFIG_SPL_BUILD. Unfortunately,
      there is no such Kconfig symbol. Use the CONFIG_SPL symbol instead to
      fix that.
      
      Cc: Jagan Teki <jagan@amarulasolutions.com>
      Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
      Reviewed-by: NStefan Roese <sr@denx.de>
      Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
      Signed-off-by: NStefan Roese <sr@denx.de>
      0ef69208
    • B
      arm: mvebu: cf gt-8k: dts: add PCIe slot reset support · d7f165cf
      Baruch Siach 提交于
      Describe the mini-PCIe slot gpio reset signal. This enables PCIe devices
      on Clearfog GT-8K.
      Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
      Reviewed-by: NStefan Roese <sr@denx.de>
      Signed-off-by: NStefan Roese <sr@denx.de>
      d7f165cf
    • B
      pcie: designware: mvebu: fix reset release polarity · 6664a0e5
      Baruch Siach 提交于
      The dm_gpio_set_value() routine sets signal logical level, with
      GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
      (asserted), while reset inactive value is 0 (de-asserted). Fix the reset
      toggle code to set the correct reset logic value.
      Reported-by: NSven Auhagen <sven.auhagen@voleatech.de>
      Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
      Reviewed-by: NStefan Roese <sr@denx.de>
      Signed-off-by: NStefan Roese <sr@denx.de>
      6664a0e5
    • B
      arm: mvebu: mcbin: dts: fix PCIe reset polarity · f301ba55
      Baruch Siach 提交于
      The PCIe slot PERST signal is active low. Fix the gpio signal
      description in the dts.
      
      This happened to work because the pcie_dw_mvebu driver sets the reset
      gpio level to 1 (high) to release the reset. The following commit will
      fix that.
      Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
      Reviewed-by: NStefan Roese <sr@denx.de>
      Signed-off-by: NStefan Roese <sr@denx.de>
      f301ba55
    • M
      i2c: mux: Generate longer i2c mux name · c4bd12a7
      Michal Simek 提交于
      For !DM case busses are listed as
      ZynqMP> i2c bus
      Bus 0:	zynq_0
      Bus 1:	zynq_0->PCA9544A@0x75:0
      Bus 2:	zynq_0->PCA9544A@0x75:1
      Bus 3:	zynq_0->PCA9544A@0x75:2
      Bus 4:	zynq_1
      Bus 5:	zynq_1->PCA9548@0x74:0
      Bus 6:	zynq_1->PCA9548@0x74:1
      Bus 7:	zynq_1->PCA9548@0x74:2
      Bus 8:	zynq_1->PCA9548@0x74:3
      Bus 9:	zynq_1->PCA9548@0x74:4
      Bus 10:	zynq_1->PCA9548@0x75:0
      Bus 11:	zynq_1->PCA9548@0x75:1
      Bus 12:	zynq_1->PCA9548@0x75:2
      Bus 13:	zynq_1->PCA9548@0x75:3
      Bus 14:	zynq_1->PCA9548@0x75:4
      Bus 15:	zynq_1->PCA9548@0x75:5
      Bus 16:	zynq_1->PCA9548@0x75:6
      Bus 17:	zynq_1->PCA9548@0x75:7
      
      where is exactly describing i2c bus topology.
      By moving to DM case i2c mux buses are using names from DT and because
      i2c-muxes describing sub busses with the same names like i2c@0, etc it
      is hard to identify which bus is where.
      Linux is adding topology information to i2c-mux busses to identify them
      better.
      This patch is doing the same and composing bus name with topology
      information.
      
      When patch is applied with topology information on zcu102-revA.
      ZynqMP> i2c bus
      Bus 0:	i2c@ff020000
         20: gpio@20, offset len 1, flags 0
         21: gpio@21, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus 2:	i2c@ff020000->i2c-mux@75->i2c@0
      Bus 3:	i2c@ff020000->i2c-mux@75->i2c@1
      Bus 4:	i2c@ff020000->i2c-mux@75->i2c@2
      Bus 1:	i2c@ff030000  (active 1)
         74: i2c-mux@74, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus 5:	i2c@ff030000->i2c-mux@74->i2c@0  (active 5)
         54: eeprom@54, offset len 1, flags 0
      Bus 6:	i2c@ff030000->i2c-mux@74->i2c@1
      Bus 7:	i2c@ff030000->i2c-mux@74->i2c@2
      Bus 8:	i2c@ff030000->i2c-mux@74->i2c@3
      Bus 9:	i2c@ff030000->i2c-mux@74->i2c@4
      Bus 10:	i2c@ff030000->i2c-mux@75->i2c@0
      Bus 11:	i2c@ff030000->i2c-mux@75->i2c@1
      Bus 12:	i2c@ff030000->i2c-mux@75->i2c@2
      Bus 13:	i2c@ff030000->i2c-mux@75->i2c@3
      Bus 14:	i2c@ff030000->i2c-mux@75->i2c@4
      Bus 15:	i2c@ff030000->i2c-mux@75->i2c@5
      Bus 16:	i2c@ff030000->i2c-mux@75->i2c@6
      Bus 17:	i2c@ff030000->i2c-mux@75->i2c@7
      
      Behavior before the patch is applied.
      ZynqMP> i2c bus
      Bus 0:	i2c@ff020000
         20: gpio@20, offset len 1, flags 0
         21: gpio@21, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus 2:	i2c@0
      Bus 3:	i2c@1
      Bus 4:	i2c@2
      Bus 1:	i2c@ff030000  (active 1)
         74: i2c-mux@74, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus 5:	i2c@0  (active 5)
         54: eeprom@54, offset len 1, flags 0
      Bus 6:	i2c@1
      Bus 7:	i2c@2
      Bus 8:	i2c@3
      Bus 9:	i2c@4
      Bus 10:	i2c@0
      Bus 11:	i2c@1
      Bus 12:	i2c@2
      Bus 13:	i2c@3
      Bus 14:	i2c@4
      Bus 15:	i2c@5
      Bus 16:	i2c@6
      Bus 17:	i2c@7
      Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
      Reviewed-by: NSimon Glass <sjg@chromium.org>
      Reviewed-by: NHeiko Schocher <hs@denx.de>
      c4bd12a7