When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Now that all boards have been converted, remove old config code and the
config option for the new style.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Converted ATUM8548, MPC8568 MDS, MPC8540 EVAL, and TQM85xx boards over
to use new LAW init code.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.

Also, minor cleanup in cache.h to make the code a bit more readable.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

On the MPC85xx boards that have PCIe enable the PCIe errata fix.
(MPC8544DS, MPC8548CDS, MPC8568MDS).
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* Enabled CONFIG_CMD_ELF
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* Removed some misc environment setup
* Enabled CONFIG_CMDLINE_EDITING
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Updated the MPC8568 MDS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

CONFIG_QE shouldn't be in the wrap of CONFIG_PCI, fix it.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

On the MPC8568 MDS we use ttyS0, UART0, etc. as the standard configured
console.  Make it so we match that config what we tell Linux as the early
STDOUT console.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The L2 cache size is 512KB for 8568, print out the correct informaiton.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

and make some minor corrections to the FDT part of the README.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Actually, fixed a large bug in the UEC for *all* platforms.
How did this ever work?

uec_init() did not follow the spec for eth_init(), and returned
0 on success.  Switch it to return the link like tsec_init()
(and 0 on error)

The immap for the 8568 was defined based on MPC8568, rather than
CONFIG_MPC8568

CONFIG_QE was off

CONFIG_ETHPRIME was set to "Freescale GETH".  Now is "FSL UEC0"

Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is
enabled
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The tsec_info structure and array has a "flags" field for each
ethernet controller.  This field is the only reason there are
settings.  Switch to defining TSECn_FLAGS for each controller
in the config header, and we can greatly simplify the array, and
also simplify the addition of future boards.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

This patch is against u-boot-mpc85xx.git of www.denx.com
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NEbony Zhu <ebony.zhu@freescale.com>

Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h
used to be included but CONFIG_BOOTP_MASK was not defined.

Remove lingering references to CFG_CMD_* symbols.
Signed-off-by: NJon Loeliger <jdl@freescale.com>

Signed-off-by: NJon Loeliger <jdl@freescale.com>

For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

This included some changes to common files:
* Add 8568 processor SVR to various places
* Add support for setting the qe bus-frequency value in the dts
* Add the 8568MDS target to the Makefile
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit
52c7a68b which failed to update the #define's
describing the local address window used for the PCI I/O space accesses -- fix
this and carry over the necessary changes into the MPC8560ADS code since the
PCI I/O space mapping was also broken for this board (by the earlier commit
08745460).  Add the comments clarifying how
the PCI I/O space must be mapped to all the MPC85xx board config. headers.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>

 board/mpc8540ads/init.S      |    4 ++--
 board/mpc8560ads/init.S      |    4 ++--
 include/configs/MPC8540ADS.h |    5 ++---
 include/configs/MPC8541CDS.h |    2 +-
 include/configs/MPC8548CDS.h |    2 +-
 include/configs/MPC8560ADS.h |    8 ++++----
 6 files changed, 12 insertions(+), 13 deletions(-)

Introduced COFIG_FSL_I2C to select the common FSL I2C driver.
And removed hard i2c path from a few u-boot.lds scipts too.
Minor whitespace cleanups along the way.
Signed-off-by: NJon Loeliger <jdl@freescale.com>

* Added support for PCI2 on CDS
  Patch by Andy Fleming 17-Mar-2006
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Signed-off-by: NJon Loeliger <jdl@freescale.com>

* Added support for PCI2 on CDS
  Patch by Andy Fleming 17-Mar-2006
Signed-off-by: NAndy Fleming <afleming@freescale.com>

  Patch by Jon Loeliger 17-Jan-2006
Signed-off-by: NJon Loeliger <jdl@freescale.com>

  Implemented support for MPC8548CDS board.
  Added DDR II support based on SPD values for MPC85xx boards.
  This roll-up patch also includes bugfies for the previously
  published patches:
    DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O

  For MPC85xxCDS:
    Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow
    for faster flash parts.
    Add documentation for BR/OR for FLASH.

  - Convert the CPM2 based functionality to use new CONFIG_CPM2
    option rather than a myriad of CONFIG_MPC8560-like variants.
    Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
    Eliminates the CONFIG_MPC8560 option entirely.  Distributes the
    new CONFIG_CPM2 option to each 8260 board.

  Reset monitor size back to 256 so environment can be written
  to flash on MPC85xx ADS and CDS releases.

* Patch by Paolo Broggini, 02 Sep 2004:
  Make BSS clearing on ARM systems more robust

* Patch by Yue Hu and Joe, 01 Sep 2004:
  - add PCI support for ixp425;
  - add EEPRO100 suppor tfor ixdp425 board.

* Fix problem with protected sector detection in driver/cfi_flash.c

* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to
  pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for
  additional ethernet addresses.

* Cleanup drivers/i82365.c - avoid duplication of code

* Fix bogus "cannot span across banks" flash error message

* Add support for CompactFlash for the CPC45 Board.

- Add support for Altera Nios-II processors.
- Add support for Psyent PCI-5441 board.
- Add support for Psyent PK1C20 board.

- Add support for the MPC8541 and MPC8555 CDS boards
- Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR

  - Fix PCI window on MPC85xx; remove unneeded PCI initialization
    from board_early_init_f()
  - Provide SW workaround for PCI initialization on 85xx CDS
  - Convert MPC85xxADS to use common CFI flash driver

* Cleanup: avoid compiler warnings

* Add CMC PU2 board to MAKEALL script

- support larger DDR memories up to 2G on the PC8540/8560ADS and
  STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads

Completion of the 8540ADS/8560ADS updates:
Fix some PCI and Rapid I/O memory maps,
Initialize both TSEC 1 and 2,
Initialize SDRAM
Update MAINTAINER for 85xx boards and README.mpc85xxads