The A72 U-boot can support early booting of any of the Main or MCU R5F
remote processors from U-boot prompt to achieve various system usecases
before booting the Linux kernel. Update the default BOOTCOMMAND to provide
an automatic and easier way to start various remote processors through
added environment variables.
Signed-off-by: NSuman Anna <s-anna@ti.com>

The J7200 SoCs has two R5F sub-systems. Enable the TI K3
R5F remoteproc driver and the remoteproc command options
to allow these R5F processors to be booted from A72 U-Boot.

The Kconfigs are added using savedefconfig.
Signed-off-by: NSuman Anna <s-anna@ti.com>

The J7200 SoCs have different number of remote processors, but reuse
the same environment settings as the J721E SoCs. The current env
variable rproc_fw_binaries is geared towards J721E SoCs and is
incorrect for J7200 SoCs. Please see the logic originally added in
commit 0b4ab9c9 ("env: ti: j721e-evm: Add support to boot rprocs
including R5Fs and DSPs").

Fix this by defining the DEFAULT_RPROCS macro appropriately using
the corresponding TARGET_EVM Kconfig symbol. This macro is used by
the 'rproc_fw_binaries' env variable in the common remoteproc env
header file k3_rproc.h.

The list of R5F cores to be started before loading and booting the
Linux kernel are as follows, and mainly comprises of the Main R5FSS0
cores in this order:
   Main R5FSS0 (Split) Core0 : 2 /lib/firmware/j7200-main-r5f0_0-fw
   Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7200-main-r5f0_1-fw

The MCU R5FSS0 is in LockStep mode and is expected to be booted by
R5 SPL, so it is not included in the list. The order of rprocs to
boot cannot be really modified as only the Main R5FSS0 cores are
involved and Core0 has to be booted first always before the
corresponding Core1.
Signed-off-by: NSuman Anna <s-anna@ti.com>

The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MAIN domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: NSuman Anna <s-anna@ti.com>

The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: NSuman Anna <s-anna@ti.com>

The A72 U-Boot code can load and boot a number of the available
R5FSS Cores on the J7200 SoC. Change the memory attributes for the
DDR regions used by the remote processors so that the cores can see
and execute the proper code.

The J7200 SoC has less number of remote processors compared to J721E,
so use less memory for the remote processors. So, a separate table
based on the current J721E table is added for J7200 SoCs, and selected
using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol.
Signed-off-by: NSuman Anna <s-anna@ti.com>

The K3 J7200 SoC family has a revised R5F sub-system and contains a
subset of the R5F clusters present on J721E SoCs. The integration of
these clusters is very much similar to J721E SoCs otherwise.

The revised IP has the following two new features:
 1. TCMs are auto-initialized during module power-up, and the behavior
    is programmable through a MMR bit controlled by System Firmware.
 2. The LockStep-mode allows the Core1 TCMs to be combined with the
    Core0 TCMs effectively doubling the amount of TCMs available.
    The LockStep-mode on previous SoCs could only use the Core0 TCMs.
    This combined TCMs appear contiguous at the respective Core0 TCM
    addresses.

Add the support to these clusters in the K3 R5F remoteproc driver
using J7200 specific compatibles and revised logic accounting for
the above IP features/differences.
Signed-off-by: NSuman Anna <s-anna@ti.com>

The K3 J7200 SoCs have two dual-core Arm R5F clusters/subsystems, with
2 R5F cores each, one in each of the MCU and MAIN voltage domains.

These clusters are a revised version compared to those present on
J721E SoCs. Update the K3 R5F remoteproc bindings with the compatible
info relevant to these R5F clusters/subsystems on K3 J7200 SoCs.
Signed-off-by: NSuman Anna <s-anna@ti.com>

The commit 316c9271 ("include: configs: j721e_evm: Add env variables
for mcu_r5fss0_core0 & main_r5fss0_core0") added four different new env
variables 'addr_mainr5f0_0load', 'name_mainr5f0_0fw', 'addr_mcur5f0_0load'
and 'name_mcur5f0_0fw' to the generic environment, but these are only
needed and used in R5 SPL for early-booting the MCU R5FSS0 and Main
R5FSS0 Core0 on J721E SoCs.

These are not really needed for A72 U-Boot, so limit the scope of
these variables only to R5 SPL. While at this, also fix the loadaddr
variable values to include the hex prefix like with other such env
variables.

Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: NSuman Anna <s-anna@ti.com>

The default rproc list currently used by A72 U-Boot to boot various
remote processors include the Main R5FSS0 (Split-mode) Core1, Main
R5FSS1 (LockStep mode) Core0 and the three DSPs. The Main R5FSS1 cluster
is configured for Split mode by default in the dts now, so add the
Main R5FSS1 Core1 (rproc #5) to the default rproc boot list. This
core is now booted after the Main R5FSS1 Core0 and before the DSPs.

The order of the rprocs to boot can always be changed at runtime if
desired by overwriting the 'rproc_fw_binaries' environment variable
at U-boot prompt. Note that the R5FSS Core1 cannot be booted before
its associated Core0.
Signed-off-by: NSuman Anna <s-anna@ti.com>

Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the
default so that two different applications can be run on each of the
R5F cores in performance mode. LockStep-mode would be available only
on SoCs efused with the appropriate bit, and Split-mode is the mode
that is available on all J721E SoCs.
Signed-off-by: NSuman Anna <s-anna@ti.com>

Add memory mapped address location of U-Boot images in HyperFlash boot
mode.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>

Enable configs required to support HyperFlash boot and detection of
onboard mux switch for HyperFlash selection
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>

Enable HyperBus and HyperFlash to support HyperFlash boot.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>

On J7200 SoC OSPI and HypeFlash are muxed at HW level and only one of
them can be used at any time. J7200 EVM has both HyperFlash and OSPI
flash on board. There is a user switch (SW3.1) that can be toggled to
select OSPI flash vs HyperFlash.
Read the state of this switch via wkup_gpio0_6 line and fixup the DT
nodes to select OSPI vs HyperFlash
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>

HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar
to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode
to NOR boot to enable SPL to load next stage using NOR boot flow.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Rsync all defconfig files using moveconfig.py
Signed-off-by: NTom Rini <trini@konsulko.com>

Pull request for UEFI sub-system for efi-2020-10-rc4

Bug fixes are provided in the following areas:

* convert file system debug and print messages go log messages
* convert UEFI booting messages to log messages
* UEFI related code clean up and simplification

CONFIG_EFI_LOADER cannot be selected for ARMv7-M CPUs. So don't check it in
the Makefile.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

The image size is checked in efi_load_pe(). Avoid checking it twice.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

* Eliminate superfluous enum value EFI_TABLE_END.
* Use correct variable type for the memory type.
* Check validity of memory type.
* Make efi_build_mem_table static.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Currently if the bootefi command fails due to missing authentication, the
user gets no feedback.

Write a log message 'Image not authenticated' if LoadImage() fails due to
missing authentication.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Use log_err() for error messages.
Replace debug() by EFI_PRINT().
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Write log messages when booting via the bootefi command to allow tracking
on the syslog server. Example messages are

    Booting /snp.efi

or

    Booting /MemoryMapped(0x0,0x4fe00000,0x35a40)
    Loading image failed
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Use log functions for error and debug messages of the file-system.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

- Fix SATA issue on Armada 3720
- Enable more SPI NOR chips in espressobin defconfig

Enable support of ISSI SPI flashes found on EspressoBIN boards

Change-Id: I6de61c48f108fb4f410f321b9db45887d23212e5
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/61455Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NGrzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: NStefan Chulski <stefanc@marvell.com>
Reviewed-by: NStefan Roese <sr@denx.de>

Include support for CONFIG_SPI_FLASH_GIGADEVICE for supporting
newly produces EspressoBin boards (v7)

Change-Id: I5d4b972cbe2ee5a9d52ce9908794ad4e1b59ee3b
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/61236Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Reviewed-by: NStefan Roese <sr@denx.de>

- This patch moves sata phy powerup from dedicate phy to compphy
  and adds invert option for sata powerup routine.

Change-Id: I1b4e8753e2b2c14c6efa97bca2ffc7d2553d8a90
Signed-off-by: Nzachary <zhangzg@marvell.com>
Signed-off-by: NKen Ma <make@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/53601Reviewed-by: NIgal Liberman <igall@marvell.com>
Tested-by: NIgal Liberman <igall@marvell.com>
[a.heider: adapt to mainline]
Signed-off-by: NAndre Heider <a.heider@gmail.com>
Tested-by: NPali Rohár <pali@kernel.org>
Reviewed-by: NStefan Roese <sr@denx.de>

- Mostly DFU fixes and r8152 fixes

- SH serial bugfix

- SoCFPGA bugfix

Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.
Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>

- New base snapshot
- Fix for high UID/GID numbers on a toolchain
Signed-off-by: NTom Rini <trini@konsulko.com>

- Fix parsing of "mtrr list" command
- Introduce USE_EARLY_BOARD_INIT option and remove dead codes for most
  x86 boards

The size returned by 'getvar partition-size' should be in bytes, not in
blocks as fastboot uses that value to generate empty partition when
running format [1].

Note that the function was already returning the proper size in bytes
for NAND devices (see struct part_info details).

[1]
https://android.googlesource.com/platform/system/core/+/refs/heads/android10-release/fastboot/fastboot.cpp#1500Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com>

It was revealed that when the fastboot_tx_write_str function is called
without the previously initialized fastboot_func->in_req->complete field,
a copy of in_req will be sent to the I/O requests queue without
an initialized field.

Moving a piece of code with the initializing of the
fastboot_func->in_req->complete field above transmit_tx allows to solve
this problem.

Fixes: 65c96757 "usb: fastboot: Convert USB f_fastboot to shared fastboot"
Signed-off-by: Nyurii.pidhornyi <yurii.pidhornyi@globallogic.com>

Since the USB HID limits the maximum bandwidth(3072) for interrupt
endpoint transfers, when the bInterval set to 1, we can only support 3
boards to run sdp at the same time. In order to support more boards,
change the bInterval of interrupt endpoint to 3, which will not affect
the transmission speed.
Reviewed-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NSherry Sun <sherry.sun@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

EP0 has been used to transfer file data in sdp before, but the max
packetsize of ep0 is 64 bytes. So in order to improve the file transfer
speed, here add the EP1_OUT interrupt endpoint which max packetsize is
set to 1024 byte.

After testing, it turns out that using ep1out is twice as fast as using
ep0 while receiving data in sdp.
Signed-off-by: NSherry Sun <sherry.sun@nxp.com>
Reviewed-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>