- 05 4月, 2017 11 次提交
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由 Heiko Stübner 提交于
Building sd images for rk3188 requires more steps due to the needed split into TPL and SPL as loaders. Describe how to build an image for it in a separate paragraph in the READER.rockchip file. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Heiko Stübner 提交于
Commit c67c8c60 ("board_init.c: Always use memset()") dropped the naive memset alternative from board_init_f_init_reserve. So activate CONFIG_TPL_LIBGENERIC for that common memset implementation. We cannot use the ARCH-specific memset, as that would incur 200bytes of additional TPL size, space we do not have. Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Kever Yang 提交于
Rockchip spl driver needs using spl_early_init(). Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit) Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NHeiko Stuebner <heiko@sntech.de> Tested-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The config options for pinctrl on the RK3188, RK3288, RK3328 and RK3399 previously showed up in menuconfig with the generic string descriptor "Rockchip pin control driver" requiring one to look through the help/full description to identify which chip each menu entry was for. This change renames each option with the chip-name in the description string to make it easy to identify the configuration options in menuconfig. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
To simplify the creation of AArch64 SPL images for the RK3399, we use the ENABLE_ARM_SOC_BOOT0_HOOK option and prepend 4 bytes of padding at the start of the text section. This makes it easy for mkimage to rewrite this word with the 'RK33' boot magic. This change brings logic to calculate the header size and allocate the header back in sync. For the RK3399 we now limit the header to before the payload (i.e. the 'header0' and the padding up to the actual image) and overwrite the first word (inserted by the boot0-hook for this purpose) with the 'RK33' magic in-place. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
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由 Philipp Tomsich 提交于
The SPL binary needs to be prefixed with the boot magic ('RK33' for the RK3399) on the Rockchip platform and starts execution of the instruction word following immediately after this boot magic. This poses a challenge for AArch64 (ARMv8) binaries, as the .text section would need to start on the odd address, violating natural alignment (and potentially triggering a fault for any code that tries to access 64bit values embedded in the .text section). A quick and easy fix is to have the .text section include the 'RK33' magic and pad it with a boot0 hook to insert 4 bytes of padding at the start of the section (with the intention of having mkimage overwrite this padding with the appropriate boot magic). This avoids having to modify the linker scripts or more complex logic in mkimage. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
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由 Philipp Tomsich 提交于
The RK3399 boot code (running as AArch64) poses a bit of a challenge for SPL image generation: * The BootROM will start execution right after the 4-byte header (at the odd instruction word loaded into SRAM at 0xff8c2004, with the 'RK33' boot magic residing at 0xff8c2000). * The default padding (during ELF generation) for AArch64 is 0x0, which is an illegal instruction and the .text section needs to be naturally aligned (someone might locate a 64bit constant relative to the section start and unaligned loads trigger a fault for all privileged modes of an ARMv8)... so we can't simply define the CONFIG_SPL_TEXT_BASE option to the odd address (0xff8c2004). * Finally, we don't want to change the values used for padding of the SPL .text section for all ARMv8 targets to the instruction word encoding 'nop', as this would affect all padding in this section and might hide errors that would otherwise quickly trigger an illegal insn exception. To deal with this situation, we modify the rkimage generation to - understand the fact that the RK3399 needs to pad the header to an 8 byte boundary using an AArch64 'nop' - the necessary logic to adjust the header_size (which controls the location where the payload is copied into the image) and to insert this padding (AArch64 insn words are always little-endian) into the image following the 4-byte header magic. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
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由 Philipp Tomsich 提交于
The RC4 encoding works on full blocks, but the calculation of the starting offset and size are needlessly complicated by using a reference value known to be offset into a block by the size of the header and then correcting for the (hard-coded) size of the header (i.e. 4 bytes). We change this over to use the RK_SPL_HDR_START directly (which is known to be on a block boundary). X-AffectedPlatforms: RK3399-Q7 Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
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由 Jacob Chen 提交于
we are using mmc alias , so mmc index have been changed. now mmc dev 0 is emmc and mmc dev 1 is sdmmc. Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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- 04 4月, 2017 6 次提交
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git://git.denx.de/u-boot-arc由 Tom Rini 提交于
In this patch-set we add support of new AXS103 firmware as well as troubleshoot unexpected execution by multiple cores simultaneously.
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git://www.denx.de/git/u-boot-marvell由 Tom Rini 提交于
This includes Marvell mvpp2 patches with the ethernet support for the ARMv8 Armada 7k/8k platforms. The ethernet patches are all acked by Joe and he is okay with me pushing them via the Marvell tree.
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- 02 4月, 2017 3 次提交
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由 Marcel Ziswiler 提交于
Actually make use of that shiny new CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK. Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Marcel Ziswiler 提交于
Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock loopback and use the internal one on SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM. Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Acked-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Marcel Ziswiler 提交于
This patch adds board support for the Toradex Apalis TK1 a computer on module which can be used on different carrier boards. The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec. Furthermore, there is a Kinetis MK20DN512 companion micro controller for analogue, CAN and resistive touch functionality. For the sake of ease of use we do not distinguish between different carrier boards for now as the base module features are deemed sufficient enough for regular booting. The following functionality is working so far: - eMMC boot, environment storage and Toradex factory config block - Gigabit Ethernet - MMC/SD cards (both MMC1 as well as SD1 slot) - USB client/host (dual role OTG port as client e.g. for DFU/UMS or host, other two ports as host) Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 01 4月, 2017 3 次提交
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由 Alexey Brodkin 提交于
Even though we expect only master core to execute U-Boot code let's make sure even if for some reason slave cores attempt to execute U-Boot in parallel with master they get halted very early. If platform wants it may kick-start slave cores before passing control to say Linux kernel or any other application that want to see all cores of SMP SoC up and running. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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由 Alexey Brodkin 提交于
In axs103 v1.1 procedure to kick-start slave cores has changed quite a bit compared t previous implementation. In particular: * We used to have a generic START bit for all cores selected by CORE_SEL mask. But now we don't touch CORE_SEL at all because we have a dedicated START bit for each core: bit 0: Core 0 (master) bit 1: Core 1 (slave) * Now there's no need to select "manual" mode of core start Additional challenge for us is how to tell which axs103 firmware we're dealing with. For now we'll rely on ARC core version which was bumped from 2.1c to 3.0. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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由 Alexey Brodkin 提交于
* Rely on default pulse polarity value * Don't mess with "multicore" value as it doesn't affect execution In essence we now do a bare minimal stuff: 1) Select HS38x2_1 with CORE_SEL=1 bits 2) Select "manual" core start (via CREG) with START_MODE=0 3) Generate cpu_start pulse with START=1 Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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- 30 3月, 2017 4 次提交
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由 Jean-Jacques Hiblot 提交于
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jean-Jacques Hiblot 提交于
This is a preparation work for the support of CONFIG_BLK. Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jean-Jacques Hiblot 提交于
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jean-Jacques Hiblot 提交于
For consistency, use an accessor to access the private data. Also for the same reason, rename all priv_data to priv. Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 29 3月, 2017 13 次提交
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由 Stefan Roese 提交于
The Marvell PHY support is needed espescially for the A7040-DB with the SGMII port (port 2). As without the marvell PHY driver configuration for SGMII, ethernet won't work. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
The default configuration for the COMPHY-0 port should be 1G, as its used as 1G SGMII connection. This change is necessary to get the MAC2 port (SGMII) working on this DB. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
As pointed out by Stefan Chulski, this variable is unused and should be removed. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
On PPv2.2 we enable PHY polling, so we also need to configure the PHY address in the specific PHY address rgisters. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Testing shows, that PHY polling needs to be enabled on Armada 7k/8k. Otherwise ethernet transfers will not work correctly. PHY polling is enabled per default after reset, so we do not need to specifically enable it, but this makes it clearer. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should be handled identical to PHY_INTERFACE_MODE_RGMII. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver for the missing port 0. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only SFI support have been added, as this is the only interface that this code has been tested with. XAUI and RXAUI support might follow at a later stage. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only RGMII and SGMII support have been added, as these are the only interfaces that this code has been tested with. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Read the "phy-speed" DT property to differentiate between 1 and 2.5GB SGMII operations. Please note that its unclear right now, if this DT property will be accepted in mainline Linux. If not, we need to revisit this code and change it to use the accepted property. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This patch does a bit of restructuring of the probe / init functions, mainly to allow earlier register access as it is needed for the upcoming GoP (Group of Ports) and NetC (Net Complex) code. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This patch adds the PPv2.2 specific FIFO configuration to the mvpp2 driver. The RX FIFO packet data size is changed to the recommended FIFO sizes. The TX FIFO configuration is newly added. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Currently, the naming of the ethernet ports is not handled correctly in the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP also instantiates an ethernet controller with the same device ID's. This patch now takes this into account and adds the required base-id so that the slave-CP ethernet devices will be named "mvpp2-3 ...". This patch also updates my Copyright notice to include 2017 as well. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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