- 23 4月, 2015 18 次提交
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Cc: Linus Walleij <linus.walleij@linaro.org>
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由 Masahiro Yamada 提交于
Switch to CONFIG_ARCH_INTEGRATOR defined by Kconfig. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Cc: Linus Walleij <linus.walleij@linaro.org>
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由 Masahiro Yamada 提交于
Select integrator boards by the combination of platform select (AP/CP) and core module select (CM720T, CM920T, ...). This allows us to remove CONFIG_SYS_EXTRA_OPTIONS and make Kconfig much cleaner. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Cc: Linus Walleij <linus.walleij@linaro.org>
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由 Masahiro Yamada 提交于
The board/SoC select menu in arch/arm/Kconfig is still cluttered. Add ARCH_INTEGRATOR into arch/arm/Kconfig and move the board select under arch/arm/mach-integrator. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Cc: Linus Walleij <linus.walleij@linaro.org>
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由 Masahiro Yamada 提交于
arch/arm/cpu/arm720t/start.S includes <asm/arch/hardware.h>, but the hardware.h headers of ARM720T boards are all empty. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
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由 Masahiro Yamada 提交于
These is a growing trend to license DT files dual GPL and X11 especially in the Linux community. It allows easier reuse of device trees for other software projects. This commit prepares for doing so in U-Boot too, since DT files are often copied from the kernel to U-Boot. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Linus Walleij 提交于
Commit d8bafe13 "ARMv8: enable DM in vexpress64 board" only enabled DM for the simulated vexpress64 board (FVP) with the hardcoded clock value for the simulated board, causing a console regression on the Juno board which was using a different clock setting. Fix this by enabling DM for all vexpress64 boards, defining the clock frequency per-board, deleting the static array of PL01x ports from the config file and relying solely on the port defined in the boardfile using platform data. Cc: David Feng <fenghua@phytium.com.cn> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Hannes Petermaier 提交于
some pins on the board have been rerouted to other peripherals, so we change the pinmux to apply with hardware-design. Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>
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由 Hannes Petermaier 提交于
The NAND-version has been become a bit orphan. Now we need to reactivate it, so bring necessary things: - loading devicetree - switch control signal to correct pins - setup pinmux - default-environment up to date. Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>
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由 Hannes Petermaier 提交于
instead of polling everytime the environment, we take usage of the global gd->fdt_blob variable and check it only against NULL. Variable "dtbaddr" from environment is needed only one time on loading the devicetree within "load_devicetree()" Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>
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由 tang yuantian 提交于
Current driver assumes the AHCI is connected to PCI, this is not true on some SoCs, e.g. LS1021A, which has PCI but the AHCI is in SoC. This patch will enable embedded AHCI devices on platforms with PCI. PCI AHCI devices still can be used by commenting CONFIG_SCSI_AHCI_PLAT option in head file. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 rev13@wp.pl 提交于
Signed-off-by: NKamil Lulko <rev13@wp.pl> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 rev13@wp.pl 提交于
Signed-off-by: NKamil Lulko <rev13@wp.pl> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 rev13@wp.pl 提交于
Signed-off-by: NKamil Lulko <rev13@wp.pl> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 rev13@wp.pl 提交于
Signed-off-by: NKamil Lulko <rev13@wp.pl>
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由 Eric Nelson 提交于
Add gzwrite command to write gzip-compressed images to block devices. Input must be gzip-compressed according to RFC1952, since the crc and file size in the trailer will be confirmed during operation. The decompressed file size must be specified on the command line for images with decompressed sizes >= 4GiB because the trailer only contains the low 32 bits of the original file size. Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
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由 Eric Nelson 提交于
Initial filesystem images are generally highly compressible. Add a routine gzwrite that allows gzip-compressed images to be written to block devices. Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com> Reviewed-by: NTom Rini <trini@ti.com>
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- 21 4月, 2015 22 次提交
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由 Linus Walleij 提交于
commit aed2fbef "dm: serial: Tidy up the pl01x driver" caused a regression on (real hardware) PL010 by omitting to update the line control register when switching baudrate. Fix this by inlining the missing write to the baud control register. Also renaming the set_line_control() function to pl011_set_line_control() since this function is clearly PL011-specific, and it won't suffice to call that to set up line control. Tested on the Integrator/AP hardware. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Andrey Skvortsov 提交于
two CMD_DNS options were added by commit 60296a83 ("commands: add more command entries in Kconfig") Signed-off-by: NAndrey Skvortsov <andrej.skvortzov@gmail.com> Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Bin Meng 提交于
The name "pch_gbe.%x" exceeds the limit of the name in the 'struct eth_device'. Rename it as just "pch_gbe". Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Michal Simek 提交于
Use phys_addr_t which is used in function prototype in system.h. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Shengzhou Liu 提交于
commit 3c6928fd "net: phy: fix warnings with W=1" caused some PHYs(e.g. CS4315/CS4340) not working. This patch fixes the warning and make those special PHYs working as well. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
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由 Luca Ellero 提交于
This patch adds a support for KSZ8081MNX in MII mode. Signed-off-by: NLuca Ellero <luca.ellero@brickedbrain.com> Acked-by: NPavel Machek <pavel@denx.de>
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由 Tim James 提交于
When accessing PHY registers it is often desirable to only update selected bits, so it is necessary to first read the current value before writing back an modified value with the relevant bits updated. To simplify this and to allow such operations to be incorporated into simple shell scripts propose adding a 'modify' option to the existing mii command, which takes a mask indicating the bits to be updated in addition to a data value containing the new bits, ie, <updated> = (<data> & <mask>) | (<current> & ~<mask>). Signed-off-by: NTim <tim.james@macltd.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Tom Rini <trini@konsulko.com> Cc: Tim <tim.james@macltd.com>
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由 Joe Hershberger 提交于
Update to my corporate email and make the supported filter and aliases more accurate. Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thierry Reding 提交于
Turn ioaddr into an unsigned long rather than a sized 32-bit variable. While at it, fix a couple of pointer to integer cast size mismatch warnings by casting through unsigned long going from pointers to integers and vice versa. Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: NThierry Reding <treding@nvidia.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Codrin Ciubotariu 提交于
Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have interrupts enabled by default. If the interrupt is not treated later by the OS and the PHY's interrupt line is enabled and shared with other interrupts, the system will get an interrupt storm. This patch disables the interrupt for PHY devices that use one of the current Realtek Ethernet PHY drivers. Some of Realtek Ethernet PHYs, such as RTL8211B(L) have the interrupt masked. In this case, the functionality of the PHY should not be afected since this patch brings INER and INSR registers to their default values. Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Scott Wood 提交于
U-Boot on this board grew a long time ago past the 384 KiB that it reserves for the U-Boot image, before the environment. Thus, saveenv overwrites the U-Boot image and bricks the board. I tried to find out when U-Boot grew beyond this point, but there is a long stretch in the history where this board did not build -- and AFAICT when it did fit in 384 KiB, it was missing vital features such as fdt support. Turning off CONFIG_VIDEO was not enough to make it fit. Thus, I don't think we have any choice other than to move the environment. Signed-off-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
CONFIG_PHY_AQ1202 is no longer needed, use CONFIG_PHY_AQUANTIA. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Scott Wood 提交于
U-Boot does not have system calls (the services it exposes to standalone commands use a different mechanism), so the syscall handler is dead code. It's also broken code, as it assumes it is located at 0xc00 -- while even before the patch to stop relocating exception vectors to 0, U-Boot had the syscall at 0x900. The critical and machine check return paths are never called -- the regular exception return path is used instead, which works because xSRR0/1 have already been saved and can be restored via the regular SRR0/1 (we don't care too much in U-Boot about taking a critical/mcheck inside another exception prolog/epilog). Also remove a few other small unused functions. Signed-off-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Scott Wood 提交于
Booke does not require exception vectors to be located at address zero. U-Boot was doing so anyway, simply because that's how it had been done on other PPC. The downside of this is that once the OS is loaded to address zero, the exception vectors have been overwritten -- which makes it difficult to diagnose a crash that happens after that point. The IVOR setup and trap entry code is simplified somewhat as a result. Also, there is no longer a need to align individual exceptions on 0x100 byte boundaries. Signed-off-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
Support SODIMM D3XP12081XL10AA 1866MT/s on T2080RDB. Enable CONFIG_CMD_MEMTEST as well. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
Now cortina driver uses macro CONFIG_SYS_CORTINA_FW_IN_NOR to define that firmware of cortina driver is stored in the nor flash. Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ying Zhang 提交于
The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: NYing Zhang <b40530@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
T2080 rev1.1 also needs erratum a007186. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alexander Graf 提交于
QEMU 2.3 changes the address layout of the CCSR map in the PV ppce500 machine to reside in higher address space. Unfortunately, this exposed a glitch in u-boot for ppce500: While providing a function to dynamically evaluate the CCSR region's position in physical address space, we never used it. Plus we forgot to support 64bit physical addresses. This patch fixes that mishap, making u-boot work fine with latest QEMU again. Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Curt Brune 提交于
According to the MPC8555/MPC8541 reference manual the SS_EN (source synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set during initialization. >From section 9.4.1.8 of that manual: Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, "DDR SDRAM Initialization Sequence," details. 0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously. In addition, Freescale application note AN2805 is also very clear that this bit must be set. This patch reverts a change introduced by commit 457caecd. Testing Done: Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS and inspected the generated assembly code to verify the SS_EN bit was being set. There is one extra instruction emitted: fff9b774: 65 29 80 00 oris r9,r9,32768 Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no additional instructions were emitted related to this patch. Booted an image on a MPC8541 based board successfully. Signed-off-by: NCurt Brune <curt@cumulusnetworks.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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