Make at91 header includes in soft_i2c depend only on CONFIG_AT91FAMILY
rather than individual SoCs.
Signed-off-by: NRyan Mallon <ryan@bluewatersys.com>
Acked-by: Reinhard Meyer<u-boot@emk-elektronik.de>

Linker needs to use the proper endian/bfd flags even when doing partial linking.
LDFLAGS_u-boot sets linker option which is called it when U-boot is built
(u-boot final).
LDFLAGS sets necessary option by partial linking (use in cmd_link_o_target).

CC: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Faraday's ftpmu010 is a power managemnet unit which support cpu
sleep and frequency scaling. It has been integrated into many SoC.

This patch also move ftpmu010 to a proper place for later enhancement.
Signed-off-by: NMacpaul Lin <macpaul@andestech.com>

If we built POST on PPC's that didn't enable CONFIG_SYS_POST_FPU we'd
get the following warning with newer toolchains:

powerpc-linux-gnu-ld: Warning: lib_powerpc/fpu/libpostpowerpcfpu.o
		      uses hard float, libpost.o uses soft float

We actually worked around this sometime ago with the following commit:

commit ce82ff05
Author: Yuri Tikhonov <yur@emcraft.com>
Date:   Sat Dec 20 14:54:21 2008 +0300

   FPU POST: fix warnings when building with 2.18 binutils

However, this only took into effect if CONFIG_SYS_POST_FPU was enabled.
We can simply move the GNU_FPOST_ATTR out of the CONFIG_SYS_POST_FPU
ifdef block to address the issue.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced the following
compiler warnings in the uec ethernet driver:

In file included from /local/home/galak/git/u-boot-85xx/include/miiphy.h:37:0,
                 from uec.c:32:
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:133:0: warning: "LPA_1000FULL" redefined
uec_phy.h:34:0: note: this is the location of the previous definition
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:134:0: warning: "LPA_1000HALF" redefined
uec_phy.h:35:0: note: this is the location of the previous definition
In file included from /local/home/galak/git/u-boot-85xx/include/miiphy.h:37:0,
                 from uec_phy.c:27:
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:133:0: warning: "LPA_1000FULL" redefined
uec_phy.h:34:0: note: this is the location of the previous definition
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:134:0: warning: "LPA_1000HALF" redefined
uec_phy.h:35:0: note: this is the location of the previous definition

Fix them be removing the duplication in the uec code and utlizing the
linux/mii.h version instead.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

ctrl_regs.c: In function 'set_ddr_sdram_mode_2':
ctrl_regs.c:690:6: warning: unused variable 'i'

'i' is only used by DDR3 code.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

.boards.depend was created in the source tree even when calling make
with O=objtree, and distclean O=objtree wouldn't clean it.  Create
.boards.depend in objtree instead as to clean it up properly.
Reported-by: NLoc Minier <loic.minier@linaro.org>
Signed-off-by: NWolfgang Denk <wd@denx.de>

When building with srctree != objtree, the build creates arch/soc/cpu
specific symlinks in the source tree.  This means that the same source
tree can't be used for multiple builds at the same time.  Also, these
symlinks in the source tree are only cleaned up if one passes the same
O= to distclean.

When srctree != objtree, mkconfig creates an $objtree/include2 directory
in the objtree to host the asm -> arch/$arch/include/asm symlink so that
"#include <asm>" can be used.  But it also creates another identical
symlink in $objtree/include.

Then, mkconfig creates two symlinks:
$objtree/include/asm/arch -> arch/$arch/include/asm/arch-$cpu (or $soc)
$objtree/include/asm/proc -> arch/$arch/include/asm/proc-armv (on arm)
but because $objtree/include/asm points at $srctree already, the two
symlinks are created under $srctree.

To fix this, create a real $objtree/include/asm directory, instead of a
symlink.  Update cleanup code accordingly.
Signed-off-by: NLoïc Minier <loic.minier@linaro.org>

Future SoC (like the P1010) replace the LBC controller with the new IFC
(Integrated Flash Controller) so ensure we properly protect code that is
related to the LBC.
Signed-off-by: NDipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

u-boot cannot be compiled after disabling CONFIG_PCI.

Place PCI related codes under #ifdef CONFIG_PCI
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Hwconfig is called before relocating. Use the new hwconfig APIs.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Extend board specific parameters to include cpo, write leveling override
Extend write leveling sample to 0xf
Adding rcw overrid for quad-rank RDIMMs
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM.
Also adding polling after enabling DDR controller to ensure completion.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.

Enable address parity and RCW by default for RDIMMs.

Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.

Use a formula to calculate rodt_on for timing_cfg_5.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch exposes more registers which can be used by the DDR drivers or
interactive debugging. U-boot doesn't use all the registers in DDRC.
When advanced tuning is required, writing to those registers is needed.

Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers
Add options to override rcw, address parity to RDIMMs.
Use array for debug registers.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

ECC can be turned on/off by hwconfig without recompiling. So enable it
by default.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file,
ECC can be turned on/off by this switch. If this switch is omitted, it is ON by
default.

Updated hwconfig calls to use local buffer.

Syntax is
hwconfig=fsl_ddr:ecc=on
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Print a message when a RDIMM is detected.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add new headers that capture common defines for a given SoC/processor
rather than duplicating that information in board config.h and random
other places.

Eventually this should be handled by Kconfig & defconfigs
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NWolfgang Denk <wd@denx.de>

There are several users of the hwconfig APIs (8xxx DDR) before we have
the environment properly setup.  This causes issues because of the
numerous ways the environment might be accessed because of the
non-volatile memory it might be stored in.  Additionally the access
might be so early that memory isn't even properly setup for us.

Towards resolving these issues we provide versions of all the hwconfig
APIs that can be passed in a buffer to parse and leave it to the caller
to determine how to allocate and populate the buffer.

We use the _f naming convention for these new APIs even though they are
perfectly useable after relocation and the environment being ready.

We also now warn if the non-f APIs are called before the environment is
ready to allow users to address the issues.

Finally, we convert the 8xxx DDR code to utilize the new APIs to
hopefully address the issue once and for all.  We have the 8xxx DDR code
create a buffer on the stack and populate it via getenv_f().
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NWolfgang Denk <wd@denx.de>

Add P2040 SoC specific information:
* SERDES Table
* Added p2040 to cpu_type_list and SVR list
* Added number of LAWs for p2040
* Set CONFIG_MAX_CPUS to 4 for p2040
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add P5020 SoC specific information:
* SERDES Table
* LIODN setup
* Portal configuration
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add P3041 SoC specific information:
* SERDES Table
* LIODN setup
* Portal configuration
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The P1014 is similar to the P1010 processor with the following differences:

- 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC)
- no eCAN interface. (P1010 has 2 eCAN interfaces)
- Two SGMII interface (P1010 has 3 SGMII)
- No secure boot
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Key Features include of the P1010:
* e500v2 core frequency operation of 500 to 800 MHz
* Power consumption less than 5.0 W at 800 MHz core speed
* Dual SATA 3 Gbps controllers with integrated PHY
* Dual PCI Express controllers
* Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs)
	* TCP/IP acceleration and classification capabilities
	* IEEE 1588 support
	* Lossless flow control
	* RGMII, SGMII
* DDR3 with support for a 32-bit data interface (40 bits including ECC),
  up to 800 MHz data rate 32/16-bit DDR3 memory controller
* Dedicated security engine featuring trusted boot
* TDM interface
* Dual controller area networks (FlexCAN) controller
* SD/MMC card controller supporting booting from Flash cards
* USB 2.0 host and device controller with an on-chip, high-speed PHY
* Integrated Flash controller (IFC)
* Power Management Controller (PMC)
* Four-channel, general-purpose DMA controller
* I2C controller
* Serial peripheral interface (SPI) controller with master and slave support
* System timers including a periodic interrupt timer, real-time clock,
  software watchdog timer, and four general-purpose timers
* Dual DUARTs
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NDipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET.
It should be as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>

Rather than defining it config.mk we can set it in config.h and remove
config.mk from several boards that don't need it.

We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for
config.h to set.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NWolfgang Denk <wd@denx.de>

This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This allows to change device and host MAC addresses without performing
reset.
Signed-off-by: NVitaly Kuzmichev <vkuzmichev@mvista.com>

Calling eth_bind at usb_eth_init time causes renaming of the network
device from 'usb_ether' to 'usb0'. Fixing this to keep the first name.
Signed-off-by: NVitaly Kuzmichev <vkuzmichev@mvista.com>

Since the ether may not be the only one usb gadget would be used
in the uboot, it is neccessary to do the register each time the
eth begin to work to make usb gadget driver less confussed when
we want to use two different usb gadget at the same time.

Usb gadget driver could simple ignore the register operation, if
it find the driver has been registered already.
Signed-off-by: NLei Wen <leiwen@marvell.com>

Documented is CONFIG_CMD_SHA1, through confusion in the source
CONFIG_CMD_SHA1 and CONFIG_CMD_SHA1SUM has to be used to enable
sha1sum.

Fix both, the documentation and the source, so that only
CONFIG_CMD_SHA1SUM is needed to enable the command sha1sum.
Signed-off-by: NAlexander Holler <holler@ahsoftware.de>

There is not break character between board name and CPU.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

By default, "-" chars are interpreted as hyphens (U+2010) by groff, not
as minus signs (U+002D). Since options to programs use minus signs
(U+002D), this means for example in UTF-8 locales that you cannot cut
and paste options, nor search for them easily.

(Reported by lintian.)
Signed-off-by: NLoc Minier <loic.minier@linaro.org>

Signed-off-by: NLoc Minier <loic.minier@linaro.org>

When a flash partition was positioned at the very top of a 32-bit memory
map (eg located at 0xf8000000 with a size of 0x8000000)
get_part_sector_size_nor() would incorrectly calculate the partition's
ending address to 0x0 due to overflow.  When the overflow occurred
get_part_sector_size_nor() would falsely return a sector size of 0.
A sector size of 0 results in subsequent jffs2 operations failing.

To workaround the overflow subtract 1 from calculated address of
the partition endpoint.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

There's no compelling reason to have the output on bootup or the
"flinfo" command print "flash" in uppercase, so use the proper case
where appropriate.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

The lan91c96_detect_chip routine is not correct according
to the manual.
Signed-off-by: YanJun Yang <yangyj.ee@gmail.com>