- 03 9月, 2015 33 次提交
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由 Sjoerd Simons 提交于
The Radxa Rock pro board is rk3188 based and thus won't work with U-Boot built for RK3288. Change the documentation to refer to the intended board, the Radxa Rock 2, which is an RK3288-based design very similar to the firefly Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a few notes on how to try out the Rockchip support so far. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This builds and displays an SPL message, but does not function beyond that. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The Firefly RK3288 is a suitable target board for initial mainline Rockchip support. It includes a good set of peripherals, a recent SoC and it is readily available. This adds only some basic files required to allow the baord to display a serial message in SPL and hang. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add an I2C driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add an MMC driver which supports RK3288, but may also support other SoCs. It uses the Designware MMC device. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a driver which supports pin multiplexing setup for the most commonly used peripherals. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a driver that provides access to system controllers. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
We can reset the SoC using some CRU (clock/reset unit) registers. Add support for this. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
PMU is the power management unit and GRF is the general register file. Both are heavily used in U-Boot. Add header files with register definitions. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3288. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a full regulator driver for the ACT8846. This provides easy access to voltage and current settings for each regulator. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a driver for the ACT8846 PMIC. This supports several LDOs and BUCKs and is connected to the I2C bus. This driver supports using a regulator driver to access the regulators. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add header files for the peripherals and clocks supported on Rockchip platforms. The particular implementation (and register set) for each is SoC-specific, but it seems that the naming can be generic. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This supports RK3288 at present. It does not implement functions or support for pull up/down. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The Rockchip boot ROM requires a particular file format for booting from SPI. It consists of a 512-byte header encoded with RC4, some padding and then up to 32KB of executable code in 2KB blocks, separated by 2KB empty blocks. Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be converted to this format. This allows booting from SPI flash on supported machines. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The Rockchip boot ROM requires a particular file format. It consists of 64KB of zeroes, a 512-byte header encoded with RC4, and then some executable code. Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be converted to this format. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Rockchip SoCs require certain formats for code that they execute, The simplest format is a 4-byte header at the start of a binary file. Add support for this so that we can create images that the boot ROM understands. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Allow the image handler to store the original input file size so that it can reference it later. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Simon Glass 提交于
At present there is an arbitrary limit of 4KB for padding. Rockchip needs more than that, so remove this restriction. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Simon Glass 提交于
In SPL we need access to the CRU and other peripherals so we can set up SDRAM. Mark these so that they will remain in the device tree. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Bring in required device tree files from Linux. Since mainline Linux is somewhat behind, use the files from the Chromium tree. We can re-sync once further code is acccepted upstream. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add support for the Rockchip serial device using the ns16550 driver. This uses driver model and device tree for both SPL and U-Boot proper. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
There can be only one do_reset(). When CONFIG_RESET is enabled this is provided by the reset uclass, and ARM's version should be disabled. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
All devices should bind without error. But when they don't, they can cause driver model init to fail. A real situation where this can happen is when there is a missing uclass. Add a debug() call to dm_scan_fdt_node to make this easier to track. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
When a uclass definition is missing, no drivers in that uclass can operate. This can happen if a board has a strange collection of options (e.g. the driver is enabled but the uclass is not). Unfortunately this is very confusing at present. Starting up driver model results in a -ENOENT error, which is pretty generic. Quite a big of digging is needed to get to the root cause. To help with this, change the error to a very strange one with no other users in U-Boot. Also add a debug message. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Some SoCs want to adjust the input clock to the DWMMC block as a way of controlling the MMC bus clock. Update the get_mmc_clk() method to support this. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
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由 Simon Glass 提交于
At present SPL does not have its own option. But these features can increase SPL code size. Adjust the Kconfig and Makefile so that separate a SPL option can be selected. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
My original pinctrl patch operating using a peripheral ID enum. This was shared between pinmux and clock and provides an easy way to specify a device that needs to be controlled, even it is does not (yet) have a driver within driver model. Masahiro's new simple pinctrl gets around this by providing a set_state_simple() pinctrl method. By passing a device to that call the peripheral ID becomes unnecessary. If the driver needs it, it can calculate it itself and use it internally. However this does not solve the problem for peripheral clocks. The 'pure' solution would be to pass a driver to the clock uclass also. But this requires that all devices should have a driver, and a struct udevide. Also a key optimisation of the clock uclass is allowing a peripheral clock to be set even when there is no device for that clock. There may be a better way to achive the same goal, but for now it seems expedient to add in peripheral ID to the pinctrl uclass. Two methods are added - one to get the peripheral ID and one to select it. The existing set_state_simple() is effectively the union of these. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The pinctrl Kconfig options should have help messages. Add this to a few options. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 01 9月, 2015 1 次提交
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- 31 8月, 2015 6 次提交
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由 Boris Brezillon 提交于
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Masahiro Yamada 提交于
This should depend on SPL_OF_CONTROL (it is not equivalent to SPL && OF_CONTROL). Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
This driver actually does nothing but test pinctrl uclass, and demonstrate how things work. To try this driver, uncomment /* #define DEBUG */ in the drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be displayed. DRAM: 128 MiB sandbox pinmux: group = 1 (serial_a), function = 1 (serial) Using default environment In: cros-ec-keyb Out: lcd Err: lcd Net: Net Initialization Skipped eth0: eth@10002000, eth1: eth@80000000, eth5: eth@90000000 => i2c dev 0 Setting bus to 0 sandbox pinmux: group = 0 (i2c), function = 0 (i2c) sandbox pinconf: group = 0 (i2c), param = 3, arg = 1 Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
This creates a new framework for handling of pin control devices, i.e. devices that control different aspects of package pins. This uclass handles pinmuxing and pin configuration; pinmuxing controls switching among silicon blocks that share certain physical pins, pin configuration handles electronic properties such as pin- biasing, load capacitance etc. This framework can support the same device tree bindings, but if you do not need full interface support, you can disable some features to reduce memory foot print. Typically around 1.5KB is necessary to include full-featured uclass support on ARM board (CONFIG_PINCTRL + CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX), for example. We are often limited on code size for SPL. Besides, we still have many boards that do not support device tree configuration. The full pinctrl, which requires OF_CONTROL, does not make sense for those boards. So, this framework also has a Do-It-Yourself (let's say simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the uclass itself provides no systematic mechanism for identifying the peripheral device, applying pinctrl settings, etc. They must be done in each low-level driver. In return, you can save much memory footprint and it might be useful especially for SPL. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
This is useful when we want to bind a device, but do not need the pointer to the device. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NSimon Glass <sjg@chromium.org>
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