- 28 4月, 2017 10 次提交
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由 Josua Mayer 提交于
CONFIG_CMD_FS_UUID was neither whitelisted, nor was it declared in Kconfig. Now it can be enabled in .config and defconfig as expected. Signed-off-by: NJosua Mayer <josua.mayer97@gmail.com>
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由 Andrew F. Davis 提交于
Almost all TI defconfigs enable this already, add this as a default and remove the explicit assignment. Signed-off-by: NAndrew F. Davis <afd@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Alexey Brodkin 提交于
Finally adding support for ARC boards in TravisCI. To build for ARC boards we need to install Synopsys prebuilt toolchain which we do here. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdfReported-by: NVishal Mahaveer <vishalm@ti.com> Signed-off-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Philipp Tomsich 提交于
This originally started out as "pinctrl: Kconfig: reorder to keep Rockchip options together" and tried to keep the Rockchip-related config options together. However, we now rewrite all chip-specific driver selections to start with CONFIG_PINCTRL_ (with the inadvertent changes to related Makefiles) and sort those alphabetically. And as this already means touching most of the file, we also reformat the help text to not exceed 80 characters (but make full use of those 80 characters). Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
An assignment (of a value to itself) was left over (after removing and addition from the line) from moving the common padding code into rkcommon_vrec_header. This change removes this to avoid a spurious warning in static code analysis (i.e. Coverity). Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reported-by: Coverity (CID: 161418) Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Alexey Brodkin 提交于
These were reminders that somehow slipped through the cracks or were erroneously introduced after previous clean-ups. Getting rid of then once again. Hopefully for good now :) Where missing and appropriate replace with CONFIG_CMDLINE_EDITING which really enables shell history as of now. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Peter Griffin <peter.griffin@linaro.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Jon Mason <jon.mason@broadcom.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Tom Rini 提交于
There are more and more cases where if we do not use gcc-6.0 or later we run into problems where our binaries are too large for the targets. Given the prevalence of gcc-6.0 or later toolchains at this point in time, we give notice now that starting with v2018.01 we will require gcc-6 (or later) for ARM. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Simon Glass 提交于
Unfortunately a test for the PWM uclass was not included when it was submitted. This was noticed when trying to add more functionality: http://patchwork.ozlabs.org/patch/748172/ Add a simple test to get us started. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Lokesh Vutla 提交于
Standardise U-Boot prompt on all keystone2 platforms instead of platform specific prompt. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 27 4月, 2017 2 次提交
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由 Adam Ford 提交于
The name of the gpio bank under DM_GPIO appear to be a copy-paste error. This changes the name of the gpio bank from am33xx_gpios to omap34xx_gpios. Signed-off-by: NAdam Ford <aford173@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Adam Ford 提交于
The register names and offset were not correct as per the TRM for OMAP3530 and OMAP3630. Correct the naing and offsets per the documentation Signed-off-by: NAdam Ford <aford173@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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- 26 4月, 2017 2 次提交
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- 25 4月, 2017 18 次提交
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由 Alexey Brodkin 提交于
We used to have opencoded ehci_readl()/writel() which required no external functions to be called. Now with attempt to switch to generic readl()/writel() accessors we see a missing declaration of those accessors in ehci-ppc4xx. Something like that happens if applied http://patchwork.ozlabs.org/patch/726714/: ---------------->8--------------- CC drivers/usb/host/ehci-ppc4xx.o drivers/usb/host/ehci-ppc4xx.c: In function 'ehci_hcd_init': drivers/usb/host/ehci-ppc4xx.c:23:3: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration] HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); ^ ---------------->8--------------- Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@konsulko.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Heinrich Schuchardt 提交于
For id = 15 an out of bound access occurs in udc_setup_ep(). Increase the size of epinfo[] from 30 to 32 to encompass ids 0..15. The problem was highlighted by cppcheck. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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由 Heinrich Schuchardt 提交于
We want to check the result of musb_init_controller and not the address were the result is stored. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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由 Dalon Westergreen 提交于
Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: NDalon Westergreen <dwesterg@gmail.com> Reviewed-by: NDinh Nguyen <dinguyen@kernel.org>
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由 Icenowy Zheng 提交于
Only A23/A33 in SUN8I want a default value of CONS_INDEX of 5, for other chips the default value is 1 like other Allwinner SoCs. Fix this default value. The original wrong value has lead to wrong console on H3 Orange Pi boards. Fixes: 7095f864 ("sunxi: Convert CONS_INDEX to Kconfig") Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 York Sun 提交于
Commit 088454cd dropped return value from initram(), setting gd->ram_size directly. Three boards were missed for SPL boot. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 Yuantian Tang 提交于
PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: NChenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: NTang Yuantian <andy.tang@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Sumit Garg 提交于
Signed-off-by: NSumit Garg <sumit.garg@nxp.com> Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com> Tested-by: NVinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Sumit Garg 提交于
Signed-off-by: NSumit Garg <sumit.garg@nxp.com> Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com> Tested-by: NVinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Sumit Garg 提交于
Add Kconfig option to support loading PPA header from eMMC/SD and NAND Flash. Signed-off-by: NSumit Garg <sumit.garg@nxp.com> Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com> Tested-by: NVinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Hou Zhiqiang 提交于
The PPA is a EL3 firmware, which support PSCI, hotplug, power-management features etc. Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Hou Zhiqiang 提交于
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Hou Zhiqiang 提交于
The PPA is a EL3 firmware, which support PSCI, hotplug, power-management features etc. Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Santan Kumar 提交于
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com> Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 24 4月, 2017 2 次提交
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由 Alison Wang 提交于
Since commit ce412b79, RGMII TX clock internal delay is not enabled for AR8033 unconditionally. On LS1021ATWR board, the third port eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to be enabled. This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX clock internal delay for AR8033 on the third port. Signed-off-by: NAlison Wang <alison.wang@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Andreas Färber 提交于
Currently $fdtfile is constructed from CONFIG_DEFAULT_TREE, containing the filename. However on arm64 that file is located in an allwinner subdirectory. To avoid the need for users/distros symlinking the .dtb files, prepend the vendor directory for ARM64. This aligns Pine64 with other boards such as Raspberry Pi 3. Signed-off-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NJagan Teki <jagan@openedev.com>
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- 21 4月, 2017 5 次提交
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由 Kyle Edwards 提交于
Before this patch, CONFIG_SYS_BOOTPARAMS_LEN was the same size as CONFIG_SYS_MALLOC_LEN. So, if malloc() had previously been called, and initr_malloc_bootparams() was called, it would fail with an out-of- memory error. This patch fixes this issue by expanding the malloc pool to 256KB. Signed-off-by: NKyle Edwards <kyleedwardsny@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Kyle Edwards 提交于
This fixes an issue with the saveenv command causing U-Boot to no longer work on the QEMU Mips pseudoboard. Because the offset of the environment was being determined by CONFIG_SYS_MONITOR_LEN, and this value was less than the actual size of U-Boot, saveenv was overwriting parts of the U-Boot code. Because CONFIG_SYS_MONITOR_LEN is no longer used on MIPS, this patch removes it and places the environment at the end of the pseudoboard's 4MB flash. Signed-off-by: NKyle Edwards <kyleedwardsny@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Icenowy Zheng 提交于
Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Icenowy Zheng 提交于
As we have now V3s support in board code, the V3s DTSI file should also be added. Add also some CCU include headers to satisfy the DTSI file. Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Icenowy Zheng 提交于
Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NJagan Teki <jagan@openedev.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 20 4月, 2017 1 次提交
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由 Masahiro Yamada 提交于
- Use - instead of @ for OPP tables - Add input-delay properties to Cadence eMMC nodes - Restore full license text because code-diff is annoying - Fix NAND compatible strings Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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