The file fsl_secure_boot.h must be included in config file for
Secure Boot. This is not required to be protected by any macro.
CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be
turned on.

The above was missing in some config files and all files have been
made uniform in this respect.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Current code compares the return pointer of function
qbman_cena_write_start with NULL. Instead the value of the return
pointer should be compared.
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Freescale's management complex (MC) uses System DDR for internal usage.
Increase used System DDR size from 256MB to 512 MB.
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Freescale's LS2040A is a another personality of LS2080A SoC
without AIOP support consisting of 4 armv8 cores.
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

LS2080A has support for 8 DPMAC ports out of which
only 5 ports can be used at a time.
Enabling all 8 DPMAC ports of LS2080A personality.
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Some images to be validated are relocated to a dynamic
address at run time. So, these addresses cannot be known
befor hand while signing the images and creating the header
offline.
So, support is required to pass the image address to the
validate function as an argument.
If an address is provided to the function, the address
field in Header is not read and is treated as a reserved
field.
Signed-off-by: NSaksham Jain <saksham@freescale.com>
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The code for image hash calculation, hash calculation from
RSA signature and comparison of hashes has been mobed to a
separate function.
Signed-off-by: NSaksham Jain <saksham@freescale.com>
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Separate functions are created for reading and checking the
sanity of Public keys:
- read_validate_single_key
- read_validate_ie_tbl
- read_validate_srk_table
Signed-off-by: NSaksham Jain <saksham@freescale.com>
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The prototype and defination of function fsl_secboot_validate
has been changed to support calling this function from another
function within u-boot.
Only two aruments needed:
1) header address - Mandatory
2) SHA256 string - optional
Signed-off-by: NSaksham Jain <saksham@freescale.com>
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Following commit 61bd2f75, exclude unused DDR controller from
calculating RAM size for SPL boot.
Signed-off-by: NEd Swarthout <Ed.Swarthout@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Fixes lsch2 SerDes registers define according to LS1043A RM Rev D.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Updated the default sata register values to enhance the
performance and stability.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.

When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

SYSCLK frequency is dependent on on-board switch settings. It may
vary as per requirement. boot-loader is aware of board switch
configurations.

So Fixup Linux device tree from boot-loader.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
CC: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

1.Use "qixis_reset sd" to boot from SD
2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support
3.Use "qixis_reset qspi" to boot from QSPI flash

On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be
pin-multiplexed. So the switches are different between SD boot with
IFC support and SD boot with QSPI support. The default booting from
SD is with IFC support.

Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS.
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch also exposes the complete DDR region(s) to Linux.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.

Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Use wildcard to clean arch subdirectories, as it is cleaner than
listing all the arch which builds dtb.
Signed-off-by: NThomas Chou <thomas@wytron.com.tw>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

GPIO, I2C, LCD and HDMI are now implemented. We have more than one PMIC.
There is an implementation to run the CPU at full speed although it does
not seem to make much difference.

Update the README to cover recent developments.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This board includes an RK3288 SoC on a SOM. It can be mounted on a
base-board which provides a wide range of peripherals.

So far this is verified to boot to a prompt from a microSD card. The serial
console works as well as HDMI.

Thanks to Tom Cubie for sending me a board.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add the required pre-relocation tags and SDRAM init information for U-Boot.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Bring in the current device tree files for rock2 from linux/next commit
719d6c1. Hopefully this is the latest one.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This has been added and we have references to it in the rock2 board. Add
this node.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Enable HDMI output and a console on firefly.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Enable these devices using the VOPL video output device. We explicitly
disable VOPB in the device tree to avoid it taking over. Since this device
has an LCD display this comes up by default. If the display fails for some
reason then it will attempt to use HDMI. It is possible to force it to fail
(and thus fall back to HDMI) by puting 'return -EPERM' at the top of
rk_edp_probe(). For now there is no easy way to select between the two.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add the 'time' and 'sf test' commands so that we can test SPI flash
performance.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).
Signed-off-by: NSimon Glass <sjg@chromium.org>

Since the device tree does not specify the EDID pinctrl option for HDMI we
must set it manually. Fix the driver to handle this.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Fix a number of small errors which were found in reviewing the clock code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

There is a minor error in the SDRAM timing. It does not seem to affect
anything so far. Fix it just in case.
Signed-off-by: NSimon Glass <sjg@chromium.org>

When the board does not use MMC SPL this code is a waste of space. Drop it.
Signed-off-by: NSimon Glass <sjg@chromium.org>

These work reasonable well, but there are a few errors:

- Brackets should be used to avoid unexpected side-effects
- When setting bits, the corresponding upper 16 bits should be set also
Signed-off-by: NSimon Glass <sjg@chromium.org>

This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Fix spaces in two comments in this file.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Now that we have a pretty good GPIO driver, enable the 'gpio' command on all
rockchip boards.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This script has proved useful for parsing datasheets and creating register
shift/mask values for use in header files. Include it in case it is useful
for others.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a command that displays the PLLs and their current rate.
Signed-off-by: NSimon Glass <sjg@chromium.org>