This causes widespread breakage due to the operation of the low-level code
in crt0.S and cro0_64.S for ARM at least.

The fix is not complicated but it seems safer to revert this for now.

This reverts commit 2afddae0.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This patch enabled the MVEBU PCIe support on the db-88f6820-gp A38x
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>

This patch enabled the MVEBU PCIe support on the db-mv784mp-gp AXP
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.

Besides the driver, this patch also removes the statically defined
PCI MBUS windows. As they are not needed anymore, since this PCIe
driver now creates the windows dynamically.

Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000
PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp
eval board using this Intel E1000 PCIe card in the PCIe 0 slot.

This port was done in cooperation with Anton Schubert.
Signed-off-by: NAnton Schubert <anton.schubert@gmx.de>
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>

This patch introduces the SDRAM scrubbing for ECC enabled board
to fill/initialize the ECC bytes. This is done via the XOR engine
to speed up the process. The scrubbing is a 2-stage process:

1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot
2) U-Boot scrubs the remaining SDRAM area(s)
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Rework these functions so that dram_init_banksize() does not call
dram_init() again. It only needs to set the banksize values in the
bdinfo struct.

Make sure to also clip the size of the last bank if it exceeds the
maximum allowed value of 3 GiB (0xc000.0000). Otherwise other
address windows (e.g. PCIe) will overlap with this memory window.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch moves CONFIG_SYS_TEXT_BASE to 0x00800000 for all Armada
XP / 38x boards in mainline U-Boot. This is done in preparation for
the ECC SDRAM scrubbing that needs to be done in the main U-Boot.
The SPL (previously bin_hdr) has already scrubbed the area:
  0x0000.0000 - 0x0100.0000

In this area this main U-Boot needs to get loaded. The main U-Boot
then can scrub the remaining SDRAM area while running from this
location.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch adds "(ECC enabled)" or "(ECC disabled)" to the DRAM
bootup text. Making it easier for board with SPD DIMM's to see,
if ECC is enabled or not.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch adds support for multiple hostcontrollers to the ehci-marvell driver
and enables all 3 usb-hcs on the db-mv784mp-gp board.

It depends on the initial Armada XP usb support patch from Stefan.
Signed-off-by: NAnton Schubert <anton.schubert@gmx.de>
Reviewed-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch enabled the USB/EHCI support for the Marvell
DB-MV784MP-GP Armada XP eval board.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch enables the USB EHCI support for the Marvell Armada XP (AXP)
SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure
the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done
this already in the bin_hdr (SPL U-Boot). Without this, accessing the
controller registers in U-Boot or Linux will hang the CPU.

Additionally, the AXP uses a different USB EHCI base address. This
patch also takes care of this by runtime SoC detection in the Marvell
EHCI driver.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NAnton Schubert <anton.schubert@gmx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch enables the NAND controller on the Armada XP/38x and provides
a new function that returns the NAND controller input clock. This
function will be used by the MVEBU NAND driver.

As part of this patch, the multiple BIT macro definitions are moved
to a common place in soc.h.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Only with disabled MMU its possible to switch the base register address
on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also
not accessible, as its still locked to cache.

So to fully release / unlock this area from cache, we need to first
flush all caches, then disable the MMU and disable the L2 cache.

On Armada XP this does not seem to be needed. Even worse, with this
code added, I sometimes see strange input charactes loss from the
console.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

With this patch, the MBUS bridge registers (base and size) are
configured upon each call to mbus_dt_setup_win(). This is needed, since
the board code can also call this function in later boot stages. As
done in the maxbcm board.

This is needed to fix a problem with the secondary CPU's not booting
in Linux on AXP.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch changes the MBUS base addresses and sizes to use more
generic names and also adds defines for the sizes. It also moves
the base address to higher addresses.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Signed-off-by: NStefan Roese <sr@denx.de>

This is tested on the DB-MV784MP-GP eval board. To really enable ECC
support on this board the I2C EEPROM needs to get changed. As it
saves the enabling of ECC support internally. For this the following
commands can be used to enable ECC support on this board:

Its recommended for first save (print) the value(s) in this EEPROM
address:

=> i2c md 4e 0.1 2
0000: 05 00    ..

To enable ECC support you need to set bit 1 in the 2nd byte:

Marvell>> i2c mw 4e 1.1 02
Marvell>> i2c md 4e 0.1 2
0000: 05 02    ..

To disable ECC support again, please use this command:

Marvell>> i2c mw 4e 1.1 00
Marvell>> i2c md 4e 0.1 2
0000: 05 00    ..

On other AXP boards, simply plugging an ECC DIMM should be enough to
enable ECC support.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

CONFIG_SYS_BOARD_DRAM_INIT is not defined anywhere. So lets get rid
of all references here.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_write" when parameters alen = 0 and len = 0.
Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com>

Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_read" when parameters alen != 0 and len = 0.
Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com>

The HCLK is not constant and can take different value; use the api function to get the value of the HCLK for the I2C clock high and low computation.
Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com>

Add LPC32xx GPIO interface macro for pin mapping.
Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com>

Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset).

To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done.
Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com>

Add missing registers in struct definition.
Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011).
Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Also update maintainer info.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

Also update maintainer info.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: York Sun <yorksun@freescale.com>

Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

The default boot command searches for dofastboot varaiable
and does a fastboot if it is set to 1.
But the condition "if test ${dofastboot} -eq 1" always
returns true if dofastboot is not defined and breaking mmc boot.
So make dofastboot as 0 by default and let the runtime
environment set it if fastboot is required.
Reported-by: NYan Liu <yan-liu@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

This reverts commit 5b344360.

This function has a few problems. It calls fdt_parent_offset() which as
mentioned in code review is very slow.

https://patchwork.ozlabs.org/patch/499482/
https://patchwork.ozlabs.org/patch/452604/

It also happens to break SPI flash on Minnowboard max which is how I noticed
that this was applied. I can send a patch to tidy that up, but in any case
I think we should consider a revert until the function is better implemented.
Signed-off-by: NSimon Glass <sjg@chromium.org>