* rename board directory to eb_cpu5282
* rename EB+MCF-EV123_.*config to eb_cpu5282_.*config
* add Maintainer for EB+CPU5282 board
* rename prompt
Signed-off-by: NJens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>

When CONFIG_ZERO_BOOTDELAY_CHECK is not defined, bootdelay==0
prevents the check for console input (as stated in README.autoboot).
This must also work in CONFIG_AUTOBOOT_KEYED mode.
Signed-off-by: NDirk Eibach <eibach@gdsys.de>

Add support for specifying a differnt CPU for main u-boot and SPL
u-boot builds.  This is done by adding an optional SPL CPU after the
main CPU in boards.cfg as follows:

     normal_cpu:spl_cpu

This this case CPU will be set to "normal_cpu" during the main u-boot
build and "spl_cpu" during the SPL build.
Signed-off-by: NAllen Martin <amartin@nvidia.com>

CONFIG_DISCOVER_PHY is not used anywhere, so remove it from config files.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: NTimo Ketola <timo@exertus.fi>

Prototype declaration of I/O operation functions are not correct. as both
'extern' and function definition are at same place.

Chage protoype declaration as static.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>

Return type of in_8, in_be16 and in_le16 should not be'int'. Update it to type
u8/u16/u32.
Although 'unsigned' for in_be32 and in_le32 is correct. But to make return type
uniform across the file changed to u32

Similarly, parameter passed to out_8, out_be16, out_le16 ,out_be32 & out_le32
should not be 'int'.Change it to type u8/u16/u32.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>

In addition to the error message also display the error code. I had the
problem that my malloc memory was not enough (ENOMEM), and if u-boot
had displayed the error code immediately that would have saved me some
debugging.
Signed-off-by: NBernhard Walle <walle@corscience.de>

Use ubifs_err instead of printf.
Add "errno=%d" in output as suggested by Albert Aribaud.
Signed-off-by: NThomas Weber <weber@corscience.de>

Since run_command() and run_command_list() are important and a little
confusing, add some basic tests to check that the behaviour is correct.

Note: I am not sure that this should be committed, nor where it should go
in the source tree. Comments welcome.

To run the unit tests use the ut_cmd command available in sandbox:

make sandbox_config
make
./u-boot -c ut_cmd

(To test both hush and built-in parsers, you need to manually change
CONFIG_SYS_HUSH_PARSER in include/configs/sandbox.h and build/run again)
Signed-off-by: NSimon Glass <sjg@chromium.org>

Any environment variable can hold commands to be executed by the 'run'
command. The environment variables preboot, bootcmd and menucmd have
special code for triggering execution in certain circumstances.

We adjust these calls to use run_command_list() instead of run_command().
This change permits these variables to have embedded newlines so that
they work the same as the 'source' command.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This new function runs a list of commands separated by semicolon or newline.
We move this out of cmd_source so that it can be used by other code. The
PXE code also uses the new function.
Suggested-by: NMichael Walle <michael@walle.cc>
Signed-off-by: NSimon Glass <sjg@chromium.org>

In file included from arch/arm/lib/board.c:43:0:
include/malloc.h:490:5: warning: "HAVE_MMAP" is not defined [-Wundef]
include/malloc.h:590:5: warning: "HAVE_USR_INCLUDE_MALLOC_H" is not defined [-Wundef]
include/malloc.h:757:5: warning: "HAVE_MMAP" is not defined [-Wundef]
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>

All the global flag defines are the same across all arches.  So unify them
in one place, and add a simple way for arches to extend for their needs.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

If we build everything correctly with multiple builds, and an
ERR directory had been previously created, we failed to report
that everything was fine because grep failed to find anything
in the ERR directory. Use grep -r, which doesn't complain if
there are no input files.
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Tested-by: NTom Rini <trini@ti.com>

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
  powerpc/mpc85xx: Ignore E bit for BSC9130/1
  powerpc/sgmii: To support PHY link state auto detect in SGMII mode
  powerpc/85xx: improve definition of BR_PHYS_ADDR macro
  powerpc/p2041: configure the CPLD lane_mux according to RCW
  powerpc/ddr: fix fsl_ddr_get_dimm_params compile error
  powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is defined
  powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB
  powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
  powerpc/p1022ds: add support for SPI and SD boot
Signed-off-by: NWolfgang Denk <wd@denx.de>

The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows
which PCI device tree node to look for.  The calls to these macros are using a hard-coded string,
but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we
should use that.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Commit 48f6a5c3 removed E bit. BSC9130/1 were left out due to patch apply
timing. Remove them now.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

PHYs on SGMII riser card are used in SGMII mode with different external
IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type
under ethernet node should be updated. Otherwise the PHY interrupt can not
be handled therefor PHY link state change can not be auto detected.

For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed
but it's still be kept to guarantee the sgmii mode could work with old
device tree.
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NJia Hongtao <B38951@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro
definition, so callers had to supply their own parenthesis.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
is 0xc, CPLD supports SATA by default, we should re-configure the lane
muxing according to RCW, which indicates what SerDes protocol it is running.

Default lane muxing map is as below:
Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
and bit 3 respectively.

Default value of these bits for lane muxing is '1', we should set or clear
these bits accoring to RCW.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

fsl_ddr_get_dimm_params() should be wrapped by
CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of
using SPD, it will cause compile error.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

ENV location compile logic is wrong, and when CONFIG_SYS_NO_FLASH is defined
and non-NOR u-boot is building, it will cause compile error. Also, add
CONFIG_SYS_FLASH_USE_BUFFER_WRITE for p2041, which will improve NOR flash
write performance.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation. Early commit eb672e92
works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

In order for indirect mode on the PIXIS to work properly, both chip selects
need to be set to GPCM mode, otherwise writes to the chip select base
addresses will not actually post to the local bus -- they'll go to the
NAND controller instead.  Therefore, we need to set BR0 and BR1 to GPCM
mode before switching to indirect mode.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.

Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.

Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.
Signed-off-by: NMatthew McClintock <msm@freescale.com>
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NJiang Yutang <b14898@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Renesas SH and R-Mobile set up device using PFC.
This provide the framework. Most codes were brought from linux kernel.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

The serial device of R8A7740 has the same structure as SH7372 of SH, etc.
Signed-off-by: NHideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

The serial device of SH73A0 has the same structure as SH7372 of SH, etc.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Even if using CPU is SH-4A, the previous code always put "SH4".
This patch fixes it.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

* 'master' of git://git.denx.de/u-boot-onenand:
  env_onenand: set ONENAND_MAX_ENV_SIZE to CONFIG_ENV_SIZE
Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NHolger Brunck <holger.brunck@keymile.com>
cc: Heiko Schocher <hs@denx.de>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Acked-by: NHeiko Schocher <hs@denx.de>

The patch "spi: tegra2: rename tegra2_spi.* to tegra_spi.*"
(sha1: edffa63d)
renamed tegra2_spi.c to tegra_spi.c

and the patch "Merge branch 'master' of git://git.denx.de/u-boot-microblaze"
(sha1: d978780b)

has wrongly resolved confict.

This patch fix it.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

The above warning was introduced originally in 436da3cd "ext2load:
increase read speed" and fixed for newer toolchains in b8032734 "ext2fs:
fix warning: 'blocknxt' may be used uninitialized".  This change did not
fix the warning with gcc 4.2, as found in ELDK 4.2.

If we rework the while loop to initalize blocknxt before entering the
warning really goes away.  Tested on am335x with an approx 7mb file and
crc32 in U-Boot befor and after this change.

Cc: Wolfgang Denk <wd@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Jason Cooper <u-boot@lakedaemon.net>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: NTom Rini <trini@ti.com>

This fix prevents env_import() CRC to fail when CONFIG_ENV_SIZE
is not equal to 4096 bytes
It also prevents mtd->read and mtd->write to be incomplete when
the environment is larger than 4096 bytes.
Signed-off-by: NDavid du Colombier <0intro@gmail.com>

The HW guys suggested to change these two values. And these values are
now identical to the values we use on mgcoge.

PSDMR_WRC was set to 1C as it should lead to better performance.
Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: NHolger Brunck <holger.brunck@keymile.com>

mgcoge2ne was an intermediate step towards mgcoge3ne. One difference is the
smaller SDRAM on mgcoge2ne (128MB). To support both boards with the same
u-boot we use here the SDRAM detection.

This patch enables SDRAM detection between 256MB and 128MB.
So in addition to the existing 256MB geometry:
     4 chips x 8M (13 rows, 10 cols) x 16 bit x 4 banks
we can now also have 128MB geometry:
     4 chips x 4M (13 rows,  9 cols) x 16 bit x 4 banks
Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>

This patch adds SDRAM detection feature to km82xx boards.
To enable this feature, define CONFIG_SYS_SDRAM_LIST as the initializer
for an array of struct sdram_conf_s.
These structs will expose the bitfields within registers PSDMR and OR1 which
have to be different between configurations; common bitfields will be
defined, as usual, within CONFIG_SYS_PSDMR and CONFIG_SYS_OR1.
If CONFIG_SYS_SDRAM_LIST is not defined, then the usual behavior is retained.
Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>

The only file including km82xx-common.h is km82xx.h.
So there is no need to have it as a separate file.
Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>

Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need
to keep them as separate .h config files.
Therefore, make mgcoge3ne.h and mgcoge.h converge into a single km82xx.h
file.
Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>

Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>