- 19 8月, 2015 8 次提交
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由 Vladimir Zapolskiy 提交于
LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit wide. This means that if HCLK is 104MHz, then minimal configurable I2C clock speed is about 51KHz. Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in assumption that peripheral clock is 13MHz it allows to set the minimal bus speed about 25.5KHz. Check for negative half clock value is removed since it is always false. The change fixes the following problem for I2C busses 0 and 1: => i2c dev 0 Setting bus to 0 => i2c speed 100000 Setting bus speed to 100000 Hz Failure changing bus speed (-22) Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Tested-by: NSylvain Lemieux <slemieux@tycoint.com>
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由 Vladimir Zapolskiy 提交于
The change adds a number of macro definitions used by USB OHCI driver, if CONFIG_USB_OHCI_LPC32XX is selected from a board config file. Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Tested-by: NSylvain Lemieux <slemieux@tycoint.com>
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由 Sylvain Lemieux 提交于
Incorporate USB driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx USB driver - lpc3250 header file USB registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com> Acked-by: NMarek Vasut <marex@denx.de> Tested-by: NVladimir Zapolskiy <vz@mleia.com>
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由 Sylvain Lemieux 提交于
Updated the LPC32xx I2C driver to support the OTG I2C that is part of the USB module. Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Sylvain Lemieux 提交于
Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (ECC layout for small page) This layout is matching the lpc32xx NAND SLC Linux Kernel driver. Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com>
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由 Sylvain Lemieux 提交于
Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (hardware ECC support) - lpc3250 header file missing SLC NAND registers definition The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver. Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com> Tested-by: NVladimir Zapolskiy <vz@mleia.com>
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由 Vladimir Zapolskiy 提交于
A number of LPC32xx SLC NAND defines is dictated by controller hardware limits and OOB layout is defined by operating system, the definitions are common for all users. Since those macro are used in out of NAND SLC driver code (simple NAND SPL framework), they can not be placed into the driver, therefore move them from board config files to arch/config.h The change also adds OOB layout details specific to small page NAND devices taken from Linux kernel. Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Tested-by: NSylvain Lemieux <slemieux@tycoint.com>
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由 Sylvain Lemieux 提交于
Incorporate DMA driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx DMA driver - lpc3250 header file DMA registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com> Acked-by: NMarek Vasut <marex@denx.de> Tested-by: NVladimir Zapolskiy <vz@mleia.com>
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- 18 8月, 2015 32 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Simon Glass 提交于
This causes widespread breakage due to the operation of the low-level code in crt0.S and cro0_64.S for ARM at least. The fix is not complicated but it seems safer to revert this for now. This reverts commit 2afddae0. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Vignesh R 提交于
Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With DMA enabled there is almost 3x improvement in read performance. This helps in reducing boot time in qspiboot mode Also add EDMA3 base address for DRA7XX and AM57XX. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Tom Rini 提交于
When doing a memory mapped copy we may have DMA available and thus need to have this copy abstracted so that the driver can do it, rather than a simple memcpy. Signed-off-by: NTom Rini <trini@ti.com> Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Kishon Vijay Abraham I 提交于
Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Kishon Vijay Abraham I 提交于
Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Ravi Babu 提交于
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read. Signed-off-by: NRavi Babu <ravibabu@ti.com> Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Tested-by: NJagan Teki <jteki@openedev.com>
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由 Ravi Babu 提交于
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read. Signed-off-by: NRavi Babu <ravibabu@ti.com> Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Tested-by: NJagan Teki <jteki@openedev.com>
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由 vishalm@ti.com 提交于
Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag, instead of platform. Signed-off-by: NVishal Mahaveer <vishalm@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Stefan Roese 提交于
This patch enabled the MVEBU PCIe support on the db-88f6820-gp A38x eval board. It also enabled the Intel E1000 driver support and adds the initialization of PCIe network controllers to the board code. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
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由 Stefan Roese 提交于
This patch enabled the MVEBU PCIe support on the db-mv784mp-gp AXP eval board. It also enabled the Intel E1000 driver support and adds the initialization of PCIe network controllers to the board code. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Anton Schubert 提交于
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs. Besides the driver, this patch also removes the statically defined PCI MBUS windows. As they are not needed anymore, since this PCIe driver now creates the windows dynamically. Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000 PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp eval board using this Intel E1000 PCIe card in the PCIe 0 slot. This port was done in cooperation with Anton Schubert. Signed-off-by: NAnton Schubert <anton.schubert@gmx.de> Signed-off-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
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由 Stefan Roese 提交于
This patch introduces the SDRAM scrubbing for ECC enabled board to fill/initialize the ECC bytes. This is done via the XOR engine to speed up the process. The scrubbing is a 2-stage process: 1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot 2) U-Boot scrubs the remaining SDRAM area(s) Signed-off-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
Rework these functions so that dram_init_banksize() does not call dram_init() again. It only needs to set the banksize values in the bdinfo struct. Make sure to also clip the size of the last bank if it exceeds the maximum allowed value of 3 GiB (0xc000.0000). Otherwise other address windows (e.g. PCIe) will overlap with this memory window. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
This patch moves CONFIG_SYS_TEXT_BASE to 0x00800000 for all Armada XP / 38x boards in mainline U-Boot. This is done in preparation for the ECC SDRAM scrubbing that needs to be done in the main U-Boot. The SPL (previously bin_hdr) has already scrubbed the area: 0x0000.0000 - 0x0100.0000 In this area this main U-Boot needs to get loaded. The main U-Boot then can scrub the remaining SDRAM area while running from this location. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
This patch adds "(ECC enabled)" or "(ECC disabled)" to the DRAM bootup text. Making it easier for board with SPD DIMM's to see, if ECC is enabled or not. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Anton Schubert 提交于
This patch adds support for multiple hostcontrollers to the ehci-marvell driver and enables all 3 usb-hcs on the db-mv784mp-gp board. It depends on the initial Armada XP usb support patch from Stefan. Signed-off-by: NAnton Schubert <anton.schubert@gmx.de> Reviewed-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
This patch enabled the USB/EHCI support for the Marvell DB-MV784MP-GP Armada XP eval board. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
This patch enables the USB EHCI support for the Marvell Armada XP (AXP) SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done this already in the bin_hdr (SPL U-Boot). Without this, accessing the controller registers in U-Boot or Linux will hang the CPU. Additionally, the AXP uses a different USB EHCI base address. This patch also takes care of this by runtime SoC detection in the Marvell EHCI driver. Signed-off-by: NStefan Roese <sr@denx.de> Signed-off-by: NAnton Schubert <anton.schubert@gmx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
This patch enables the NAND controller on the Armada XP/38x and provides a new function that returns the NAND controller input clock. This function will be used by the MVEBU NAND driver. As part of this patch, the multiple BIT macro definitions are moved to a common place in soc.h. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
Accessing MBUS windows not backed-up by e.g. PCIe devices will hang the SoC. Disable MBUS error propagation back to CPU allows to read 0xffffffff instead of hanging the SoC. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
Only with disabled MMU its possible to switch the base register address on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not accessible, as its still locked to cache. So to fully release / unlock this area from cache, we need to first flush all caches, then disable the MMU and disable the L2 cache. On Armada XP this does not seem to be needed. Even worse, with this code added, I sometimes see strange input charactes loss from the console. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
With this patch, the MBUS bridge registers (base and size) are configured upon each call to mbus_dt_setup_win(). This is needed, since the board code can also call this function in later boot stages. As done in the maxbcm board. This is needed to fix a problem with the secondary CPU's not booting in Linux on AXP. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
This patch changes the MBUS base addresses and sizes to use more generic names and also adds defines for the sizes. It also moves the base address to higher addresses. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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