- According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271),
   -- Timer Value Register @ TIMER Base + 4 is Read-only.
   -- Prescale Value (Bits 3-2 of TIMER Control register)
	can only be one of 00,01,10. 11 is undefined.
   -- CFG_HZ for Versatile board is set to
	#define CFG_HZ		(1000000 / 256)
	So Prescale bits is set to indicate
	- 8 Stages of Prescale, Clock divided by 256
 - The Timer Control Register has one Undefined/Shouldn't Use Bit
   So we should do read/modify/write Operation
Signed-off-by: NGururaja Hebbar <gururajakr@sanyo.co.in>

ARM DaVinci: Removed redundant NAND initialization code.
Signed-off-by: NHugo Villeneuve <hugo.villeneuve@lyrtech.com>

ARM DaVinci: Fix compilation error with new MTD code.
Signed-off-by: NHugo Villeneuve <hugo.villeneuve@lyrtech.com>

During recent PCI-E tests it has been found that current
driverl level and de-emphasis values are not set correctly.
After sweeping throgh all de-ephasis values, it was found that
0x130 is a right value. Where 0x13 is driver level and 0 is
de-emphasis.
Signed-off-by: NTirumala R Marri <tmarri@amcc.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes some minor issues introduced with the patch:
ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika:

- Rework memory-queue and PLB arbiter optimization code, that the
  local variable is not needed anymore. This removes one #ifdef.
- Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead
  of XXX+ 0x01). This was not introduced by Prodyut, just a
  copy-paste problem.
Signed-off-by: NStefan Roese <sr@denx.de>

	PPC405EX and PPC460EX/GT/SX

- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
  processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
  across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
  processors
- Add register bit definitions for Memory Queue Configuration registers
Signed-off-by: NProdyut Hazarika <phazarika@amcc.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Move to using the environment variables 'ethaddr', 'eth1addr', etc..
instead of bd->bi_enetaddr, bi_enet1addr, etc.

This makes the code a bit more flexible to the number of ethernet
interfaces.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Tested with TQM5200S on STK52XX.200 Board
Signed-off-by: NAxel Beierlein <belatronix@web.de>

There is no point in disabling the icache on 7xx/74xx/86xx parts and not
also flushing the icache.  All callers of invalidate_l1_instruction_cache()
call icache_disable() right after.  Make it so icache_disable() calls
invalidate_l1_instruction_cache() for us.

Also, dcache_disable() already calls dcache_flush() so there is no point
in the explicit calls of dcache_flush().
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Incorrect CFG_HZ value, change 1000000 to 1000.
Rename #waring to #warning. RAMBAR1 uses twice
in start.S, rename the later to FLASHBAR. Insert
nop for DRAM setup. And, env_offset in linker file.
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NScott Wood <scottwood@freescale.com>

rename CFG_NAND_LEGACY to CONFIG_NAND_LEGACY
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Note that with older board revisions, NAND boot may only work after a
power-on reset, and not after a warm reset.  I don't have a newer board
to test on; if you have a board with a 33MHz crystal, please let me know
if it works after a warm reset.
Signed-off-by: NScott Wood <scottwood@freescale.com>

Here comes a trivial patch to cpu/arm926ejs/davinci/nand.c. Unfortunately I
don't have hardware handy so I can not test it at the moment but changes are
rather trivial so it should work. It would be nice if somebody with a
hardware checked it anyways.
Signed-off-by: NSergey Kubushyn <ksi@koi8.net>

This patch changes the 4xx NAND driver ndfc.c to match the new
infrastructure from the updated NAND subsystem. This NAND
subsystem was recently synced again with the Linux 2.6.22 MTD/NAND
subsystem.

Tested successfully on AMCC Sequoia and Bamboo.
Signed-off-by: NStefan Roese <sr@denx.de>

 - Fixing leading white spaces
 - Fixing indentation where 4 spaces are used instead of tab
 - Removing C++ comments (//), wherever I introduced them
Signed-off-by: NWilliam Juul <william.juul@tandberg.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Signed-off-by: NWilliam Juul <william.juul@tandberg.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

A lot changed in the Linux MTD code, since it was last ported from
Linux to U-Boot. This patch takes U-Boot NAND support to the level
of Linux 2.6.22.1 and will enable support for very large NAND devices
(4KB pages) and ease the compatibility between U-Boot and Linux
filesystems.

This patch is tested on two custom boards with PPC and ARM
processors running YAFFS in U-Boot and Linux using gcc-4.1.2
cross compilers.

MAKEALL ppc/arm has some issues:
 * DOC/OneNand/nand_spl is not building (I have not tried porting
   these parts, and since I do not have any HW and I am not familiar
   with this code/HW I think its best left to someone else.)

Except for the issues mentioned above, I have ported all drivers
necessary to run MAKEALL ppc/arm without errors and warnings. Many
drivers were trivial to port, but some were not so trivial. The
following drivers must be examined carefully and maybe rewritten to
some degree:
 cpu/ppc4xx/ndfc.c
 cpu/arm926ejs/davinci/nand.c
 board/delta/nand.c
 board/zylonite/nand.c
Signed-off-by: NWilliam Juul <william.juul@tandberg.com>
Signed-off-by: NStig Olsen <stig.olsen@tandberg.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Use CONFIG_NUM_CPUS to match existing define used by 86xx.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NJon Loeliger <jdl@freescale.com>

This is needed because we will be possibly be locating
devices at physical addresses above 32bits, and the asm
preprocessing does not appear to deal with ULL constants
properly. We now call write_bat in lib_ppc/bat_rw.c.
Signed-off-by: NBecky Bruce <becky.bruce@freescale.com>
Acked-by: NJon Loeliger <jdl@freescale.com>

Correct the mx31_gpio_mux() function to allow changing all i.MX31 IOMUX
contacts instead of only the first 256 ones as is the case prior to
this patch.

Add missing MUX_* macros and update board files to use the new macros.
Signed-off-by: NMagnus Lilja <lilja.magnus@gmail.com>

Signed-off-by: NStefan Roese <sr@denx.de>

And in the process eliminate some duplicate register defines.
Signed-off-by: NKenneth Johansson <kenneth@southpole.se>

On ADS5121 when booting linux the following errors are seen:
    Unable to update property /soc5121@80000000:bus-frequency, err=FDT_ERR_NOTFOUND
    Unable to update property /soc5121@80000000/ethernet@2800:local-mac-address, err=FDT_ERR_NOTFOUND
    Unable to update property /soc5121@80000000/ethernet@2800:address, err=FDT_ERR_NOTFOUND

This is caused by ft_cpu_setup trying to deal with
both old and new soc node naming.  This patch
fixes this by being smarter about what to
fixup.

Also do soc node fixups by compatible instead of by path.
A new board config called OF_SOC_COMPAT defined
to be "fsl,mpc5121-immr" replaces the old
OF_SOC node path that was defined to be "soc@80000000".

Old device trees still work, but the compatiblity
is conditional on CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
which is on by default in include/configs/ads5121.h.
Signed-off-by: NJohn Rigby <jrigby@freescale.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NMatvejchikov Ilya <matvejchikov@gmail.com>

The Hammerhead platform is built around a AVR32 32-bit microcontroller
from Atmel.  It offers versatile peripherals, such as ethernet, usb
device, usb host etc.

The board also incooperates a power supply and is a Power over Ethernet
(PoE) Powered Device (PD).

Additonally, a Cyclone III FPGA from Altera is integrated on the board.
The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two
DDR2 SDRAM interfaces, which will cover even the most exceptional need
of memory bandwidth. Together with the onboard video decoder the board
is ready for video processing.

For more information see: http:///www.miromico.com/hammerheadSigned-off-by: NJulien May <mailinglist@miromico.ch>
[haavard.skinnemoen@atmel.com: various small fixes and adaptions]
Signed-off-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com>

Support for the adsvix was originally provided by Applied Data
Systems (ADS), inc., now EuroTech, Inc.
The board never shipped aside from some sample boards.
Signed-off-by: NAdrian Filipi <adrian.filipi@eurotech.com>

Use CFG_MIPS_TIMER_FREQ when computing the baudrate divisor
on alchemy cpus.
Signed-off-by: NWolfgang Ocker <weo@reccoware.de>
Signed-off-by: NShinya Kuribayashi <skuribay@ruby.dti.ne.jp>

Signed-off-by: NMichal Simek <monstr@monstr.eu>

This patch fixes a problem with incorrect MODTx (On Die Termination)
setup for a configuration with multiple DIMM's and multiple ranks.
Without this change Katmai was unable to boot Linux with DDR2 frequency
>= 533MHz and mem>=3GB. With this patch Katmai successfully boots Linux
with DDR2 frequency = 640MHz and mem=4GB.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

-This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by  Stefan Roese
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: NStefan Roese <sr@denx.de>

The L2 size detection code was a bit confusing and we kept having to add
code to it to handle new processors.  Change the sense of detection so we
look for the older processors that aren't changing.

Also added support for 1M cache size on 8572.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>