rmobile/lowlevel_init_ca15.S are common in r8a7790, r8a7791 and r8a7794 of
rmobile SoCs.  The initialize L2 cache in lowlevel_init_ca15.S only needed
for Cortex-A15. The r8a7794 is Cortex-A7, not Cortex-A15.
This adds Skip to initialize L2 cache when r8a7794.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

rmobile/lowlevel_init_ca15.S are common in r8a7790 and r8a7791 of
rmobile SoC. But L2 cache of r8a7791 does not use L2CTLR[5].
This adds fix to set L2CTLR [5] only when the r8a7790.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

This removes duplicate initialization of l2ctlr.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

L2CTLR only need to update for cluster 0.
This changes L2CTLR to initialize only when cluster is 0.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Renesas R8A7790 is CPU with Cortex-A7 and A15.
This supports the basic register definition and GPIO and
framework of PFC.
Signed-off-by: NKouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: NRyo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: NHisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>