In case of multilib-enabled toolchains if default architecture differ from
the one examples are being built for linker will fail to link example object
files with libgcc of another (non-compatible) architecture.

Interesting enough for years in main Makefile we used CFLAGS/c_flags for this
but not for examples.

So fixing it now.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denx <wd@denx.de>
Acked-by: NWOlfgang Denk <wd@denx.de>
Acked-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Entry for dfu subsystem have been added to doc/git-mailrc file
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>

This is currently the only x86 board.
Signed-off-by: NSimon Glass <sjg@chromium.org>

In 71689776 we made calls to check_and_invalidate_dcache_range()
conditional on !CONFIG_SYS_FSL_ESDHC_USE_PIO.  Only define this function
in this case as well.
Signed-off-by: NTom Rini <trini@ti.com>

The implementation of mmc_select_hwpart() was cribbed from do_mmcops().
Update do_mmcops() to call mmc_select_hwpart() to avoid duplication.

<panto> Manual patch update due to patch order.
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This enables specifying which eMMC HW partition to target for any U-Boot
command that uses the generic get_partition() function to parse its
command-line arguments.
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Some device types (e.g. eMMC) have hardware-level partitions (for eMMC,
separate boot and user data partitions). This change allows the user to
specify the HW partition they wish to access when passing a device ID to
U-Boot Commands such as part, ls, load, ums, etc.

The syntax allows an optional ".$hwpartid" to be appended to the device
name string for those commands.

Existing syntax, for MMC device 0, default HW partition ID, SW partition
ID 1:

ls mmc 0:1 /

New syntax, for MMC device 0, HW partition ID 1 (boot0), SW partition
ID 2:

ls mmc 0.1:2 /

For my purposes, this is most useful for the ums (USB mass storage
gadget) command, but there's no reason not to allow the new syntax
globally.

This patch adds the core support infra-structure. The next patch will
provide the implementation for MMC.
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

All the sub-commands start with the main command name, but it was
missing from one of the help texts.

<panto> typos fix.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NTom Rini <trini@ti.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

This sub-command adds support for the RPMB partition of an eMMC:
* mmc rpmb key <address of the authentication key>
  Programs the authentication key in the eMMC This key can not
  be overwritten.
* mmc rpmb read <address> <block> <#count> [address of key]
  Reads <#count> blocks of 256 bytes in the RPMB partition
  beginning at block number <block>. If the optionnal
  address of the authentication key is provided, the
  Message Authentication Code (MAC) is verified on each
  block.
* mmc rpmb write <address> <block> <#count> <address of key>
  Writes <#count> blocks of 256 bytes in the RPMB partition
  beginning at block number <block>. The datas are signed
  with the key provided.
* mmc rpmb counter
  Returns the 'Write counter' of the RPMB partition.

The sub-command is conditional on compilation flag CONFIG_SUPPORT_EMMC_RPMB
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NPierre Aubert <p.aubert@staubli.com>
CC: Wolfgang Denk <wd@denx.de>

User's confirmation is asked in different commands. This commit adds a
function for such confirmation.
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NPierre Aubert <p.aubert@staubli.com>

This patch adds functions for read, write and authentication
key programming for the Replay Protected Memory Block partition
in the eMMC.
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NPierre Aubert <p.aubert@staubli.com>

MMC switch command for unsupported feature (e.g. bus width) sets a switch
error bit in card status. This bit should be checked, and, if it's set,
no access with new controller settings should be performed.
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NAndrew Gabbasov <andrew_gabbasov@mentor.com>

mmc_init() doesn't call get_timer() anymore if MMC is already
initialized.

<panto> Minor formatting fix.
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>

Since B&R boards uses only MMC-Controller #1, it only
wastes time if we initialize #0 first to see that there is nothing.

Cc: <trini@ti.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>

When configure the fsl_esdhc driver to PIO mode by defining
"CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail.

Two bugs in the driver to cause the issue:
1. The read buffer was invalidated after reading from DATAPORT register,
which should be only applied to DMA mode. The valid data in cache was
overwritten by physical memory.
2. The watermarks are not set in PIO mode, will cause according state not
be set.
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NYe.Li <B37916@freescale.com>

Added support to load a bitstream image in chunks by reading it in
chunks from SD/MMC.
Command format:
loadfs [dev] [address] [image size] [blocksize] <interface>
       [<dev[:part]>] <filename>
Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use new fpga commands for loading partial bitstreams.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Do not do partial bitstream detection based on bitstream
size and use bitstream_type argument which is passed
from the fpga core.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Added support to load partial bitstreams.
The partial bitstreams can be loaded using the below commands
Commands:
fpga loadp <dev> <addr> <size>
fpga loadbp <dev> <addr> <size>
The full bit streams can be loaded using the
old commands(fpga load and fpga loadb).
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Guard the LOADMK functionality with config to provide
an option to enable or disable it.
Enable it for all platforms in mainline which enable CONFIG_CMD_FPGA.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Fix typo in CMD_FPGA command enabling.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Conflicts:
	boards.cfg

Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).

Apply command "tools/reformat.py -i -d '-' -s 8 <boards.cfg
>boards0.cfg && mv boards0.cfg boards.cfg" in preparation of
pull request from ARM to main tree.

The new 768KB u-boot image size requires changes for
SRIO/PCIE boot. These addresses need to be updated to
appropriate locations.

The updated addresses are used to configure the SRIO/PCIE
inbound windows for the boot, and they must be aligned
with the window size based on the SRIO/PCIE modules requirement.
So for the 768KB u-boot image, the inbound window cannot be set
with 0xfff40000 base address and 0xc0000 size, it should be
extended to 1MB size and the base address can be aligned with
the size.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

AFAICT, c=ffe does nothing and was a typo from the original commit
d1712369 "powerpc/p4080: Add support
for the P4080DS board" and just kept on getting duplicated
in subsequently added board config files.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Acked-by: NEdward Swarthout <ed.swarthout@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

In case of secure boot from NAND, CSPR and FTIM settings are
same as non-secure NAND boot. CSPR0 is configured as NAND and
CSPR1 is configured as NOR.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

P1020 SoC which has two USB controllers, but only first one is used
on this platform.
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Signed-off-by: NSandeep Singh <Sandeep@freescale.com>
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T4160RDB shares the same platform as T4240RDB. T4160 is
a low power version of T4240, with the eight e6500 cores,
two DDR3 controllers, and same peripheral bus interfaces.
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T104xrdb has several sleep management signals that are used for deep
sleep. They are enabled by OS to enter deep sleep and should be
disabled by u-boot when cores wake up.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>