- 02 11月, 2018 3 次提交
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由 Marek Vasut 提交于
Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire 64bit DRAM space as cachable. On CortexA57, this might result in odd side effects, where the CPU tries to prefetch from those areas and if there is no DRAM backing them, CPU bus hang can happen. This patch fixes it by generating the mem_map structure based on the actual memory layout obtained from the DT, thus not marking areas without any DRAM behind them as cachable. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Fixes: c1ec3476 ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3") Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add definition of the POCCTRL register and bits therein to R8A77990 E3 pincontrol driver. This allows the pincontrol driver to configure SDHI pin voltage according to power-source DT property. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Use fixed 4bit size for generating the DRV register element mask, not the size of the value, which can be smaller. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- 01 11月, 2018 1 次提交
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- 31 10月, 2018 4 次提交
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由 Simon Goldschmidt 提交于
Using imply for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION instead of select ensures we can build without partition support (used to build a network boot only version of SPL and U-Boot). Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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由 Stefan Roese 提交于
Commit 768f23dc ("ARM: socfpga: Put stack at the end of SRAM") broke those socfpga boards that keep the bootcounter at the end of the internal SRAM as the bootcounter needs 8 bytes by default and thus the very first SPL call to board_init_f_alloc_reserve overwrites the bootcounter. This patch allows to move the initial stack pointer down a bit by checking if CONFIG_SYS_BOOTCOUNT_ADDR is located in the internal SRAM area and then using this address as location for the start of the stack pointer. No new macros / defines are added by this approach. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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由 Simon Goldschmidt 提交于
The 'status' variable in 'socfpga_load()' for both gen5 and arria10 is of type 'unsigned long' while it is always used as 'int' only. Change it to 'int'. Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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git://git.denx.de/u-boot-mpc85xx由 Tom Rini 提交于
Workaround and bug fix for Freescale PowerPC Add workaround for Freescale USB erratum A005275. Correct RCW macros for T1080.
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- 30 10月, 2018 4 次提交
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由 Bin Meng 提交于
Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NPoonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Bin Meng 提交于
Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NPoonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Chris Packham 提交于
Workaround makes FS as default mode on all affected socs. Add support to check erratum-A005275 validity for an soc. This info is required to determine whether a given soc is affected by this erratum. Add quirk for this erratum "has_fsl_erratum_a005275" . This quirk is used to enable workaround for the errata Force FS mode as default by: - making EPS as FS - setting PFSC bit to disable HS chirping This workaround can be disabled by mentioning "no_erratum_a005275" in hwconfig string Signed-off-by: NChris Packham <judge.packham@gmail.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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- 29 10月, 2018 7 次提交
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由 Andre Przywara 提交于
At the moment we rely on the infamous get_ram_size() function to learn the actual DRAM size in U-Boot proper. This function has two issues: 1) It only works if the DRAM size is a power of two. We start to see boards which have 3GB of (usable) DRAM, so this does not fit anymore. 2) As U-Boot has no notion of reserved memory so far, it will happily ride through the DRAM, possibly stepping on secure-only memory. This could be a region of DRAM reserved for OP-TEE or some other secure payload, for instance. It will most likely crash in that case. As the SPL DRAM init routine has very accurate knowledge of the actual DRAM size, lets propagate this wisdom to U-Boot proper. We re-purpose a currently reserved word in our SPL header for that. The SPL itself stores the detected DRAM size there, and bumps the SPL header version number in that case. U-Boot proper checks for a valid SPL header and a high enough version number, then uses the DRAM size from there. If the SPL header field is not sufficient, we fall back to the old DRAM scanning routine. Part of the DRAM might be present and probed by SPL, but not accessible by the CPU. They're restricted in the main U-Boot binary, when accessing the DRAM size from SPL header. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Icenowy Zheng 提交于
Allwinner 64-bit SoCs can use 4GiB DRAM chip, however their memory map has only allocated 3GiB for DRAM, so only 3GiB of the DRAM is accessible. Add a Kconfig option for the maximum accessible DRAM. For A80 it should be a much higher value (8GiB), but as I have no A80 device to test and originally U-Boot only supports 2GiB DRAM on A80, it currently still falls under the 2GiB situation. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Reviewed-by: NAndre Przywara <andre.przywara@arm.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Icenowy Zheng 提交于
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of external DRAM, however the size of DRAM part in the MMU translation table is still 2GiB. Change the size of DRAM part in MMU table to 3GiB. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Reviewed-by: NAndre Przywara <andre.przywara@arm.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Andre Przywara 提交于
So far we have two users which want to look at the SPL header. We will get more in the future. Refactor the existing SPL header checks into a common function, to simplify reusing the code. Now that this is easy, add proper version checks to the DT name parsing. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Acked-by: NJagan Teki <jagan@openedev.com>
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由 Andre Przywara 提交于
On Allwinner SoCs we use some free bytes at the beginning of the SPL image to store various information. We have a version byte to allow updates, but changing this always requires all tools to be updated as well. Introduce the concept of semantic versioning [1] to the SPL header: The major part of the version number only changes on incompatible updates, a minor number bump indicates backward compatibility. This patch just documents the major/minor split, adds some comments to the header file and uses the versioning information for the existing users. [1] https://semver.orgSigned-off-by: NAndre Przywara <andre.przywara@arm.com> Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Acked-by: NJagan Teki <jagan@openedev.com>
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由 Icenowy Zheng 提交于
The Pine A64 Plus/non-Plus model detection code is now built on all 64-bit ARM SoCs, even if the code cannot be triggered when H5/H6 is in use. Disable them when the board is Pine A64 by adding a Kconfig option that is only selected on Pine A64. On GCC 7.3.1 this makes the size of the function reduces 184 bytes, and saves a 104 byte strstr() function, then makes SPL on H6 succeed to build. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Reviewed-by: NAndre Przywara <andre.przywara@arm.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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- 28 10月, 2018 7 次提交
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由 Patrick Delaunay 提交于
Complete in the drivers directory the work started with commit 83d290c5 ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Bin Meng 提交于
Since commit 80df194f ("x86: detect unsupported relocation types"), an error message is seen on QEMU x86 target during boot: do_elf_reloc_fixups32: unsupported relocation type 0x1 at fff841f0, offset = 0xfff00087 do_elf_reloc_fixups32: unsupported relocation type 0x2 at fff841f8, offset = 0xfff00091 Check offset 0xfff00087 and 0xfff00091 in the u-boot ELF image, fff00087 000df401 R_386_32 00000000 car_uninit fff00091 000df402 R_386_PC32 00000000 car_uninit we see R_386_32 and R_386_PC32 relocation type is generated for symbol car_uninit, which is declared as a weak symbol in start.S. However the actual weak symbol implementation ends up nowhere. As we can see below, it's *UND*. $ objdump -t u-boot | grep car_uninit 00000000 w *UND* 00000000 car_uninit With this fix, it is normal now. $ objdump -t u-boot | grep car_uninit fff00094 w F .text.start 00000001 car_uninit Reported-by: NHannes Schmelzer <hannes@schmelzer.or.at> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: NHannes Schmelzer <oe5hpm@oevsv.at>
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由 Stefan Roese 提交于
The build breaks because its not fitting the U-Boot binary into the ROM image. So lets move VGA BIOS a bit to make room for the grown U-Boot binary. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
To enable the root device selection (kernel cmd-line) via PARTUUID, this patch enables CMD_PART on all missing theadorable-x86 boards and changes the default environment to generate the root=PARTUUID string automatically. This fixes problems that have been noticed on systems with multiple SATA/AHCI controller connected via PCIe, where the device name for the root device / partition (/dev/sdaX) was incorrect. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
This is needed for the PCIe hotplug to work correctly on some boards with the newer Linux kernel versions. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
To allow bigger 64 bit prefetchable PCI regions in Linux, this patch changes the base address and range of the ACPI area passed to Linux. BayTrail can only physically access 36 bit of PCI address space. So just chaning the range without changing the base address won't work here, as 0xf.ffff.ffff is already the maximum address. With this patch, a maximum of 16 GiB of local DDR is supported. This should be enough for all BayTrail boards though. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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- 26 10月, 2018 2 次提交
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由 Tom Rini 提交于
To help with size constraints, enable thumb2 when building. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 25 10月, 2018 12 次提交
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由 Peng Fan 提交于
Fix below build warning. arch/arm/dts/fsl-imx8qxp-mek.dtb: Warning (avoid_unnecessary_addr_size): /regulators: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Introduce a new script to check whether file exists and use that check in Makefile to avoid break CI system. The script return 1 when the required files not exists, return 0 when files exists. The script will ignore check to u-boot-dtb.bin, because if there is something wrong to generate u-boot-dtb.bin, there must be some code error. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Anatolij Gustschin 提交于
Add compatible property and enable the FEC ipg clock when probing on i.MX8X. Add specific function for reading FEC clock rate via clock driver when configuring MII speed register. Allow FEC_MXC selection for i.MX8. Signed-off-by: NAnatolij Gustschin <agust@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Baruch Siach 提交于
The default Linux PHY reset delay is 10ms. This is also the requirement for Marvell 88E151x PHYs, which are likely to be used with this Ethernet MAC. Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Baruch Siach 提交于
The dm_gpio_set_value() call sets the logical level of the GPIO signal. That is, it takes the GPIO_ACTIVE_{LOW,HIGH} property into account. The driver needs to assert the reset, and then deassert it. Not the other way around. Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Priyanka Jain 提交于
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Martin Fuzzey 提交于
The DT property "phy-mode" already provides the transceiver type. Use it so that we do not have to also set CONFIG_FEC_XCV_TYPE Signed-off-by: NMartin Fuzzey <martin.fuzzey@flowbird.group> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Martin Fuzzey 提交于
Configure the phy regulator if defined by the "phy-supply" DT phandle. Signed-off-by: NMartin Fuzzey <martin.fuzzey@flowbird.group> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Martin Fuzzey 提交于
The DT binding says: - phy-reset-duration : Reset duration in milliseconds. Should present only if property "phy-reset-gpios" is available. Missing the property will have the duration be 1 millisecond. Numbers greater than 1000 are invalid and 1 millisecond will be used instead. However the current code: - clamps values greater than 1000ms to 1000ms rather than 1. - does not initialize the delay if the property does not exist (else clause mismatch) - returns an error if phy-reset-gpios is not defined Fix all this and simplify by using dev_read_u32_default() Signed-off-by: NMartin Fuzzey <martin.fuzzey@flowbird.group> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Martin Fuzzey 提交于
The DT binding says that phy-reset-duration is in ms, but the driver currently uses udelay(). Switch to mdelay() to fix this. Signed-off-by: NMartin Fuzzey <martin.fuzzey@flowbird.group> Reviewed-by: NMichael Trimarchi <michael@amarulasolutions.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Jeremy Gebben 提交于
If the phy reports a valid firmware version and doesn't indicate a fault, skip loading the firmware. This allows the same image to be used on boards that have firmware storage and those that do not. Signed-off-by: NJeremy Gebben <jgebben@sweptlaser.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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