This patch adds an alterative SPL version of atmel_serial_enable_clk().
This enables the usage of this driver without full clock support (in
drivers and DT nodes). This saves some space in the SPL image.

Please note that this fixed clock support is only added to the SPL code
in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL
should not be affected.

This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART
input clock. It defaults to 132096000 for ARCH_AT91 but can be set to
a different value if needed.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>

This patch adds a call to spl_early_init() to board_init_f() which is
needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for
the early SPL setup including the DTB setup for later usage.

Please note that this call might also be needed for non SPL_OF_CONTROL
board, like the smartweb target. But smartweb fails to build with this
call because its binary grows too big. So I disabled it for these kind
of targets for now.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: NHeiko Schocher <hs@denx.de>

Make sure that lowlevel_init is not compiled when
CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: NHeiko Schocher <hs@denx.de>

Migrate the following options to CONFIG_DM:
  CONFIG_DM_GPIO
  CONFIG_DM_MMC
  CONFIG_DM_ETH
  CONFIG_DM_SERIAL
  CONFIG_DM_USB
Signed-off-by: NIlko Iliev <iliev@ronetix.at>

When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional
chip id. The check if the cpu is sama5d2 was changed from a preprocessor
definition (inlining a call to 'get_chip_id()') to a C function,
probably to not call get_chip_id twice?

That however broke a check in the macb ethernet driver. That driver is
more generic and also used for other platforms. I suppose this solution
was implemented to use it in 'gem_is_gigabit_capable()', without having
to stricly depend on the at91 platform:

	#ifndef cpu_is_sama5d2
	#define cpu_is_sama5d2() 0
	#endif

That only works as long as cpu_is_sama5d2 is a preprocessor definition.
(The same is still true for sama5d4 by the way.) So this is a straight
forward fix for the workaround.

The not working check on the SAMA5D2 CPU lead to an issue on a custom
board with a LAN8720A ethernet phy connected to the SoC:

	=> dhcp
	ethernet@f8008000: PHY present at 1
	ethernet@f8008000: Starting autonegotiation...
	ethernet@f8008000: Autonegotiation complete
	ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff)
	BOOTP broadcast 1
	BOOTP broadcast 2
	BOOTP broadcast 3
	BOOTP broadcast 4
	BOOTP broadcast 5
	BOOTP broadcast 6
	BOOTP broadcast 7
	BOOTP broadcast 8
	BOOTP broadcast 9
	BOOTP broadcast 10
	BOOTP broadcast 11
	BOOTP broadcast 12
	BOOTP broadcast 13
	BOOTP broadcast 14
	BOOTP broadcast 15
	BOOTP broadcast 16
	BOOTP broadcast 17

	Retry time exceeded; starting again

Notice the wrong reported link speed, although both SoC and phy only
support 100 MBit/s!

The real issue on reliably detecting the features of that cadence
ethernet mac IP block, is probably more complicated, though.

Fixes: 245cbc58 ("ARM: at91: Get the Chip ID of SAMA5D2 SiP")
Signed-off-by: NAlexander Dahl <ada@thorsis.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.

Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]

So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.

Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.

[1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.htmlReported-by: NPablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

- i.MX8QXP-MEK ethernet fix

PHY cannot be detected unless we wait about 150 ms.
Signed-off-by: NAndrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>
Reviewed-by: NStefano Babic <sbabic@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

As per Linux kernel DT binding doc:
- phy-reset-post-delay : Post reset delay in milliseconds. If present then
  a delay of phy-reset-post-delay milliseconds will be observed after the
  phy-reset-gpios has been toggled. Can be omitted thus no delay is
  observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.
Signed-off-by: NAndrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>
Reviewed-by: NStefano Babic <sbabic@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Acked-by: NLukasz Majewski <lukma@denx.de>

This patch moves all instances of static "watchdog_dev" declarations to
the "data" section. This may be needed, as the BSS may not be cleared
in the early U-Boot phase, where watchdog_reset() is already beeing
called. This may result in incorrect pointer access, as the check to
"!watchdog_dev" in watchdog_reset() may not be true and the function
may continue to run.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
Reviewed-by: NMichal Simek <michal.simek@xilinx.com>

Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.
Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Tested-by: NLukasz Majewski <lukma@denx.de>

Fixes for 2019.04

	- fix bashism for MX8
	- fix ethernet for MX53
	- fix docs for i.MX8

- Documentation fix

- Important Khadas VIM2 fix
- Build fix for macOS Mojave
- Build fix for gcc-4.7 for host tools.

Parts of the code are using C99 constructs (such as variables declared
inside loops), but also GNU extensions (such as typeof), so using
-std=gnu99 is necessary to build with older versions of gcc that don't
default to building with gnu99.

It fixes the following build failure:

./tools/../lib/crc16.c: In function "crc16_ccitt":
./tools/../lib/crc16.c:70:2: error: "for" loop initial declarations are only allowed in C99 mode
  for (int i = 0;  i < len;  i++)
  ^
./tools/../lib/crc16.c:70:2: note: use option -std=c99 or -std=gnu99 to compile your code

when building the host tools with gcc 4.7.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

The Khadas VIM2 defconfig was missing the USB PHY config and
two other misc configs to setup dram banks and call misc_init_r.
Align it on the other Amlogic SoC based boards defconfig.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs.

Fixes: 2960e27e ("phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers")
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Fix missing at91 boards and split the at91 in two categories:
at91 arm v7
at91 arm926esj
which are the two main cores for the at91 architecture.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

After the commit: "eth: dm: fec: Add gpio phy reset binding"
SHA1: efd0b791

The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).
Signed-off-by: NLukasz Majewski <lukma@denx.de>

Signed-off-by: NLukasz Majewski <lukma@denx.de>

After running tools/moveconfig.py it turned out that for various boards
there are an empty #ifdef statements.

Remove them to clean u-boot source code.
Signed-off-by: NLukasz Majewski <lukma@denx.de>

The ohci driver calls board_usb_init(), not usb_board_init().
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

Let the underline marker "=" fill the whole sentence for better
readability.
Signed-off-by: NFabio Estevam <festevam@gmail.com>

The DDR firmware binaries should be copied to '$(srctree)', so fix
a typo.
Signed-off-by: NFabio Estevam <festevam@gmail.com>

After building ATF it is needed to copy the generated bl31.bin file to
the U-Boot source tree.

Make this step explicit in the instructions.
Signed-off-by: NFabio Estevam <festevam@gmail.com>

Minor fixes for the Alt board and PHY use on Gen2.

- clk: sunxi: a10: Add CLK_AHB_GMAC

CLK_AHB_GMAC was suppose to be part of previous commit
"clk: sunxi: Implement A10 EMAC clocks" add it so-that
we can get rid of sunxi_set_gate warning on boot message.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Use a single '=' to test string equality for compatibility with non-bash
shells. Otherwise, if /bin/sh is dash, build fails:

./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator
WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Tested-by: NChris Spencer <christopher.spencer@sea.co.uk>

Fixes for 2019.01

	- pico-imx6ul: fix after conversion
	- engicam boards
	- pico-imx7d _ README due to hang with imx-usb-loader

Since commit 9e3c0174 ("pico-imx7d: Add LCD support") we started to
notice some hangs in U-Boot.

There is not an issue on such commit per se, but due to the LCD support
the current drawn is increased and this may cause issues when powering
pico-imx7d-pi from USB.

Some computers may be a bit strict with USB current draw and will
shut down their ports if the draw is too high.

The solution for that is to use an externally powered USB hub between the
board and the host computer.

Add such recommendation to the README file.
Signed-off-by: NFabio Estevam <festevam@gmail.com>

SRAM address used for bootcount on exiting code is erasing
previous count value when system reset from Linux. So use
the dedicated imx6 scratch register, GPR2 to preserve the
contents even if the system reset from Linux.

Fixes: 4eb9aa39 ("configs: imx6qdl_icore_mmc: Enable watchdog and bootcounter")
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: NShyam Saini <shyam.saini@amarulasolutions.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>

SPL on Engicam i.Core M6 boards enabled DM, so it would require some
malloc() pool before relocation in order to load U-Boot proper properly.

So, enable SPL malloc() pool of 0x2000 size similarly like what we have
used for icore mmc defconfigs.
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: NShyam Saini <shyam.saini@amarulasolutions.com>
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>

With UUID support, the root can now point to UUID.  This makes
swiching between mmc 0 and mmc 1 easier by simplying changing
mmcdev between 0 and 1.  From there, the scripts handle the rest.
Signed-off-by: NAdam Ford <aford173@gmail.com>

After the DM_MMC conversion the following eMMC boot error is observed:

U-Boot SPL 2019.04-rc4 (Mar 20 2019 - 18:53:28 +0000)
Trying to boot from MMC1
MMC Device 0 not found
spl: could not find mmc device 0. error: -19
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

This happens because the SPL code does not initialize the SDHC pins
and clock.

Fix it by moving the original eMMC initialization from U-Boot proper
to SPL.
Reported-by: NOtavio Salvador <otavio@ossystems.com.br>
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Tested-by: NFabio Berton <fabio.berton@ossystems.com.br>
Reviewed-by: NOtavio Salvador <otavio@ossystems.com.br>

Signed-off-by: NStefano Babic <sbabic@denx.de>

sunxi HDMI clock fix

Last-minute fixes for Rockchip for 2019.04:
- reverts the deprecation of the 'download-key' detection
  (with a full solution pending for the next release)
- applies a temporary fix for the 32bit pinctrl registers on the RK3288