1. 04 7月, 2011 3 次提交
    • A
      armv7: rename cache related CONFIG flags · e47f2db5
      Aneesh V 提交于
      Replace the cache related CONFIG flags with more meaningful
      names. Following are the changes:
      
      CONFIG_L2_OFF	     -> CONFIG_SYS_L2CACHE_OFF
      CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF
      CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF
      Signed-off-by: NAneesh V <aneesh@ti.com>
      V2:
       * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE
      V4:
       * Changed all three flags to the final names suggested as above
         and accordingly changed the commit message
      e47f2db5
    • A
      armv7: cache maintenance operations for armv7 · 2c451f78
      Aneesh V 提交于
      - Add a framework for layered cache maintenance
      	- separate out SOC specific outer cache maintenance from
      	  maintenance of caches known to CPU
      
      - Add generic ARMv7 cache maintenance operations that affect all
        caches known to ARMv7 CPUs. For instance in Cortex-A8 these
        opertions will affect both L1 and L2 caches. In Cortex-A9
        these will affect only L1 cache
      
      - D-cache operations supported:
      	- Invalidate entire D-cache
      	- Invalidate D-cache range
      	- Flush(clean & invalidate) entire D-cache
      	- Flush D-cache range
      - I-cache operations supported:
      	- Invalidate entire I-cache
      
      - Add maintenance functions for TLB, branch predictor array etc.
      
      - Enable -march=armv7-a so that armv7 assembly instructions can be
        used
      Signed-off-by: NAneesh V <aneesh@ti.com>
      2c451f78
    • A
      arm: make default implementation of cache_flush() weakly linked · 4c93da7c
      Aneesh V 提交于
      make default implementation of cache_flush() weakly linked so that
      sub-architectures can override it
      Signed-off-by: NAneesh V <aneesh@ti.com>
      4c93da7c
  2. 02 7月, 2011 7 次提交
  3. 01 7月, 2011 1 次提交
  4. 30 6月, 2011 1 次提交
  5. 29 6月, 2011 1 次提交
    • M
      cfi_flash: reverse geometry for newer STM parts · 4c2105cb
      Mike Frysinger 提交于
      For newer STM parts where CFI >= 1.1, there is a byte in the extended
      structure that declares the flash layout type (just like the AMD parts),
      so key off of that to find out when we need to reverse the geometry.
      
      This can be seen with M29W640 parts where U-Boot does:
      Bank # 1: CFI conformant FLASH (16 x 16)  Size: 8 MB in 135 Sectors
        AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22ED
        Erase timeout: 8192 ms, write timeout: 1 ms
        Buffer write timeout: 1 ms, buffer size: 16 bytes
      
        Sector Start Addresses:
        20000000   RO   20002000   RO   20004000   RO   20006000   RO   20008000   RO
        2000A000   RO   2000C000   RO   2000E000   RO   20010000   RO   20020000   RO
        ...
      
      But Linux does:
      physmap platform flash device: 00800000 at 20000000
      physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank.
                       Manufacturer ID 0x000020 Chip ID 0x0022ed
      physmap-flash.0: Swapping erase regions for top-boot CFI table.
      Signed-off-by: NMike Frysinger <vapier@gentoo.org>
      Signed-off-by: NStefan Roese <sr@denx.de>
      4c2105cb
  6. 28 6月, 2011 2 次提交
  7. 25 6月, 2011 3 次提交
  8. 23 6月, 2011 22 次提交