The attached patch is mainly cosmetic, allowing u-boot to
display the correct bootstrap option letter according to the
datasheets.

The original patch was extended with 405EZ support by Stefan
Roese.
Signed-off-by: NBenoit Monin <bmonin@adeneo.eu>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch undoes the patch by Jeff Mann with commit-id ada4697d. As
suggested by AMCC it is not recommended to dynamically change the EBC
speed after bootup. So we undo this change to be on the safe side.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds NAND booting support for the AMCC Bamboo eval board.
Since the NAND-SPL boot image is limited to 4kbytes, this version
only supports the onboard 64MBytes of DDR. The DIMM modules can't be
supported, since the setup code for I2C DIMM autodetection and
configuration is too big for this NAND bootloader.
Signed-off-by: NStefan Roese <sr@denx.de>

The U-Boot NAND booting support is now extended to support ECC
upon loading of the NAND U-Boot image.

Tested on AMCC Sequoia (440EPx) and Bamboo (440EP).
Signed-off-by: NStefan Roese <sr@denx.de>

This patch updates the "normal" Bamboo NOR booting port, so
that it is compatible with the coming soon NAND booting
Bamboo port.

It also enables the 2nd NAND flash on the Bamboo.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds hardware ECC support to the NDFC driver. It also
changes the register access from using the "simple" in32/out32
functions to the in_be32/out_be32 functions, which make sure
that the access is correctly synced. This is the only recommended
access to SoC registers in the current Linux kernel.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch updates the nand_ecc code to the latest Linux version.
The main reason for this is the more compact code. This makes
it possible to include the ECC code into the NAND bootloader
image (NAND_SPL) for PPC4xx.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

With the updated 44x DDR2 driver the Luan board now supports
ECC generation and checking.
Signed-off-by: NStefan Roese <sr@denx.de>

Add config option for 180 degree advance clock control as needed
for the AMCC Luan eval board.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NBartlomiej Sieka <tur@semihalf.com>

Enable redundant environment, add a MTD partition for it; also add env.
variable command for passing MTD partitions to the kernel command line.
Signed-off-by: NPiotr Kruszynski <ppk@semihalf.com>
Acked-by: NBartlomiej Sieka <tur@semihalf.com>

Allow passing longer command line to the kernel - useful especially
for passing MTD partition layout.
Signed-off-by: NPiotr Kruszynski <ppk@semihalf.com>
Acked-by: NBartlomiej Sieka <tur@semihalf.com>

Signed-off-by: NPiotr Kruszynski <ppk@semihalf.com>
Acked-by: NBartlomiej Sieka <tur@semihalf.com>

Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A
have a page write capability of two bytes", and "This device offers fast (1ms)
byte write". Add 3ms of extra delay.
Signed-off-by: NPiotr Kruszynski <ppk@semihalf.com>
Acked-by: NBartlomiej Sieka <tur@semihalf.com>

After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which
networking does not function. This commit switches PHY to TX mode by clearing
the FX_SEL bit of Mode Control Register. It also reverses commit
008861a2, i.e., a temporary workaround.
Signed-off-by: NGrzegorz Bernacki <gjb@semihalf.com>
Acked-by: NBartlomiej Sieka <tur@semihalf.com>

Signed-off-by: NPiotr Kruszynski <ppk@semihalf.com>
Acked-by: NBartlomiej Sieka <tur@semihalf.com>

Signed-off-by: NJan Wrobel <wrr@semihalf.com>
Acked-by: NBartlomiej Sieka <tur@semihalf.com>

Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining
them does not cause PCI or IPB clocks to run at the specified speed.
Instead, they configure divisors used to calculate said clocks. This
patch renames the defines according to their real function.
Signed-off-by: NGrzegorz Bernacki <gjb@semihalf.com>
Acked-by: NBartlomiej Sieka <tur@semihalf.com>

Signed-off-by: NJan Wrobel <wrr@semihalf.com>
Signed-off-by: NMarian Balakowicz <m8@semihalf.com>
Acked-by: NBartlomiej Sieka <tur@semihalf.com>

As pointed out by Bruce Adler <bruce.adler@acm.org> this patch
fixes a small bug in the 405EZ OCM initialization. Thanks for
spotting.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch updates the Acadia (405EZ) support for the new 1.1 board
revision. It also adds support for NAND FLASH via the 4xx NDFC.

Please note that the jumper J7 must be in position 2-3 for this
NAND support. Position 1-2 is for NAND booting only. NAND booting
support will follow later.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds support for 405 PPC's to the 4xx NAND driver
ndfc.c. This is in preparation for the new AMCC 405EZ.
Signed-off-by: NStefan Roese <sr@denx.de>

As spotted by Bruce Adler this patch fixes an initialization problem
for the 405EZ OCM.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefano Babic <sbabic@denx.de>

Because the Sequoia board does not boot with an EBC faster than 66MHz,
the clock divider are changed after the initial boot process.

This allows for maximum clocking speeds  to be achieved on newer boards.
Sequoia boards with 666.66 MHz processors require that the EBC divider
be set to 3 in order to start the initial boot process at a slower EBC
speed. After the initial boot process, the divider can be set back to 2,
which will cause the boards to run at 83.333MHz. This is backward
compatible with boards with 533.33 MHz processors, as these boards will
already be set with an EBC divider of 2.
Signed-off-by: NJeffrey Mann <mannj@embeddedplanet.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>