The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the
config option to make it less misleading. No functional change, just
a mechanical change done using the following script:

  git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \
  while read line ; do
    sed -i "s/USB_GADGET_S3C_UDC_OTG/USB_GADGET_DWC2_OTG/g" $line ;
  done
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
Tweak the comments in the driver to reflect this fact.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames the remaining S3C_* macros to match the
DWC2 naming.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames the local source files to dwc2_*c and
adjusts the Makefile to use the new names.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames the local header files to dwc2_*h and
adjusts the sources to use the new names.
Signed-off-by: NMarek Vasut <marex@denx.de>

Just change the driver name.
Signed-off-by: NMarek Vasut <marex@denx.de>

The extern statements are useless, remove them. Also remove the
extern ... controller, which is completely useless.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames the remaining local s3c_*() functions
to reflect this.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
The function s3c_udc_probe() is a special case and is not
renamed by this patch yet.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep0_*() functions to reflect this.
Signed-off-by: NMarek Vasut <marex@denx.de>

Just staticize the functions, they are not used outside of the file.
Signed-off-by: NMarek Vasut <marex@denx.de>

This function is local to s3c_udc_otg_xfer_dma.c , staticize it.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_request to reflect this.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_ep to reflect this.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_dev_*_ep to reflect this.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy
to make things more obvious and clear.
Signed-off-by: NMarek Vasut <marex@denx.de>

Most of the functions are local to the s3c_udc driver, remove them
from the s3c_udc.h header to stop those bits from propagating all
over the place. Instead, move all the private stuff into new private
s3c_udc_otg_priv.h header.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_reg to struct dwc2_usbotg_reg
to make things more obvious and clear.
Signed-off-by: NMarek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_udc to struct dwc2_udc to make
things more obvious and clear.
Signed-off-by: NMarek Vasut <marex@denx.de>

Rename the header file, so it's obvious which driver it's part of.
No functional change.
Signed-off-by: NMarek Vasut <marex@denx.de>

This fixes commit 1a37889b:
----------------------->8--------------------
eeprom: Pull out the RW loop

Unify the code for doing read/write into single function, since the
code for both the read and write is almost identical. This again
trims down the code duplication.
----------------------->8--------------------

where the same one routine is utilized for both EEPROM writing and
reading. The only difference was supposed to be a "read" flag which
in both cases was set with 1 somehow.

That lead to a missing delay in case of writing which lead to write
failure (in my case no data was written).
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
Acked-by: NMarek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>

This reverts commit e8f954a7, which
causes compiling errors on 32-bit hosts.
Acked-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
CC: Alex Porosanu <alexandru.porosanu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

uintptr_t which is a typdef for unsigned long is needed for creating
pointers (32 or 64 bit depending on Core) from 32 bit variables
storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *),
compiler gives a warning in case size of pointer on the core is 64 bit.

The typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
timeout might occur meanwhile. So pet the watchdog while operating on
the flash.
Signed-off-by: NAlexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.

In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.
Signed-off-by: NYork Sun <yorksun@freescale.com>

As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves
some memory from the end of ram, tracked by gd->ram_size. It is not
always the top of u-boot visible memory. Rewrite the macro with a
weak function to provide flexibility for complex calcuation. Legacy
use of this macro is still supported.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.

gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Secure memory is at the end of memory, separated and reserved
from OS, tracked by gd->secure_ram. Secure memory can host
MMU tables, security monitor, etc. This is different from PRAM
used to reserve private memory. PRAM offers memory at the top
of u-boot memory, not necessarily the real end of memory for
systems with very large DDR. Using the end of memory simplifies
MMU setup and avoid memory fragmentation.

"bdinfo" command shows gd->secure_ram value if this memory is
marked as secured.
Signed-off-by: NYork Sun <yorksun@freescale.com>

As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
[York Sun: Add commit message]
Reviewed-by: NYork Sun <yorksun@freescale.com>

Since the changes in a1e56cf6 the way that we had board_mmc_init()
structured for OMAP parts (so that we always report device 0) are no
longer functional.  For now, make the case of booting from the second
device initialize both devices (we have no devices that only have the
second device as MMC).  A further rework and consolidation of the
functions should be done at a later date.

Tested on Beaglebone Black (SD and eMMC boot).
Reported-by: NVagrant Cascadian <vagrant@debian.org>
Signed-off-by: NTom Rini <trini@konsulko.com>

In order to support boot from multiple devices through board_boot_order,
it's necessary to use the block number of a device.

The use of a hard-coded 0 for the device number also creates a need
to re-order block devices for use in SPL like this:
	http://git.denx.de/?p=u-boot.git;a=blob;f=board/freescale/mx6slevk/mx6slevk.c;hb=HEAD#l195Signed-off-by: NEric Nelson <eric@nelint.com>