Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: NTom Rini <trini@ti.com>
Acked-by: NMarek Vasut <marex@denx.de>

Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: NTom Rini <trini@ti.com>

Some editors such as Emacs can highlight source files.
But their parser algorithm is not perfect.

If you use one double-quotation alone, some editor cannot
handle it nicely and mark source lines as a string by mistake.

It is preferable to use two double-quotations as a pair.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

The default value of CONFIG_SYS_FSL_TBCLK_DIV is 16.

So, update its value as default.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

A new valid setting case added for fman1, it uses platform frequency.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

This adds a SPI framework for people to hook up simulated SPI clients.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

The new name is longer but more clearly related to sandbox.

This is in a separate patch within the same series since some comments on the
SPI series rely on it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHung-ying Tyan <tyanh@chromium.org>

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

In order to get the very same value for legacy pin definitions and new gpio
definitions set the legacy PIN_BASE to 0.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

This patch define new names for GPIO pins on at91 devices. Follow up patches
will convert the whole infrastructure to use these new definitions.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Tested-by: NBo Shen <voice.shen@atmel.com>

Current LDS files /DISCARD/ a lot of sections when linking ELF
files, causing diagnostic tools such as readelf or objdump to
produce partial output. Keep all section at link stage, filter
only at objcopy time so that .bin remains minimal.
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

The lower 5 bit of MVBAR is UNK/SBZP.
So, Monitor Vector Base Address must be 32-byte aligned.
On the other hand, the secure monitor handler does not need
32-byte alignment.

This commit moves ".algin 5" directive to the correct place.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andre Przywara <andre.przywara@linaro.org>
Acked-by: NAndre Przywara <andre.przywara@linaro.org>

This patch change the per_clocks_enable() function used in OMAP3
code to enable peripherals clocks. Only required clock should be
activated. So if the board use the uart(x) as a console we need
to activate it. The Board's config should include define to enable
every subsystem that the board use. For a complete list
of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER
should be checked.
Right now the bootloader can enable and disable clocks for:
uart(x) using CONFIG_SYS_NS16550
gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 }
i2c bus using CONFIG_DRIVER_OMAP34XX_I2C.

Not required gptimer(x) and mcbsp(x) for booting are disabled by default and
are not supported by any define.
Their activation need to included in the per_clocks_enable if the
peripheral is included. Not booting board should enable the peripheral
clock connected to their driver
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>

This patch fix following errors and warnings

spl_boot.c: In function 'exynos_spi_copy':
spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function)
spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in
spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function)
spl_boot.c: In function 'copy_uboot_to_ram':
spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable]
spl_boot.c: At top level:
spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function]
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>

Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>

These defines didn't use anywhere.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Acked-by: NAlexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

The "int" type is right.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

MPC8349 has been using mpc85xx DDR driver through a symbolic link to
mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set
under driver/ddr/fsl/, the link is replaced by referring driver
directly. We now can simply enable the macro and use the driver.
Other mpc83xx SoCs still use their own driver.
Signed-off-by: NYork Sun <yorksun@freescale.com>

MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.
Signed-off-by: NDave Liu <daveliu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NHardik Patel <hardik.patel@volansystech.com>

MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at
0x01C14114
Signed-off-by: NViktar Palstsiuk <viktar.palstsiuk@promwad.com>

This patch add the OMAP34XX_UART4 memory address
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>

Certain EFUSE settings were recommended for the first
four lots of OMAP5 ES1.0 silicon. These are not applicable
for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings.
Reported-by: NGriffis, Brad <bgriffis@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Adds the necessary PRCM and Control register information for
SATA on DRA7xx.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Add platform glue logic for the SATA controller.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Adds the necessary PRCM and Control register information for
SATA on OMAP5.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is
a driver for the Pipe3 PHY.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

When core power domain hits oswr, then DDR3 memories does not come back
while resuming. This is because when EMIF registers are lost, then the
controller takes care of copying the values from the shadow registers.
If the shadow registers are not updated with the right values, then this
results in incorrect settings while resuming. So updating the shadow registers
with the corresponding status registers here during the boot.
Signed-off-by: NSricharan R <r.sricharan@ti.com>

Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Signed-off-by: NSricharan R <r.sricharan@ti.com>

A generic is_dra7xx cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.
Signed-off-by: NSricharan R <r.sricharan@ti.com>

Based on the definitive guide to EMIF configuration[1] certain registers
that we have been modifying (and are documented registers) should be
left in their reset values rather than modified.  This has been tested
on AM335x GP EVM and Beaglebone White.

[1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Javier Martinez Canillas <javier@dowhile0.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: NTom Rini <trini@ti.com>
Tested-by: NMatt Porter <matt.porter@linaro.org>

The struct incorrectly referenced SMPS1 for all three power
domains. Fixed this by using SMPS2 and SMPS5 as appropriate.

Add some comments and choose voltage values that correspond
to voltage selection codes.
Signed-off-by: NLubomir Popov <l-popov@ti.com>

Add cm_t335 board directory, config file. Enable build.
Signed-off-by: NIlya Ledvich <ilya@compulab.co.il>
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
[trini: Adapt Makefile]
Signed-off-by: NTom Rini <trini@ti.com>

Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: NChin Liang See <clsee@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

This patch implements a custom spi_copy funtion to copy u-boot from SF
to RAM. This is faster then iROM spi_copy funtion as this runs spi at
50Mhz and also in WORD mode of operation.

Changed a printf in pinmux.c to debug just to avoid the compilation
error in SPL.
Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: NTom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Renesas ARM SoCs (R-Mobile, R-Car) are armv7 only.
This drops armv5 supprt from PLATFORM_CPPFLAGS and remove config.mk of
rmobile.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

The kzm9g board fails in building with -march=armv7-a.
This fixs this problem by converting to do_div().

-----
USE_PRIVATE_LIBGCC=yes ./MAKEALL kzm9g
...
arch/arm/cpu/armv7/rmobile/librmobile.o: In function `get_time_us':
arch/arm/cpu/armv7/rmobile/timer.c:41: undefined reference to `__aeabi_uldivmod'
arch/arm/cpu/armv7/rmobile/librmobile.o: In function `get_time_ms':
arch/arm/cpu/armv7/rmobile/timer.c:47: undefined reference to `__aeabi_uldivmod'
-----
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Tetsuyuki Kobayashi <koba@kmckk.co.jp>

The koelsch board has R8A7791, 2GB DDR3-SDRAM, USB,
Quad SPI, Ethernet, and more.

This patch supports the following functions:
 - DDR3-SDRAM
 - SCIF
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NHisashi Nakamura <hisashi.nakamura.ak@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>